SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF

Abstract

A substrate structure including a carrier and a substrate is provided. The carrier includes a release layer, a dielectric layer and a metal layer. The dielectric layer is disposed between the release layer and the metal layer. The substrate includes a packaging region and a peripheral region. The peripheral region is connected to the packaging region and surrounds the packaging region. The peripheral region or the packaging region has a plurality of through holes. The substrate is disposed on the carrier. The release layer is located between the substrate and the dielectric layer. The release layer and the dielectric layer are filled in the through hole such that the substrate is separably attached to the carrier.

Claims

1. A substrate structure for packaging a chip, comprising: a carrier, comprising a release layer, a dielectric layer, and a metal layer, wherein the dielectric layer is disposed between the release layer and the metal layer; and a substrate, comprising a packaging region and a peripheral region, wherein the peripheral region is connected to the packaging region and surrounds the packaging region, the packaging region has a plurality of through holes, the substrate is disposed on the carrier, the release layer is located between the substrate and the dielectric layer, and the release layer and the dielectric layer are filled into the through holes located at the packaging region, such that the substrate is separably attached to the carrier, wherein the chip is configured to directly contact the release layer filled into the through holes, and the substrate is configured to be separated from the release layer and the carrier to expose the back surface of the chip after packaging the chip on the substrate.

2. The substrate structure as claimed in claim 1, wherein the substrate further comprises a plurality of pads and a patterned solder mask, the pads are disposed on an upper surface of the substrate and located within the packaging region for packaging the chip, the pads are disposed around the through holes, and the patterned solder mask covers the upper surface and exposes the pads.

3. The substrate structure as claimed in claim 1, wherein the dielectric layer directly contacts with the release layer, the release layer contacts with inner walls of the through holes, and a first top surface of the release layer in the through holes is substantially coplanar with a second top surface of the patterned solder mask.

4. The substrate structure as claimed in claim 1, wherein the chip is disposed in the packaging region and covering one of the through holes to contact the release layer.

5. The substrate structure as claimed in claim 2, wherein the chip is electrically connected to the pads by a plurality of wires.

6. The substrate structure as claimed in claim 1, wherein a material of the release layer comprises an aluminum foil or a polyimide (PI) film.

7. The substrate structure as claimed in claim 1, wherein the substrate is a single-layer circuit board.

8. The substrate structure as claimed in claim 1, wherein the substrate is a multi-layer circuit board.

9. A manufacturing method of a substrate structure, comprising: providing a substrate, comprising a packaging region and a peripheral region, wherein the peripheral region is connected to the packaging region and surrounds the packaging region; forming a plurality of through holes in the packaging region; providing a carrier, wherein the carrier comprises a release layer, a dielectric layer, and a metal layer, the dielectric layer being disposed between the release layer and the metal layer; laminating the substrate to the release layer of the carrier, such that the release layer and the dielectric layer are filled into the through holes to separably attach the substrate to the carrier; packaging a chip on the packaging region of the substrate, wherein the chip directly contacts the release layer filled into the through holes; and separating the chip and the substrate from the release film and the carrier to expose the back surface of the chip after packaging the chip on the substrate.

10. The manufacturing method of the substrate structure as claimed in claim 9, wherein the step of providing the substrate further comprises: forming a plurality of pads on an upper surface of the substrate, the pads being located in the packaging region and disposed around the through holes; and forming a patterned solder mask on the upper surface, and the patterned solder mask exposing the pads.

11. The manufacturing method of the substrate structure as claimed in claim 10, wherein the dielectric layer directly contacts with the release layer, the release layer contacts with inner walls of the through holes, and a first top surface of the release layer in the through holes is substantially coplanar with a second top surface of the patterned solder mask.

12. The manufacturing method of the substrate structure as claimed in claim 9, wherein the chip covers one of the through holes and contacting the release layer.

13. The manufacturing method of the substrate structure as claimed in claim 10, further comprising: electrically connecting the chip to the pads via a plurality of wires.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention, and together with the description, serve to explain the principles of the invention.

[0026] FIGS. 1A to 1D are cross-sectional schematic views illustrating the processes of a manufacturing method of a substrate structure according to an embodiment of the invention.

[0027] FIG. 2 is a top schematic view illustrating a substrate according to an embodiment of the invention.

[0028] FIG. 3 is a top schematic view illustrating a substrate according to an embodiment of the invention.

[0029] FIGS. 4A to 4E are cross-sectional schematic views illustrating the processes of a manufacturing method of a substrate structure according to an embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

[0030] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0031] FIGS. 1A to 1D are cross-sectional schematic views illustrating the processes of a manufacturing method of a substrate structure according to an embodiment of the invention. FIG. 2 is a top schematic view illustrating a substrate according to an embodiment of the invention. Referring to FIGS. 1A and 2, the manufacturing method of the substrate structure of this embodiment includes steps as follows. First of all, as shown in FIG. 1A, a substrate 110 is provided. In this embodiment, the substrate may be a single-layer circuit board or a multi-layer circuit board. In addition, the substrate 110 may include a packaging region A1 and a peripheral region A2, as shown in FIG. 1A. In this embodiment, the peripheral region A2 may be connected to the packaging region A1 and surround the packaging region A1, as shown in FIG. 2. Here, it should be noted that the peripheral region A2 in FIG. 2 is only shown for an illustrative purpose, and the invention is not limited thereto. In other embodiments of the invention, the peripheral region A2 may be merely located at one side of the packaging region A1 without surrounding the whole packaging region A1.

[0032] A manufacturing process of the substrate 110 may include forming a plurality of pads 130 on an upper surface 114 of the substrate 110. The pads 130 are located within the packaging region A1, and may be connected to corresponding vias 132 on the substrate 110, for example, so as to be electrically connected to a circuit layer 134 on the other side of the substrate 110 through the vias 132. Then, a patterned solder mask 140 may be further formed on the upper surface 114. The patterned solder mask 140 may have a plurality of openings 142 and each of the openings 142 exposes at least a portion of the corresponding pad 130. Then, a surface finishing layer 150 is formed on the pads 130 exposed by the patterned solder mask 140 to form the substrate 110 shown in FIG. 1A. In this embodiment, a material of the surface finishing layer is gold, nickel, silver, or other suitable materials.

[0033] Referring to FIGS. 1B and 2, a plurality of through holes 112 are formed in the peripheral region A2, so as to form the substrate 110 shown in FIG. 2. In this embodiment, the substrate 110 includes the upper surface 114 and a lower surface 116 opposite to each other, and the through holes 112 connect the upper surface 114 and the lower surface 116, as shown in FIG. 1B.

[0034] Then, a carrier 120 shown in FIG. 1C is provided. It should be noted that in FIG. 1C, the carrier is shown in exploded view. The carrier 120 includes a release layer 122, a dielectric layer 124, and a metal layer 126. In addition, the dielectric layer 124 is disposed between the release layer 122 and the metal layer 126. In this embodiment, a material of the release layer may include an aluminum foil or a polyimide film (PI film), a material of the dielectric layer 124 may include prepreg (PP), and a material of the metal layer 126 may be copper foil, for example. Naturally, the embodiment only serves for an illustrative purpose, and the invention is not limited thereto.

[0035] Referring to FIGS. 1C and 1D, the substrate 110 is laminated onto the release layer 122 of the carrier 120, such that the release layer 122 and the dielectric layer 124 are filled into the through holes 112, as shown in FIG. 1D. In addition, the release layer 122 is located between the substrate 110 and the dielectric layer 124 and contacts an inner wall of each of the through holes 112, such that the substrate 110 may be separably attached to the carrier 120. Thus, preliminary manufacture of the substrate structure 100 is completed.

[0036] As shown in FIG. 1D, the substrate structure 100 formed by the manufacturing method includes the substrate 110 and the carrier 120. As shown in FIG. 2, the substrate 110 includes the packaging region A1 and the peripheral region A2. In addition, the peripheral region A2 has the plurality of through holes 112 and is connected to the packaging region A1, and the peripheral region A2 surrounds the packaging region A1. In this embodiment, the substrate 110 may further include the plurality of pads 130, the patterned solder mask 140, and the surface finishing layer 150. The pads 130 are located within the packaging region A1 of the substrate 110 and connected to the corresponding vias 132, so as to be electrically connected to the circuit layer 134 on the other side of the substrate 110 through the vias 132. The patterned solder mask 140 covers the upper surface 114 of the substrate and exposes the pads 130. The surface finishing layer 150 covers the pads 130 exposed by the patterned solder mask 140. In this embodiment, a material of the surface finishing layer 150 is gold, nickel, silver, or other suitable materials.

[0037] Based on the above, the carrier 110 includes the release layer 122, the dielectric layer 124, and the metal layer 126. In addition, the dielectric layer 124 is disposed between the release layer 122 and the metal layer 126. The substrate 110 is disposed on the release layer 122 of the carrier 120, and the release layer 122 and the dielectric layer 124 are filled in the through holes 112, such that the release layer 122 is located between the substrate 110 and the dielectric layer 124 and contacts an inner wall of each through hole 112, so as to separably attach the substrate 110 to the carrier 120.

[0038] Given the configuration, the release layer 122 and the dielectric layer 124 of the carrier 120 are pressed and filled into the through holes 112 of the substrate 110 by laminating the substrate 110 to the carrier 120, thereby enhancing a bonding strength between the substrate 110 and the carrier 120. In addition, by utilizing a characteristic that the release layer 122 is easily separated from the substrate 110, the substrate 110 may be easily separated from the carrier 120 without being damaged after a subsequent packaging process is completed. Thus, the embodiment not only enhances the bonding strength between the substrate 110 and the carrier 120 in the substrate structure 100, but reduces a manufacturing difficulty and increases a yield rate of the manufacturing process.

[0039] FIG. 3 is a top schematic view illustrating a substrate according to an embodiment of the invention. FIGS. 4A to 4E are cross-sectional schematic views illustrating the processes of a manufacturing method of a substrate structure according to an embodiment of the invention. It should be noted that a substrate structure 100a of this embodiment is similar to the substrate structure 100. Therefore, the reference numerals and a part of the contents in the previous embodiment are used in the this embodiment, in which identical reference numerals indicate identical or similar components, and repeated description of the same technical contents is omitted. For a detailed description of the omitted parts, reference can be found in the previous embodiment, and no repeated description is contained in this embodiment. Detailed description regarding the difference between the substrate structure 100a of this embodiment and the substrate structure 100 in the previous embodiment is provided below.

[0040] Referring to FIGS. 3 and 4A, the manufacturing method of the substrate structure of this embodiment includes steps as follows. First of all, as shown in FIG. 1A, a substrate 110a is provided. In this embodiment, the substrate 110a may be a single-layer circuit board or a multi-layer circuit board. In addition, as shown in FIG. 3, the substrate 110a may include the packaging region A1 and the peripheral region A2. As described in the previous embodiment, the peripheral region A2 is connected to the packaging region A1 and surrounds the packaging region A1. It should be noted that FIGS. 4A to 4E only illustrate partial cross-sections of the packaging region A1 without illustrating partial cross-sections of the peripheral region A2.

[0041] A manufacturing process of the substrate 110a of this embodiment is similar to the manufacturing process of the substrate 110. Namely, the plurality of pads 130 may also be formed on the packaging region A1 of the substrate 110a, and then the patterned solder mask 140 is formed on the substrate 110a. The patterned solder mask 140 covers the upper surface 114 of the substrate 110a and exposes the pads 130. Then, the surface finishing layer 150 is formed on the pads 130 exposed by the patterned solder mask 140. However, through holes 112a of this embodiment are formed in the packaging region A1 of the substrate 110a, and the pads 130 may be disposed around the through holes 112a, for example.

[0042] Then, the carrier 120 shown in FIG. 4B is provided. Like the carrier 120 of the previous embodiment, the carrier 120 of this embodiment also includes the release layer 122, the dielectric layer 124, and the metal layer 126. Relevant technical contents may be referred to the previous embodiment, and no further details in this respect will be reiterated below. Then, as shown in FIG. 4C, the substrate 110a is laminated to the release layer 122 of the carrier 120, such that the release layer 122 and the dielectric layer 124 are pressed and filled into the through holes 112a located within the packaging region A1, as shown in FIG. 4C. In addition, the release layer 122 is located between the substrate 110a and the dielectric layer 124 and contacts an inner wall of each through hole 112a, as shown in FIG. 4C, so as to separably attach the substrate 110a to the carrier 120. Thus, preliminary manufacture of the substrate structure 100a is completed.

[0043] The substrate structure 100a formed by the manufacturing method is similar to the substrate structure 100 of the previous embodiment, except that the through holes 112a are disposed in the packaging region A1 of the substrate 110a. Therefore, in this embodiment, the release layer 122 and the dielectric layer 124 of the carrier 120 are pressed and filled into the through holes 112a of the packaging region A1 of the substrate 110a, so as to preserve a space for filling a heat dissipation paste or liquid, preserve a space to be conductive for ventilation, or preserve a sensing space for a sensing element of a chip on the substrate structure 100a, for example.

[0044] For example, as shown in FIG. 4D, a chip 160 may be further disposed in the packaging region A1 of the substrate 110a in this embodiment. The chip 160 covers one of the through holes 112a and contacts the release layer 122 in the through holes 112a. Then, the chip 160 is electrically connected to the pads 130 by a plurality of wires 170, so as to fix the chip 160 to the substrate 110a and be electrically connected to the substrate 110a. In this embodiment, the chip 160 includes an active surface 162 and a back surface 164 opposite to the active surface 162. The wires 170 are connected to the active surface 162 of the chip 160.

[0045] Then, as shown in FIG. 4E, the carrier 120 is removed to expose the back surface 164 of the chip 160 by utilizing the characteristic that the release layer 122 is easily separated from the substrate 110a. Accordingly, with the back surface 164 of the chip 160 exposed, a chip package formed by the aforementioned manufacturing process is able to provide a sensing space for a sensing element of the chip 160. For example, the chip 160 may include a light-sensing element, a sound-sensing element, or a touch-sensing element. Thereby, a light-sensing region of the light-sensing element, a resonant region (i.e. vibrating region) of the sound-sensing element or a touch region of the touch-sensing element located at the back surface 164 may be exposed through the through holes 112a of the substrate 110a, so as to enhance the performance of the chip. Alternatively, the chip 160 may also utilize the back surface 164 exposed by the through holes 112a for heat dissipation or ventilation. Or, a heat dissipation paste or liquid maybe filled in the through holes 112a to facilitate heat dissipation efficiency. Therefore, this embodiment is capable of increasing a functionality of the chip 160.

[0046] In view of the foregoing, in the invention, the substrate is laminated to the carrier so the release layer and the dielectric layer of the carrier are pressed and filled into the through holes of the substrate, so as to enhance the bonding strength between the substrate and the carrier. In addition, by utilizing the characteristic that the release layer is easily separated from the substrate, the substrate may be easily separated from the carrier without being damaged after the subsequent packaging process is completed. Thus, the invention not only enhances the bonding strength between the substrate and the carrier in the substrate structure, but reduces the manufacturing difficulty and increases the yield rate of the manufacturing process.

[0047] In addition, if the through holes of the substrate are located within the packaging region of the substrate and the chip is disposed on the packaging region to cover the through holes, the through holes of the substrate then exposes the surface of the chip after the carrier is separated from the substrate by utilizing the release layer. Thereby, the sensing space of the sensing element of the chip, which may serve as the light-sensing region of the light-sensing element, the resonant region (vibrating region) of the sound-sensing element, and the touch region of the touch-sensing element, may be provided. Alternatively, the chip may utilize the surface exposed by the through holes for heat dissipation or ventilation. Besides, the heat dissipation paste may be filled in the through holes, so as to facilitate the heat dissipation efficiency of the chip. Therefore, the invention also increases the functionality of the chip.

[0048] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.