PHASE DETECTION METHOD BASED ON A RECEIVING SEQUENCE OF SAMPLED VALUES

Abstract

The invention relates to a phase detection method (200) comprising the following steps: receiving (201) a receiving sequence (Y.sub.j) of values (Y.sub.0, Y.sub.1, . . . , Y.sub.N-1) of a receiving signal (Y), said values (Y.sub.0, Y.sub.1, . . . , Y.sub.N-1) having been sampled with a known sampling frequency f.sub.s and said receiving signal (Y) representing a reaction to a transmitting signal having a known transmitting frequency f.sub.w; providing (202) a sine sequence (S.sub.j) and a cosine sequence (C.sub.j) for each index (j) of the receiving sequence (Y.sub.j), said sine sequence (S.sub.j) comprising sine values of consecutive multiples of a known circular frequency, which depends on the transmitting frequency and the sampling frequency, and said cosine sequence (C.sub.j) comprising cosine values of consecutive multiples of the known circular frequency; and determining (203) a phase real part (U) of the receiving signal (Y) based on a scalar product of the receiving sequence (Y.sub.j) with the cosine sequence (C.sub.j) and a phase imaginary part (V) of the receiving signal based on a scalar product of the receiving sequence (Y.sub.j) with the sine sequence (S.sub.j).

Claims

1. A phase detection method comprising the following steps: receiving a receiving, sequence (Y.sub.j) of values (Y.sub.0, Y.sub.1, . . . , Y.sub.N-1) of a receiving signal (Y), said values (Y.sub.0, Y.sub.1, . . . , Y.sub.N-1) having been sampled with a known sampling frequency f.sub.s and said receiving signal (Y) representing a reaction to a transmitting signal having a known transmitting frequency f.sub.w; providing a sine sequence (S.sub.j) and a cosine sequence (C.sub.j) for each index (j) of the receiving sequence (Y.sub.j), said sine sequence (S.sub.j) comprising sine values of consecutive multiples of a known circular frequency (Ω) which depends on the transmitting frequency f.sub.w and the sampling frequency f.sub.s, and said cosine sequence (C.sub.j) including cosine values of consecutive multiples of the known circular frequency (Ω); and determining a phase real part (U) of the receiving signal (Y) based on a scalar product of the receiving sequence (Y.sub.j) with the cosine sequence (C.sub.j) and a phase imaginary part (V) of the receiving signal based on a scalar product of the receiving sequence (Y.sub.j) with the sine sequence (S.sub.j).

2. The phase detection method according to claim 1, wherein a normalization factor of the two scalar products depends on a length (N) of the receiving sequence (Y.sub.j).

3. The phase detection method according to claim 1, wherein the sampling frequency f.sub.s, with which the receiving signal (Y) is sampled, is lesser than a Nyquist-Shannon sampling frequency.

4. The phase detection method according to claim 1, wherein the length (N) of the receiving sequence (Y.sub.j), which is multiplied by a quotient from the known transmitting frequency f.sub.w and the known sampling frequency f.sub.s, is an integer and a period of the cosine sequence (C.sub.j) as well as of the sine sequence (S.sub.j).

5. The phase detection method according to claim 1, wherein the length (N) of the receiving sequence (Y.sub.j) corresponds to a quotient from the sampling frequency f.sub.s and a smallest common denominator from the sampling frequency f.sub.s and the transmitting frequency f.sub.w or to a multiple of the quotient.

6. The phase detection method according to claim 1 including determining a bias of the receiving signal (Y) based on a mean of the receiving sequence (Y.sub.j).

7. The phase detection method according to claim 1, wherein the known circular frequency Ω satisfies the following condition: Ω=2π(f.sub.w/f.sub.s).

8. A processor for determining a phase of a receiving signal, said processor comprising: an n-ary input register configured for storing a receiving sequence (Y.sub.j) of values (Y.sub.0, Y.sub.1, . . . , Y.sub.N-1) of a receiving signal (Y), said values (Y.sub.0, Y.sub.1, . . . , Y.sub.N-1) having been sampled with a known sampling frequency f.sub.s and said receiving signal (Y) representing a reaction to a transmitting signal having a known transmitting frequency f.sub.w; an n-ary first parameter register and an n-ary second parameter register, respectively, which are configured for storing a sine sequence (S.sub.j) and a cosine sequence (C.sub.j), said sine sequence (S.sub.j) including sine values of consecutive multiples of a known circular frequency (Ω) which depends on the transmitting frequency f.sub.w and the sampling frequency f.sub.s and said cosine sequence (C.sub.j) including cosine values of consecutive multiples of the known circular frequency (Ω); a first output register and a second output register, said first output register being configured for providing a phase real part (U) and said second output register being for providing a phase imaginary part (V) of the receiving signal; and a computing unit configured for determining the phase real part (U) of the receiving signal (Y) based on a scalar product of the receiving sequence (Y.sub.j) with the sine sequence (S.sub.j) and for determining the phase imaginary part (V) of the receiving signal (Y) based on a scalar product of the receiving sequence (Y.sub.j) with the cosine sequence (C.sub.j).

9. The processor according to claim 8, wherein a normalization factor of the two scalar products is a function of N, wherein N denotes a length of the receiving sequence (Y.sub.j).

10. The processor according, to claim 7 including a third output register configured for providing a bias of the receiving signal (Y), wherein the computing unit is configured for determining the bias of the receiving signal (Y) based on a mean of the receiving sequence (Y.sub.j).

11. The processor according to claim 8, wherein the known circular frequency Ω satisfies the following condition: Ω=2π(f.sub.w/f.sub.s).

12. A processor for determining a phase of a receiving signal, said processor comprising: an input register configured for storing a receiving value of a receiving signal (Y) sampled with a known sampling, frequency f.sub.s, said receiving signal (Y) representing a reaction to a transmitting signal having a known transmitting frequency f.sub.w; a first coefficient register and a second coefficient register, which are configured for storing, a first Fourier Coefficient (S) and a second Fourier Coefficient (C), respectively, said first Fourier Coefficient (S) denoting a linear relation between the receiving signal (Y) and a phase real part of the receiving signal (Y), and said second Fourier Coefficient (C) denoting a linear relation between the receiving signal (Y) and a phase imaginary part of the receiving signal (Y); a first output register and a second output register, which are configured for providing a phase real part (U) and a phase imaginary part (V) of the receiving signal (Y), respectively; and a computing unit configured for determining the phase real part (U) of the receiving signal (Y) based on an averaged product of the receiving value with the content (S) of the first coefficient register and for determining the phase imaginary part (V) of the receiving signal (Y) based on an averaged product of the receiving, value with the content (C) of the second coefficient register.

13. The processor according to claim 10 including an instruction unit configured for resetting the second coefficient register to one in response to a reset signal and for deleting the remaining registers, and for storing a new receiving value of the sampled receiving signal (Y) in response to a clock signal and for providing the first coefficient register and the second coefficient register with new coefficients, wherein the computing unit is configured for determining the averaged products based on a temporal averaging of products from the receiving value and the content (S) of the first coefficient register or the content (C) of the second coefficient register, respectively, said products each being present in dependence of the clock signal, and wherein the instruction unit is configured for renewing the second coefficient register in response to the clock signal using the coefficient dC.Math.C−dS.Math.S and for renewing the first coefficient register using the coefficient dC.Math.S+dS.Math.C, wherein C denotes the content of the second coefficient register, S denotes the content of the first coefficient register and furthermore dC=cos(Ω) and dS=sin(Ω) with Ω=2π*(f.sub.w/f.sub.s) also apply.

14. The processor according to claim 13, including a first internal register and a second internal register, wherein the instruction unit is configured for incrementing the first internal register by a product from the content of the input register and the content (S) of the first coefficient register in response to the clock signal and for incrementing the second internal register by a product from the content of the input register and the content (C) of the second coefficient register and for providing each with a normalization factor normalized in the first output register and the second output register, respectively.

15. The processor according to claim 12, including a third output register configured for providing a bias (β) of the receiving signal (Y), wherein the computing unit is configured for determining the bias (β) of the receiving signal (Y) based on a temporal averaging of the content of the input register.

16. The phase detection method according to claim 2, wherein the normalization factor is 2/N.

17. The processor according to claim 9, wherein the normalization factor is 2/N.

Description

[0045] Further embodiments are described by way of reference to the attached drawings. In the figures,

[0046] FIG. 1 shows a schematic view of a system 100 for measuring phase relations of acoustic waves in a vessel 102;

[0047] FIG. 2 shows a schematic view of a phase detection method 200 according to an embodiment;

[0048] FIG. 3 shows a schematic view of a processor 300 for determining a phase of a receiving signal according to a first embodiment;

[0049] FIG. 4 shows a schematic view of a processor 400 for determining a phase of a receiving signal according to a second embodiment; and

[0050] FIG. 5 shows a schematic view of a processor 500 for determining a phase of a receiving signal according to a third embodiment.

[0051] The following detailed description refers to the enclosed drawings, said drawings forming a part thereof and showing specific embodiments of implementing the invention for illustrative purposes. It is understood that other embodiments can also be used and structural or logical changes can be made without deviating from the concept of the present invention. The following detailed description is therefore not to be understood in a limiting sense. Moreover, it is understood that the features of the different exemplary embodiments described herein can be combined with each other, unless something else is specifically indicated.

[0052] The aspects and embodiments are described with reference to the drawings, with identical reference numbers generally referring to identical elements. In the following description, numerous specific details are described for the purpose of explaining the invention in order to enable thorough understanding of one or more aspects of the invention. However, it can be obvious to a skilled person that one or more aspects or embodiments can be implemented by a lesser degree of the specific details. In other cases, known structures and elements are shown in a schematic form in order to facilitate describing one or more aspects or embodiments. It is understood that other embodiments can be used and structural or logical changes can be implemented without deviating from the concept of the present invention.

[0053] Albeit a certain feature or a certain aspect of an embodiment regarding only one of several implementations may have been disclosed, such a feature or such an aspect can furthermore be combined with one or more other features or aspects of the other implementations, as may be desired or advantageous for any given or specific use. Furthermore, expressions such as “contain”, “have”, “with” or other variations thereof as used in the description or the claims are to be understood as in an inclusive sense, like the meaning of “comprise”. The expressions “coupled” and “connected” may have been used in conjunction with its derivatives. It is understood that such expressions are used for indicating that two elements cooperate or interact with each other independently of whether they are in direct physical or electric contact with each other or whether they are not in direct contact with each other. Moreover, the expressions “such as” and “for example” are to be understood merely as referring to an exemplary embodiment instead of a description of the best or the ideal embodiment. The following description is therefore not to be understood in a limiting sense.

[0054] FIG. 2 shows a schematic view of a phase detection method 200 according to an embodiment. The method 200 comprises receiving 201 a receiving sequence Y.sub.j of values Y.sub.0, Y.sub.1, . . . , Y.sub.N-1 of a receiving signal Y, said values Y.sub.0, Y.sub.1, . . . , Y.sub.N-1 having been sampled with a known sampling frequency f.sub.s and said receiving signal Y representing a reaction to a transmitting signal having a known transmitting frequency f.sub.w. The method 200 comprises providing 202 a sine sequence S.sub.j and a cosine sequence C.sub.j for each index j of the receiving sequence Y.sub.j, said sine sequence S.sub.j comprising sine values of consecutive multiples of a known circular frequency, which depends on the transmitting frequency f.sub.w and the sampling frequency f.sub.s, and said cosine sequence C.sub.j comprising cosine values of consecutive multiples of the known circular frequency. The method 200 comprises determining 203 a phase real part U of the receiving signal Y based on a scalar product of the receiving sequence Y.sub.j with the cosine sequence C.sub.j and a phase imaginary part V of the receiving signal based on a scalar product of the receiving sequence Y.sub.j with the sine sequence S.sub.j.

[0055] The known circular frequency Ω can satisfy the condition Ω=2π(f.sub.w/f.sub.s).

[0056] A normalization factor 2/N of the two scalar products can depend on a length N of the receiving sequence Y.sub.j. The sampling frequency f.sub.s, by means of which the receiving signal Y is sampled, can be independent of the Nyquist-Shannon sampling theorem. The length N of the receiving sequence Y.sub.j multiplied by a quotient from the known transmitting frequency f.sub.w and the known sampling frequency f.sub.s can be an integer and a period of the cosine sequence C.sub.j as well as of the sine sequence S.sub.j. The length N of the receiving sequence Y.sub.j can correspond to a quotient from the sampling frequency f.sub.s and the smallest common denominator from the sampling frequency f.sub.s and the transmitting frequency f.sub.w or to a multiple of the quotient.

[0057] The following representation describes the theoretic principles of the method 200.

[0058] A vector

Y.sub.0,Y.sub.1, . . . ,Y.sub.N-1 (4)

of sampled values of the function

Y(τ)=β+A sin(2π≦f.sub.wτ+φ) (5)

in the sampling frequency f.sub.S is given.

[0059] The approximation values of the unknown parameters [0060] A, β and φ
can be regained by applying a method of least squares while using the following formulas:

[00002] $\begin{matrix} [\begin{matrix} Cov (S, Y) \\ Cov (C, Y) \end{matrix}] = [\begin{matrix} Cov (S, S) & Cov (S, C) \\ Cov (C, S) & Cov (C, C) \end{matrix}] \times [\begin{matrix} A .Math. .Math. \cos (ϕ) \\ A .Math. .Math. \sin (ϕ) \end{matrix}], & (6 .Math. a) \\ β = \overline{Y} - A .Math. (\overline{C} .Math. .Math. \sin (ϕ) + \overline{S} .Math. .Math. \cos (ϕ)), & (6 .Math. b) \end{matrix}$

wherein the term

Cov(Z,T)=(Z−Z).Math.(T−T)=ZT−Z.Math.T (7)

represents a covariance of the sequences Z and T
and the sequences S and C, and
wherein S and C are given via the conditions:

S.sub.j=sin(2π.Math.(f.sub.w/f.sub.s).Math.j),j=0, . . . ,N−1 (8a)

C.sub.j=cos(2π.Math.(f.sub.w/f.sub.s).Math.j),j=0, . . . ,N−1 (8b).

[0061] As can be easily seen, the term

N.Math.(f.sub.w/f.sub.s)εZ, (9)

is a period of both sequences {S.sub.j} and {C.sub.j} for every N, wherein Z denotes the number of the integers.

[0062] N is then also a multiple of

[00003] $\begin{matrix} {\hat{f}}_{s} = \frac{f_{s}}{ggT (f_{s}, f_{w})}, & (10) \end{matrix}$

wherein ggT denotes the largest common divisor and

[00004] $\begin{matrix} \overline{S} = \frac{1}{N} .Math. {.Math.}_{j = 0}^{N - 1} .Math. S_{j} = 0, .Math. \overline{C} = \frac{1}{N} .Math. {.Math.}_{j = 0}^{N - 1} .Math. C_{j} = 0, .Math. \overline{SC} = \frac{1}{N} .Math. {.Math.}_{j = 0}^{N - 1} .Math. S_{j} .Math. C_{j} = 0 & (11 .Math. a) \\ \overline{S^{2}} = \frac{1}{N} .Math. {.Math.}_{j = 0}^{N - 1} .Math. S_{j}^{2} = \frac{1}{2} .Math. .Math. and .Math. .Math. \overline{C^{2}} = \frac{1}{N} .Math. {.Math.}_{j = 0}^{N - 1} .Math. C_{j}^{2} = \frac{1}{2} & (11 .Math. b) \end{matrix}$

applies.

[0063] The equation (6a) thus takes on the following form:

[00005] $\begin{matrix} [\begin{matrix} \overline{S .Math. Y} \\ \overline{C .Math. Y} \end{matrix}] = [\begin{matrix} \frac{1}{2} & 0 \\ 0 & \frac{1}{2} \end{matrix}] \times [\begin{matrix} A .Math. .Math. \cos (ϕ) \\ A .Math. .Math. \sin (ϕ) \end{matrix}] . & (12) \end{matrix}$

[0064] Thus, the following applies:

U=A cos(φ)=2.Math.SY (13a)

V=A sin(φ)=2.Math.CY (13b)

and the searched values can be determined via the following conditions:

A=U.sup.2+V.sup.2, (14a)

φ=(arcsin(V/A)mod 2π), (14b)

β=Y. (14c)

[0065] Receiving 201 the receiving sequence Y.sub.j of values Y.sub.0, Y.sub.1, . . . , Y.sub.N-1 of a receiving signal Y of the method 200, said values having been sampled with a known sampling frequency f.sub.s, can be described using the equations (4) and (5).

[0066] Providing 202 a sine sequence S.sub.j and a cosine sequence C.sub.j for each index j of the receiving sequence Y.sub.j of the method 200 can be described using the equations (8a), (8b), (9) and (10).

[0067] Determining 203 a phase real part U of the receiving signal Y based on a scalar product of the receiving sequence Y.sub.j with the cosine sequence C.sub.j and a phase imaginary part V of the receiving signal based on a scalar product of the receiving sequence Y.sub.j with the sine sequence S.sub.j of the method 200 can be described using the equations (6a), (6b), (7) and (11a) to (14c).

[0068] FIG. 3 shows a schematic view of a processor 300 for determining a phase of a receiving signal according to a first embodiment.

[0069] The processor 300 comprises an n-ary input register 301, an n-ary first parameter register 303, an n-ary second parameter register 305, a first output register 307, a second output register 309, a third output register 313, a computing unit 311 and an instruction unit 315. The processor further comprises an inlet for a clock signal CLK 320 and an inlet for a reset signal RST 322. The processor 300 is coupled to an input data bus 317 on its inlet side and to an output data bus 319 on its outlet side.

[0070] The n-ary input register 301 is configured for storing a receiving sequence Y.sub.j of values Y.sub.0, Y.sub.1, . . . , Y.sub.N-1 of the receiving signal Y, said values Y.sub.0, Y.sub.1, . . . , Y.sub.N-1 having been sampled with a known sampling frequency f.sub.s and said receiving signal Y representing a reaction to a transmitting signal having a known transmitting frequency f.sub.w.

[0071] The n-ary first parameter register 303 is configured for storing a sine sequence S.sub.j, which comprises sine values of consecutive multiples of a known circular frequency Ω, which depends on the transmitting frequency f.sub.w and the sampling frequency f.sub.s. The n-ary second parameter register 305 is configured for storing a cosine sequence C.sub.j, which comprises cosine values of consecutive multiples of the known circular frequency Ω.

[0072] The known circular frequency Ω can satisfy the condition Ω=2π(f.sub.w/f.sub.s).

[0073] The first output register 307 is configured for providing a phase real part U of the receiving signal. The second output register 309 is configured for providing a phase imaginary part V of the receiving signal.

[0074] The computing unit 311 is configured for determining the phase real part U of the receiving signal Y based on a scalar product of the receiving sequence Y.sub.j with the sine sequence S.sub.j. The computing unit 311 is further configured for determining the phase imaginary part V of the receiving signal Y based on a scalar product of the receiving sequence Y.sub.j with the cosine sequence C.sub.j. A normalization factor of the two scalar products can be chosen as 2/N, wherein N denotes a length of the receiving sequence Y.sub.j.

[0075] The computing unit 311, which is shown here only as a box using dashed lines, can comprise arithmetic-logic units for executing arithmetic operations. It can comprise adders, multipliers and other units for executing computing operations.

[0076] The third output register 313 is configured for providing a bias of the receiving signal Y, said bias being able to be determined by the computing unit 313 based on a mean of the receiving sequence Y.sub.j.

[0077] The processor 300 can be realized in hardware or in software. The processor 300 can form an operating unit on a chip or can be realized as a chip. The processor 300 can be a digital signal processor or a microcontroller. The processor 300 can be realized as an FPGA, as an integrated circuit, as an ASIC or as part of these components. The processor 300 can be realized in a receiver or as part of a receiver circuit, such as a receiver 103 as shown in FIG. 1.

[0078] The mode of operation of the processor 300 can be described as follows.

[0079] The vectors S and C stored in the two parameter registers 303, 305 each contain the sequences:

sin(2πσ.Math.j),j=0, . . . ,N−1 and (15a)

cos(2πσ.Math.j),j=0, . . . ,N−1, (15b)

wherein σ denotes a quotient from the signal frequency f.sub.w and the sampling frequency f.sub.s:

[00006] $\begin{matrix} σ = \frac{f_{w}}{f_{s}} = \frac{{\hat{f}}_{w}}{{\hat{f}}_{s}} . & (16) \end{matrix}$

[0080] After starting the processor 300 or after receiving the reset signal RST 322, respectively, the data from the input data bus 317 are transmitted into the n-ary input register 301. The values

[00007] $\begin{matrix} \frac{2}{N} .Math. Y \circ S .Math. .Math. and & (17 .Math. a) \\ \frac{2}{N} .Math. Y \circ C, & (17 .Math. b) \end{matrix}$

are uploaded into each of the output registers U and V, wherein Y represents the sequence of sampled values Y.sub.0, Y.sub.1, . . . , Y.sub.N-1 of the receiving signal Y in vector form and S and C each represent the sine sequence S.sub.j and the cosine sequence C.sub.j, respectively, in vector form. The symbol ∘ denotes the scalar product or the inner product, respectively, of two vectors.

[0081] The bias β can be determined as a mean over the sequence of sampled values Y.sub.0, Y.sub.1, . . . , Y.sub.N-1 of the receiving signal Y according to the following condition:

[00008] $\begin{matrix} \overline{Y} = \frac{1}{N} .Math. \underset{j = 1 .Math. .Math. .Math. .Math. N}{.Math.} .Math. Y_{j} & (18) \end{matrix}$

and is stored in the third output register 313.

[0082] FIG. 4 shows a schematic view of a processor 400 for determining a phase of a receiving signal according to a second embodiment.

[0083] The processor 400 comprises an input register 401, a first parameter register 403, a second parameter register 405, a third parameter register 425, a fourth parameter register 427, a counter 429, a first output register 407, a second output register 409, a third output register 413, an internal register 421, a second internal register 423, a third internal register 431, a computing unit 411 and an instruction unit 415. The processor 311 further comprises an inlet for a clock signal CLK 420 and an inlet for a reset signal RST 422. The processor 400 is coupled to an input data bus 417 on its inlet side and to an output data bus 419 on its outlet side.

[0084] The input register 401 is configured for storing a receiving value of a receiving signal Y sampled with a known sampling frequency f.sub.s, said receiving signal Y representing a reaction to a transmitting signal having a known transmitting frequency f.sub.w.

[0085] The first coefficient register 403 is configured for storing a first Fourier Coefficient S, which denotes a linear relation between the receiving signal Y and a phase real part of the receiving signal Y.

[0086] The second coefficient register 405 is configured for storing a second Fourier Coefficient C, which denotes a linear relation between the receiving signal Y and a phase imaginary part of the receiving signal Y.

[0087] The first output register 407 is configured for providing a phase real part U of the receiving signal Y. The second output register 409 is configured for providing a phase imaginary part V of the receiving signal Y.

[0088] The computing unit 411 is configured for determining the phase real part U of the receiving signal Y based on an averaged product of the receiving value with the content S of the first coefficient register 403. The computing unit 411 is configured for determining the phase imaginary part V of the receiving signal Y based on an averaged product of the receiving value with the content C of the second coefficient register 405.

[0089] The computing unit 411, which is shown here only as a box using dashed lines, can comprise arithmetic-logic units for executing arithmetic operations. It can comprise adders, multipliers and other units for executing computing operations.

[0090] The instruction unit 415 is configured for setting the second coefficient register 405 to one in response to a reset signal 422 and for deleting the remaining registers. The instruction unit 415 is configured for storing a new receiving value of the sampled receiving signal Y and for providing the first coefficient register 403 and the second 405 coefficient register with new coefficients S, C in response to a clock signal 420.

[0091] The computing unit 411 is further configured for determining the averaged products based on a temporal averaging of each of the products from the receiving value and the content S of the first coefficient register 403 or the content C of the second coefficient register 405, respectively, said products being present in dependence of the clock signal 420.

[0092] The instruction unit 415 is configured for renewing the second coefficient register 405 with the coefficient dC.Math.C−dS.Math.S in response to the clock signal 420 and for renewing the first coefficient register 403 with the coefficient dC.Math.S+dS.Math.C. In this instance, C denotes the content of the second coefficient register 405 and S denotes the content of the first coefficient register 403. Furthermore, dC=cos(Ω) and dS=sin(Ω) with δ=2π*(f.sub.w/f.sub.s) applies. The values dC and dS are present in the third parameter register 425 and the fourth parameter register 427, respectively. The counter register 429 can store a counter for counting the means of the averaged products from Y with S and Y with C, respectively.

[0093] The instruction unit 415 is configured for incrementing the first internal register 421 by a product SY from the content of the internal register 401 and the content S of the first coefficient register 403 in response to the clock signal 420. The instruction unit 415 is configured for incrementing the second internal register 423 by a product CY from the content of the input register 401 and the content C of the second coefficient register 405 in response to the clock signal 420. The instruction unit 415 is configured for providing the corresponding products, which are normalized by a normalization factor, in the first output register 407 and the second output register 409, respectively.

[0094] The third output register 413 is configured for providing a bias β of the receiving signal Y. The computing unit 411 is further configured for determining the bias β of the receiving signal Y based on a temporal averaging of the content of the input register 401.

[0095] The processor 400 can be realized in hardware or in software. The processor 400 can form an operating unit on a chip or can be realized as a chip. The processor 400 can be a digital signal processor or a microcontroller. The processor 400 can be realized as an FPGA, as an integrated circuit, as an ASIC or as part of these components. The processor 400 can be realized in a receiver or as part of a receiver circuit, such as a receiver 103 as shown in FIG. 1.

[0096] The mode of operation of the processor 400 can be described as follows:

[0097] After starting the processor 400 or after receiving the reset signal RST 422, the processor is operated using the given transmitting frequency f.sub.w and the given sampling frequency f.sub.s. The counter 429 is set corresponding to the values of f.sub.w and f.sub.s. In an embodiment of the processor 400, the abovementioned condition from equation (10) is met, i.e. N is equal to or a multiple of {circumflex over (f)}.sub.s:

[00009] $\begin{matrix} {\hat{f}}_{s} = \frac{f_{S}}{ggT (f_{S}, f_{w})} . & (10) \end{matrix}$

[0098] The internal registers 421, 423, 431 and the first parameter register 403 are deleted. The second parameter register 405 receives the value one. An input value is then successively stored in the input register 401, said input value being added to the third internal register 431. The first internal register 421 is then incremented by the product Y×S, i.e. the product of the contents of the input register 401 and the first coefficient register 403; the second internal register 423 is incremented by the product Y×C, i.e. the product of the contents of the input register 401 and the second coefficient register 405. Simultaneously, the first internal register 421 is modified corresponding to the rule S←dC.Math.S+dS.Math.C and the second internal register 423 is modified corresponding to the rule C∴dC.Math.C−dS.Math.S. In this instance, dS and dC denote constants comprising the values:

dS=sin(Ω), (19a)

dC=cos(Ω), (19b)

in which Ω=2πσ. (19c).

[0099] The counter 429 is reduced and only when the counter 429 is deleted are the contents of the internal registers 421, 423, 431, i.e. the values

[00010] $\frac{2}{N} .Math. SY, \frac{2}{N} .Math. CY, \frac{1}{N} .Math. Σ_{Y}$

stored as U, V and β in the corresponding output registers 407, 409, 413. U, V and β can then also be transferred onto the output data bus 419.

[0100] Subsequently, the processor 400 can be reset by setting the reset signal 422.

[0101] FIG. 5 shows a schematic view of a processor 500 for determining a phase of a receiving signal according to a third embodiment.

[0102] The processor 500 corresponds to the processor 400 except in that it has two additional internal registers, a fourth internal register 531 and a fifth internal register 533. Accordingly, the computing unit 511 and the instruction unit 515 are designed differently for processing the additional tasks associated therewith.

[0103] The fourth internal register 531 and the fifth internal register 533 can be used for storing intermediate results when determining the products Y×S and Y×C. Thus, the fourth internal register 531 can determine the value {tilde over (S)}=dC.Math.S+dS.Math.C, which can then be used for modifying the first internal register 421 according to the rule S←dC.Math.S+dS.Math.C or S←{tilde over (S)}.

[0104] The fifth internal register 533 can determine the value {tilde over (C)}=dC.Math.C−dS.Math.S, which can then be used for modifying the second internal register 423 according to the rule C←dC.Math.C−dS.Math.S or C←{tilde over (C)}.

[0105] The processor 500 can be realized in hardware or in software. The processor 500 can form an operating unit on a chip or can be realized as a chip. The processor 500 can be a digital signal processor or a microcontroller. The processor 500 can be realized as an FPGA, as an integrated circuit, as an ASIC or as part of these components. The processor 500 can be realized in a receiver or as part of a receiver circuit, such as a receiver 103 as shown in FIG. 1.

[0106] The processor 300 according to the description of FIG. 3 as well as the processors 400, 500 according to the description of FIGS. 4 and 5 are suitable for implementing the method 200 described in FIG. 2.

[0107] An aspect of the invention also comprises a computer program product, which can be uploaded directly into the internal memory of a digital computer and comprises software code sections, by means of which the method 200 described in FIG. 2 can be carried out when the product is running on a computer. The computer program product can be stored on a medium suitable for computers and can comprise the following: machine-readable programming means, which induce a computer to receive 201 a receiving sequence of values of a receiving signal, said values having been sampled with a known sampling frequency f.sub.s and said receiving signal (Y) representing a reaction to a transmitting signal having a known transmitting frequency f.sub.w; providing 202 a sine sequence and a cosine sequence for each index of the receiving sequence, said sine sequence comprising sine values of consecutive multiples of a known circular frequency Ω, which depends on the transmitting frequency f.sub.w and the sampling frequency f.sub.s, and said cosine sequence comprising cosine values of consecutive multiples of the known circular frequency; and determining 203 a phase real part of the receiving signal based on a scalar product of the receiving sequence with the cosine sequence and a phase imaginary part of the receiving signal based on a scalar product of the receiving sequence with the sine sequence.

[0108] The computer can be a PC, for example a PC of a computer network. The computer can be realized as a chip, an ASIC, a microprocessor, a signal processor or as a processor in general and can be implemented as a processor as described in FIGS. 3 to 5, for example.

[0109] It is understood that the features of the different exemplary embodiments described herein can be combined with one another, except when explicitly indicated otherwise. As shown in the description and the drawings, individual elements, which are shown in connection with one another, do not have to be directly connected to one another; intermediate elements can be provided between the connected elements. Furthermore, it is understood that embodiments of the invention can be implemented in individual circuits, partially integrated circuits or entirely integrated circuits or programming means. The terms “such as” and “for example” solely refer to an exemplary embodiment and not to the best or the ideal embodiment. Certain embodiments were depicted and described herein, although it is obvious to the skilled person that a plurality of alternative and/or similar implementations can be realized in place of the embodiments shown and described, without deviating from the concept of the present invention.

LIST OF REFERENCES

[0110] 100: system 100 for measuring phase relations of acoustic waves in a vessel [0111] 101: transmitter [0112] 102: vessel [0113] 103: receiver [0114] 104: ultrasonic wave [0115] 105: inlet [0116] 107: outlet [0117] 200: phase detection method 200 [0118] 201: 1.sup.st method step: receiving [0119] 202: 2.sup.nd method step: providing [0120] 203: 3.sup.rd method step: determining [0121] 300: processor, suitable for determining a phase of a receiving signal [0122] 301: n-ary input register [0123] 303: n-ary first parameter register [0124] 305: n-ary second parameter register [0125] 307: first output register [0126] 309: second output register [0127] 311: computing unit [0128] 313: third output register [0129] 315: instruction unit [0130] 317: input data bus [0131] 319: output data bus [0132] 320: clock signal [0133] 322: reset signal [0134] 400: processor, suitable for determining a phase of a receiving signal [0135] 401: input register [0136] 403: first parameter register [0137] 405: second parameter register [0138] 407: first output register [0139] 409: second output register [0140] 411: computing unit [0141] 413: third output register [0142] 415: instruction unit [0143] 417: input data bus [0144] 419: output data bus [0145] 420: clock signal [0146] 422: reset signal [0147] 421: first internal register [0148] 423: second internal register [0149] 431: third internal register [0150] 425: third parameter register [0151] 427: fourth parameter register [0152] 429: counter [0153] 500: processor, suitable for determining a phase of a receiving signal [0154] 511: computing unit [0155] 515: instruction unit [0156] 531: fourth internal register [0157] 533: fifth internal register

PHASE DETECTION METHOD BASED ON A RECEIVING SEQUENCE OF SAMPLED VALUES

Inventors

Cpc classification

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G01R19/25

PHYSICS

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G01R19/2506

PHYSICS

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H04M3/2209

ELECTRICITY

Classification Explorer

H04M3/30

ELECTRICITY

Classification Explorer

H04M1/24

ELECTRICITY

Classification Explorer

H03L7/091

ELECTRICITY

International classification

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H03L7/091

ELECTRICITY

Classification Explorer

G01R19/25

PHYSICS

Classification Explorer

H04M1/24

ELECTRICITY

Abstract

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Description