SWITCHING CIRCUITRY, RELATED METHOD AND INTEGRATED CIRCUIT

Abstract

Switching circuitry includes first and second transistors in series between two terminals and including a common control node with a capacitance between the common control node and an intermediate point. A control circuit includes first and second circuits configured to charge and discharge the capacitance as a function of first and second control signals. The control circuit includes a third circuit having a plurality of diodes and a switch that operates when the voltage at the capacitance is greater than a threshold two diodes in cascade between the intermediate point and the common control node to enable current flow from the intermediate point to the common control node. When the voltage at the capacitance is smaller than the given threshold two diodes are connected in series between the common control node and the intermediate point to enable current flow from the common control node to the intermediate point.

Claims

1. Switching circuitry, comprising: a first and a second transistor connected in series between two terminals, wherein said first and said second transistor comprise a respective control terminal connected to a common control node, wherein a capacitance is connected between said common control node and an intermediate point between said first and said second transistor, wherein said first and said second transistor are rendered conductive or non-conductive as a function of the voltage at said capacitance; and a control circuit comprising: a first circuit configured to charge said capacitance as a function of a first control signal, and a second circuit configured to discharge said capacitance as a function of a second control signal; a third circuit comprising a plurality of diodes and at least one switch configured such that: when the voltage at said capacitance is greater than a given threshold value, two diodes are connected in cascade between said intermediate point and said common control node, thereby enabling current flow from said intermediate point to said common control node, and when the voltage at said capacitance is smaller than said given threshold value, two diodes are connected in series between said common control node and said intermediate point, thereby enabling current flow from said common control node to said intermediate point.

2. The switching circuitry according to claim 1, wherein said first and said second transistor are n-channel Field Effect Transistors, wherein said first control signal indicates that said first and said second transistor should be conductive and said second control signal indicates that said first and said second transistor should be non-conductive.

3. The switching circuitry according to claim 2, wherein said third circuit comprises: a first branch comprising a first and a second diode connected in cascade, a second branch comprising a third and a fourth diode connected in cascade, and at least one switch configured to selectively connect either said first branch or said second branch between said common control node and said intermediate point.

4. The switching circuitry according to claim 3, wherein said at least one switch is driven as a function of the voltage at said capacitance.

5. The switching circuitry according to claim 4, wherein said at least one switch comprises: an n-channel Field Effect Transistor connected in series with said first branch between said intermediate point and said common control node, wherein the gate of said n-channel Field Effect Transistor is connected to said common control node, and a p-channel Field Effect Transistor connected in series with said second branch between said common control node and said intermediate point, wherein the gate of said p-channel Field Effect Transistor is connected to said common control node.

6. The switching circuitry according to claim 1, wherein said third circuit comprises: a first and a second n-channel Field Effect Transistor connected in series between said common control node and said intermediate point, and a first and a second p-channel Field Effect Transistor connected in series between said common control node and said intermediate point, and a first and a second diode connected in cascade, wherein the anode of said first diode is connected to the intermediate point between said first and said second n-channel Field Effect Transistor and the cathode of said second diode is connected to the intermediate point between said first and said second p-channel Field Effect Transistor.

7. The switching circuitry according to claim 6, wherein: the gate of said first n-channel Field Effect Transistor is connected to said common control node, the gate of said second n-channel Field Effect Transistor is connected to said intermediate point, the gate of said first p-channel Field Effect Transistor is connected to said common control node, and the gate of said second n-channel Field Effect Transistor is connected to said intermediate point.

8. The switching circuitry according to claim 7, wherein said first circuit comprises: a first sub-circuit configured to selectively apply a first voltage to said common control node, and a second sub-circuit configured to selectively apply a second voltage to said intermediate point, said first voltage being greater than said second voltage.

9. The switching circuitry according to claim 8, wherein said second circuit comprises: a first sub-circuit configured to selectively apply a first voltage to said intermediate point, and a second sub-circuit configured to selectively apply a second voltage to said common control node, said first voltage being equal to or greater than said second voltage.

10. The switching circuitry according to claim 9, wherein said first sub-circuit of said first circuit and/or said second sub-circuit of said second circuit are connected to the intermediate point between first and said second diode.

11. A method of switching a high voltage signal, comprising: applying an oscillating high-voltage drive signal to an input node; coupling the high-voltage drive signal to an output node through two series-connected transistors, the series-connected transistors having a common control node and signal nodes coupled between the input and output nodes with an intermediate node being defined at the interconnection of the signal nodes of the series-connected transistors; coupling a plurality of series-connected diodes between the common control node and the intermediate node to provide current flow from the intermediate node to the common control node responsive to a transition of the high-voltage drive signal on the input node from a first level to a second level if a voltage across the common control node and the intermediate node exceeds a threshold voltage of the series-connected transistors; and coupling a plurality of series-connected diodes between the common control node and the intermediate node to provide current flow from the common control node to the intermediate node responsive to a transition of the high-voltage drive signal from the second level to the first level if the voltage across the common control node and the intermediate node is less than the threshold voltage of the series-connected transistors.

12. The method of claim 11, wherein coupling a plurality of series-connected diodes between the common control node and the intermediate node comprises: coupling first and second diodes between the common control node and the intermediate node; and charging a parasitic capacitance of a parasitic intermediate node defined between the first and second diodes.

13. The method of claim 12, wherein charging a parasitic capacitance of a parasitic intermediate node defined between the first and second diodes comprises charging the parasitic capacitance to prevent the flow of current from the common control node to the intermediate node responsive to transitions of the high-voltage drive signal when the threshold voltage across the common control node and the intermediate node exceeds the threshold voltage of the series-connected transistors.

14. The method of claim 13, wherein charging a parasitic capacitance of a parasitic intermediate node defined between the first and second diodes comprises charging the parasitic capacitance to prevent the flow of current from the intermediate node to the common control node responsive to transitions of the high-voltage drive signal when the threshold voltage across the common control node and the intermediate node is less than threshold voltage of the series-connected transistors.

15. An electronic system, comprising: at least one transducer; signal generation circuitry; analysis circuitry; and an integrated circuit including switching circuitry coupled between the at least one transducer and the analysis and signal generation circuitry, the switching circuitry including: a first transistor and a second transistor coupled in series between an input node and an output node, each of the first and second transistors having a control node coupled to a common control node and having a first signal node coupled to an intermediate node, a second signal node of the first transistor being coupled to the input node and a second signal node of the second transistor coupled to the output node; and a control circuit coupled to the common control node and to the intermediate node and configured to receive a control signal indicating whether the first and second transistors are conductive to close the switching circuitry or are non-conductive to open the switching circuitry, the control circuit including a plurality of diodes configured to be coupled between the common control node and the intermediate node to provide current flow from the intermediate node to the common control node responsive to a transition of a drive signal on the input node from a first level to a second level if a voltage across the common control node and the intermediate node exceeds a threshold voltage of the first and second transistors, and the control circuit including a plurality of diodes configured to be coupled between the common control node and the intermediate node to provide current flow from the common control node to the intermediate node responsive to a transition of the drive signal from the second level to the first level if the voltage across the common control node and the intermediate node is less than the threshold voltage of the first and second transistors.

16. The electronic system of claim 15, wherein the electronic system comprises an echography system and the signal generation circuitry comprises a pulser circuit, and wherein the at least one transducer comprises an array of capacitive micromachined ultrasound transducers or piezoelectric transducers.

17. The electronic system of claim 16, wherein each of the first and second transistor comprises an n-channel field effect transistor having a source node coupled to the intermediate node and having a gate node coupled to the common control node, and a drain of the first transistor coupled to the input node and a drain of the second transistor coupled to the output node.

18. The electronic system of claim 17, wherein the plurality of diodes includes first and second series coupled diodes having a first parasitic intermediate node defined between the first and second series coupled diodes, the first parasitic intermediate node having a parasitic capacitance that is charged to prevent the flow of current from the common control node to the intermediate node responsive to transitions of the drive signal if the threshold voltage across the common control node and the intermediate node exceeds the threshold voltage of the first and second transistors.

19. The electronic system of claim 18, wherein the plurality of diodes includes third and fourth series coupled diodes having a second parasitic intermediate node defined between the third and fourth series coupled diodes, the second parasitic intermediate node having a parasitic capacitance that is charged to prevent the flow of current from the intermediate node to the common control node responsive to transitions of the drive signal if the threshold voltage across the common control node and the intermediate node is less than the threshold voltage of the first and second transistors.

20. The electronic system of claim 10, wherein each of the plurality of diodes comprises an active diode.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE FIGURES

[0050] Embodiments of the present disclosure will now be described with reference to the annexed drawings, which are provided purely by way of non-limiting example and in which:

[0051] FIGS. 1, 2 and 3 shows examples of ultrasound systems;

[0052] FIGS. 4 and 5 show examples of high voltage switching circuits adapted to be used in the systems of FIGS. 1 to 3;

[0053] FIGS. 6 and 7 show embodiments of a control circuit for a high voltage switching circuit in accordance with embodiments of the present disclosure;

[0054] FIGS. 8 and 12 show embodiments of charge circuits adapted to switch on a high voltage switching circuit;

[0055] FIGS. 9, 10 and 11 show embodiments of discharge circuits adapted to switch off a high voltage switching circuit;

[0056] FIGS. 13, 14a, 14b, 15a and 15b show a first embodiment of a rectification circuit adapted to maintain the state of a high voltage switching circuit;

[0057] FIGS. 16, 17a and 17b show a second embodiment of a rectification circuit adapted to maintain the state of a high voltage switching circuit;

[0058] FIGS. 18, 19a and 19b show a third embodiment of a rectification circuit adapted to maintain the state of a high voltage switching circuit, and

[0059] FIGS. 20, 21a and 21b show a fourth embodiment of a rectification circuit adapted to maintain the state of a high voltage switching circuit.

DETAILED DESCRIPTION

[0060] In the following description, numerous specific details are given to provide a thorough understanding of embodiments. The embodiments can be practiced without one or several specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0061] Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0062] The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0063] In the following FIGS. 6 to 21 parts, elements or components which have already been described with reference to FIGS. 1 to 5 are denoted by the same references previously used in such Figures; the description of such previously described elements will not be repeated in the following in order not to overburden the present detailed description.

[0064] As mentioned in the foregoing, the present disclosure relates to a high voltage switching circuitry 400. For example, such switching circuitry 400 may be used in place of the switches 300 disclosed in the foregoing. Accordingly, the respective description will not be repeated again.

[0065] FIG. 6 shows a first embodiment of the switching circuitry 400.

[0066] Generally, also the switching circuitry 400 of the present disclosure comprises two terminals T1 and T2 being either connected together (closed/conductive condition) or disconnected (opened/non-conductive condition), and two control terminals SET and RESET for receiving control signals indicating whether the two terminals T1 and T2 should be connected together or disconnected, respectively.

[0067] Specifically, in the embodiment considered, the switch 400 is implemented with two n-channel FET (Field Effect Transistors) SW.sub.1 and SW.sub.2 connected back-to-back (source nodes shorted together) to allow for bipolar and bidirectional operation. For example, these transistors may be implemented as Double-Diffused MOS (DMOS). As mentioned in the foregoing, this connection is preferable due to the parasitic body diodes of the transistors SW.sub.1 and SW.sub.2.

[0068] Accordingly, in the embodiment considered, the drain of the switch SW.sub.1 is connected (e.g., directly) to the terminal T1, the drain of the switch SW.sub.2 is connected (e.g., directly) to the terminal T2 and the sources of the switches SW.sub.1 and SW.sub.2 are connected (e.g., directly) to a common node S. Also the gates of the transistors SW.sub.1 and SW.sub.2 are connected (e.g., directly) together at a common node G and controlled by a control circuit 410 as a function of the control signals provided at the terminal SET and RESET. Specifically, the control circuit 410 is configured to ensure that: [0069] the gate-source voltage V.sub.GS of the transistors SW.sub.1 and SW (i.e., the voltage between the node G and the node S) is greater than the threshold voltage of the transistors SW.sub.1 and SW.sub.2 when the control signal SET indicates that the switch 400 should be closed (e.g., when the signal SET is high), and [0070] the gate-source voltage V.sub.GS of the transistors SW.sub.1 and SW is smaller than the threshold voltage of the transistors SW.sub.1 and SW.sub.2 when the control signal RESET indicates that the switch 400 should be opened (e.g., when the signal RESET is high).

[0071] Similar to document US 2005/0146371 A1, also the control circuit 410 of the present disclosure may operate with low voltage signals, e.g., in the range between 0 V and 5 V, preferably between 0 V and 3.3 V.

[0072] For this purpose, the state of the switch 400 should be changed only when the node S is connected (substantially) to ground GND and the drive signal TX is deactivated.

[0073] As mentioned in the foregoing, the node S may be connected to ground GND via the diode of the switch SW.sub.1 when the node T1 is connected to ground GND. For example, as described in the foregoing, the terminal T1 may be connected to ground GND via the pulser circuit 104.

[0074] However, generally, when the drive signal TX is deactivated, the terminal T1 may also be in a high impedance state, i.e., floating. For example, the terminal T1 may be floating, e.g., by disconnecting the terminal T1 or connecting the terminal T1 to the analysis circuitry 110 via the T/R switch 120. In this case, the switching circuitry 400 may comprise a clamp circuit 420 configured to connect the terminal T1 to ground GND when the state of the switch 400 has to be changed, e.g., when the signal SET is high or the signal RESET is high. For example, such a clamp circuit 420 may comprise an electronic switch, such as an n-channel FET, connected between the terminal T1 and ground GND.

[0075] Conversely, FIG. 7 shows an embodiment in which a similar clamp circuit 422 is used to connect directly the node S to ground GND. For example, such a clamp circuit 422 may comprise an electronic switch, such as an n-channel FET, connected between the node S and ground GND. This embodiment may thus ensure that the node S is connected to ground GND, independently from fact whether the node T1 is connected to ground or floating.

[0076] In the embodiment considered, the control circuit 410 comprises three sub-circuits: [0077] a first circuit 412 configured to charge the gate-source capacitance C.sub.GS between the node G and the node S when the signal SET indicates that the switch 400 has to be closed (e.g., when the signal SET is high), i.e., the transistors SW.sub.1 and SW.sub.2 have to be closed; [0078] a second circuit 414 configured to discharge the gate-source capacitance C.sub.GS between the node G and the node S when the signal RESET indicates that the switch 400 has to be opened (e.g., the signal RESET is high), i.e., the transistors SW.sub.1 and SW.sub.2 have to be opened; and [0079] a third circuit 416 configured to maintain the state of the switch 400 when the signals SET and RESET indicates that the state of the switch 400 should be maintained (e.g., when the signals SET and RESET are low) and the drive signal TX is activated.

[0080] FIG. 8 shows a possible embodiment of the circuit 412.

[0081] Generally, as mentioned in the foregoing, the circuit 412 should charge the gate-source capacitance C.sub.GS when the signal SET indicates that the switch 400 has to be closed (e.g., when the signal SET is high).

[0082] Moreover, as mentioned in the foregoing, the external control circuit generating the signals SET and RESET (e.g., the control circuit 102) ensures that the signal SET tries to close the switch 400 when the drive signal TX applied to the terminal T1 is deactivated.

[0083] In the embodiment considered, in order to switch on the switch 400, at least one of the nodes T1, T2 and S should be connected to ground GND. As mentioned in the foregoing, this may be ensured directly by the signal generation circuitry 100 (e.g., the pulser circuit 104) and/or by a clamp circuit 420/422 in the switch 400 and/or a similar clamp circuit connected to the node T2.

[0084] For example, in the embodiment considered, a clamp circuit 420 is used. For example, in the embodiment considered, the clamp circuit 420 comprises an electronic switch 4202, such as an n-channel FET, and a diode 4204 connected in series between the terminal T1 and ground GND.

[0085] Specifically, in the embodiment considered, the source of the transistor 4202 is connected (e.g., directly) to ground GND, the drain of the transistor 4202 is connected (e.g., directly) to the cathode of the diode 4204, and the anode of the diode 4204 is connected (e.g., directly) to the terminal T1, i.e., the drain of the transistor SW.sub.1. Accordingly, when a positive voltage is applied to the gate of the transistor 4202, the transistor 4202 will be closed, i.e., be conductive, and the terminal T1 will be short-circuited to ground GND. Conversely, the diode 4204 may be used to ensure that the body diode of the transistor 4202 is not rendered conductive when a negative voltage is applied to the terminal T1. This diode 4204 is purely optional, e.g., in case only positive voltages may be applied to the terminal T1.

[0086] In the embodiment considered, the switch 4202 is closed when the signal SET indicates that the switch 400 should be closed, e.g., when the signal SET is high.

[0087] In various embodiments, the diode 4204 is an active diode. Generally, an active diode means that the diode is implemented with an FET, wherein the body diode of the FET is used as the diode. In fact, in this case, the FET may be driven by a respective control signal. In this case, the FET behaves as a short circuit when the respective control signal has a first logic value, or as a diode when the control signal has a second logic value. For example, in the embodiment considered, such an FET could be driven with the signal SET in order to pull the node T1 to ground without the usual voltage drop of approximately 0.7 V at the diode 4204. Conversely, when the signal SET is low, the FET behaves exactly as the diode 4204 and blocks negative voltages at the node T1.

[0088] As mentioned in the foregoing, a similar clamp circuit may also be used for the clamp circuit 422 used to connect the node S to ground (see FIG. 7), e.g., by connecting (e.g., directly) the anode of the diode 4204 to the node S.

[0089] Accordingly, a low voltage, e.g., between 1.5 V and 5 V, e.g., 3.0 V or 3.3 V applied to the node G is sufficient to switch on the transistors SW.sub.1 and SW.sub.2.

[0090] For example, in the embodiment considered, the circuit 412 comprises for this reason an electronic switch 4122, such as a p-channel FET, and a diode 4124 connected in series between the node G and a positive supply voltage VDD.sub.P, such as 3.3 V. Specifically, in the embodiment considered, the source of the transistor 4122 is connected (e.g., directly) to the supply voltage VDD.sub.P, the drain of the transistor 4122 is connected (e.g., directly) to the anode of the diode 4124 and the cathode of the diode 4124 is connected (e.g., directly) to the node G. Accordingly, when a positive voltage is applied to the gate of the transistor 4122, the transistor 4122 will be opened and the node G will be floating. Conversely, the node G will be connected to the supply voltage VDD.sub.P and, thanks to the connection of the node S to ground, the node G will be charged, e.g., substantially to VDD.sub.P (neglecting the diode 4124). In fact, preferably, also the diode 4124 is an active diode driven as a function of the signal SET, i.e., the diode 4124 behaves as a short circuit, when the signal SET indicates that the switch 400 should be closed.

[0091] Accordingly, in the embodiment considered, the switch 4122 should be closed when the signal SET indicates that the switch 400 should be closed (e.g., when the signal SET is high). For example, considering the exemplary logic values of the signal SET and the opposed operation of the p-channel FET, the gate of the transistor 4122 may be driven by means of an inverted version of the signal SET. For example, in the embodiment considered, an inverter 4126 is interposed between the terminal SET and the gate of the transistor 4122.

[0092] Conversely, FIG. 9 shows an embodiment of the circuit 414 configured to discharge the node G, when the signal RESET indicates that the switch 400 should be opened (e.g., when the signal RESET is high).

[0093] Again, as mentioned in the foregoing, the external control circuit generating the signals SET and RESET ensures that the signal RESET tries to close the switch 400 when the drive signal TX applied to the node T1 is deactivated.

[0094] In the embodiment considered, in order to switch off the switch 400, the node T1 and/or the node S should be connected to ground GND. As mentioned in the foregoing, this may be ensured directly by the signal generation circuitry 100 and/or by a clamp circuit 420/422 in the switch 400.

[0095] For example, in FIG. 9 is used the same clamp circuit 420 already shown in FIG. 8. However, in this case, the clamp circuit 420 should also be active when the signal RESET indicates that the switch 400 should be opened. Accordingly, the gate of the transistor 4222 could be driven, e.g., via an OR gate receiving at input the signals SET and RESET.

[0096] In the embodiment considered, the circuit 414 used to discharge the node G is implemented with a clamp circuit comprising an electronic switch 4142, such as an n-channel FET, and a diode 4144, preferably an active diode driven by means of the signal RESET, connected in series between the node G and the node S. Specifically, in the embodiment considered, the source of the transistor 4142 is connected (e.g., directly) to the node S, the drain of the transistor 4142 is connected (e.g., directly) to the cathode of the diode 4144 and the anode of the diode 4144 is connected (e.g., directly) to the node G. Accordingly, when a positive voltage is applied to the gate of the transistor 4142, the transistor 4142 will be closed and the node G is connected to the node S. For example, considering the exemplary logic levels of the signal RESET, the gate of the transistor 4142 may be driven directly by the signal RESET.

[0097] Accordingly, when a positive voltage is applied to the gate of the transistor 4142, the transistor 4142 will be closed and the node G will be connected to the node S and the node G will be discharged. Considering the connection of the node S to ground, the node G will thus be discharged to substantially 0 V (again neglecting the diode 4144, which preferably is an active diode).

[0098] The inventors have observed that this voltage level might not be sufficient, because charge injected into the node G may still increase the gate-source voltage V.sub.GS above the threshold voltage of the transistors SW.sub.1 and SW.sub.2, thereby closing the switch 400.

[0099] FIG. 10 shows in this regards an alternative embodiment of the circuit 414, in which a negative gate-source voltage V.sub.GS is created.

[0100] In the embodiment considered, the circuit 414 comprises two sub-circuits 414a and 414b.

[0101] Specifically, the first sub-circuit 414a is configured to apply a positive voltage to the node S when the signal RESET indicates that the switch 400 should be opened. For example, in the embodiment considered, the circuit 414a has the same architecture as the circuit 412 described with respect to FIG. 8, with the only difference that the circuit is connected to the node S and not the node G. Specifically, in the embodiment considered, an electronic switch 4146, such as a p-channel FET, and a diode 4148, preferably an active diode driven by means of the signal RESET, are connected in series between a positive supply voltage, e.g., VDD.sub.P, and the node S, wherein the gate of the transistor 4146 is driven as a function of the signal RESET. For example, in the embodiment considered, an inverter 4150 is used to generate the drive signal applied to the gate of the transistor 4146, i.e., the supply voltage VDD.sub.P is applied to the node S when the signal RESET is high.

[0102] Conversely, a second circuit 414b is used to connect the node G to ground when the signal RESET indicates that the switch 400 should be opened. For example, in the embodiment considered, the circuit 414a has the same architecture as the clamp circuit 420 described with respect to FIG. 8, with the only difference that the circuit is connected to the node G and not the terminal T1. Specifically, in the embodiment considered, an electronic switch 4152, such as an n-channel FET, and a diode 4154, preferably an active diode driven by means of the signal RESET, are connected between the node G and ground GND, wherein the gate of the transistor 4152 is driven as a function of the signal RESET. For example, in the embodiment considered, the signal RESET is applied directly to the gate of the transistor 4152, i.e., the node G is connected to ground when the signal RESET is high.

[0103] Accordingly, in this embodiment, a negative gate-source voltage V.sub.GS (approximately −VDD.sub.P) will be generated when the signal RESET indicates that the switch 400 should be opened.

[0104] As shown in FIG. 11, generally, the circuit 414 may thus comprise two-sub-circuits: [0105] a first sub-circuit 414a configured to selectively apply a first voltage VDD.sub.P to the node S when the signal RESET indicates that the switch 400 should be opened; and [0106] a second sub-circuit 414b configured to selectively apply a second voltage VDD.sub.N to the node G when the signal RESET indicates that the switch 400 should be opened.

[0107] In the embodiment shown in FIG. 9, the voltages VDD.sub.P and VDD.sub.N are the same and the gate-source voltage is 0 V.

[0108] Conversely, in the embodiment shown in FIG. 10, the voltage VDD.sub.P is greater than the voltage VDD.sub.N, thereby generating a negative gate-source voltage:

V.sub.GS=VDD.sub.N−VDD.sub.P.

[0109] Generally, as shown in FIG. 12, the opposed behavior may be used for the circuit 412, i.e., the circuit 412 may thus comprise two-sub-circuits: [0110] a first sub-circuit 412a configured to selectively apply a first voltage VDD.sub.P to the node G when the signal SET indicates that the switch 400 should be closed; and [0111] a second sub-circuit 412b configured to selectively apply a second voltage VDD.sub.N to the node S when the signal SET indicates that the switch 400 should be closed.

[0112] Specifically, the second sub-circuit 412b may apply the second voltage VDD.sub.N to the node S: [0113] directly, as shown, e.g., with respect to the clamp circuit 422 (representing the circuit 412b in FIG. 7), or [0114] indirectly via the terminal T1 (or T2), as shown, e.g., with respect to the clamp circuit 420 (representing the circuit 412b in FIGS. 6 and 8)

[0115] Generally, the voltage VDD.sub.P should be greater than the voltage VDD.sub.N, thereby generating a positive gate-source voltage:

V.sub.GS=VDD.sub.P−VDD.sub.N.

[0116] For example, in the embodiment shown in FIGS. 6, 7 and 8, the voltage VDD.sub.N corresponds indeed to ground GND and V.sub.GS =VDD.sub.P.

[0117] Generally, the circuits 412 and 414 may also operate with different voltages VDD.sub.P and VDD.sub.N.

[0118] Accordingly, in the previous embodiments, the circuit 412 charges the gate-source capacitance C.sub.GS and generates a positive gate-source voltage V.sub.GS when the signal SET has a first logic value (e.g., high) indicating that the switch 400 has to be closed. Conversely, the circuit 414 discharges the gate-source capacitance C.sub.GS and generates a negative gate-source voltage V.sub.GS when the signal RESET has a first logic value (e.g., high) indicating that the switch 400 has to be opened.

[0119] Accordingly, the gate-source voltage V.sub.GS may have two levels: [0120] a positive voltage (switch 400 closed), or [0121] either a zero voltage or preferably a negative voltage (switch 400 opened)

[0122] Finally, the node G is disconnected, i.e., not connected to a supply voltage, when the signals SET and RESET have a second logic values (e.g., both low).

[0123] Accordingly, when the signals SET and RESET have the second logic values (e.g., low) the gate-source capacitance will be discharged due to leakage and/or charge sharing with parasitic capacitance. Moreover, positive and negative charge may be injected into the gate node G through the gate-drain capacitances of the switches SW.sub.1 and SW.sub.2.

[0124] Accordingly, in several embodiments, the circuit 410 comprises also a rectification circuit 416 configured to inject charge into the gate node G in order to maintain the state of the switch 400 thanks to the oscillation at the node T1 and/or T2.

[0125] FIG. 13 shows in this respect a first embodiment of a rectification circuit 416a.

[0126] Specifically, in the embodiment considered, the rectification circuit 416a comprises two branches and an electronic switch 4166 configured to connect one of the branches between the nodes G and S.

[0127] Specifically, each of the branches comprises two diodes connected in series, i.e., diodes 4162.sub.1 and 4164.sub.1 for the first branch and diodes 4162.sub.2 and 4164.sub.2 for the second branch.

[0128] Generally, also a series connection of a more diodes may be used for the diodes 4162 and 4164.

[0129] More specifically, in the embodiment considered, the cathode of the diode 4164.sub.1 is connected (e.g., directly) to the node G, the anode of the diode 4164.sub.1 is connected (e.g., directly) to the cathode of the diode 4162.sub.1 and the anode of the diode 4164.sub.1 is connected to the switch 4166 and may thus be connected selectively to the node S. Conversely, the anode of the diode 4162.sub.2 is connected (e.g., directly) to the node G, the cathode of the diode 4162.sub.2 is connected (e.g., directly) to the anode of the diode 4164.sub.2 and the cathode of the diode 4164.sub.2 is connected to the switch 4166 and may thus be connected selectively to the node S.

[0130] Accordingly, the first branch defines a conductive path from the node S to the node G (with the opposite direction being blocked, i.e., non-conductive) and the second branch defines a conductive path from the node G to the node S (with the opposite direction being blocked), wherein one of the branches may be activated selectively via the switch 4166.

[0131] Moreover, in the embodiment considered, the switch 4166 is driven as a function of the state of the switch 400 (on/off), for example as a function of the signals SET/RESET or the gate-source voltage V.sub.GS: [0132] when the switch 400 is closed (high gate-source voltage V.sub.GS) the diodes 4162.sub.1 and 4164.sub.1 are connected between the nodes G and S; and [0133] when the switch 400 is opened (low gate-source voltage V.sub.GS) the diodes 4162.sub.2 and 4164.sub.2 are connected between the nodes S and G.

[0134] Generally, a parasitic capacitance C.sub.P1 will be associated with the node between the diodes 4162.sub.1 and 4164.sub.1 and a parasitic capacitance C.sub.P2 will be associated with the node between the diodes 4162.sub.2 and 4164.sub.2. Preferably, these capacitances are increased voluntarily during the design process of the switch 400 and may be, e.g., between 100 fF (Femto-Farad) and several pF (Pico-Farad).

[0135] Accordingly, as shown in FIG. 14a, when the switch 400 is closed (ON), positive transitions at the terminal T1 (or T2) may be partially transferred through the diode 4162.sub.1 to the capacitance C.sub.P1, thereby charging the capacitance C.sub.P1 approximately to the voltage at the node T1. For example, assuming a forward voltage of 0.7 V for the diode 4162.sub.1, the capacitance C.sub.P1 will be charged to approximately 99.3 V for a maximum voltage of 100 V at the node T1. Conversely, the node G will have a higher voltage, e.g., 103.3 V, because the gate-source capacitance C.sub.GS maintains the voltage difference. Accordingly, the diode 4164.sub.1 blocks a discharging of the node G to the capacitance C.sub.P1 during this phase. Moreover, also the second branch comprising the diodes 4162.sub.2 and 4164.sub.2 is disconnected via the switch 4166.

[0136] Conversely, as shown in FIG. 14b, when a negative transition occurs, the voltage at the node G will decrease. For example, assuming a minimum voltage of 0 V at the node T1, the voltage at the node G would decrease, e.g., to 3.3 V. Accordingly, the diode 4164.sub.1 will become conductive and the charge at the capacitance C.sub.P1 will be transferred in part to the node G, thereby charging the gate-source capacitance C.sub.GS.

[0137] Conversely, as shown in FIGS. 15a and 15b the opposite behavior may be used to discharge the gate-source capacitance C.sub.GS via the second branch, i.e., the diodes 4162.sub.2 and 4164.sub.2, when the switch 400 is opened (OFF).

[0138] Specifically, as shown in FIG. 15a, when the switch 400 is opened (OFF), negative transitions at the terminal T1 may be used to discharge the capacitance C.sub.P2 through the diode 4164.sub.2.

[0139] Conversely, as shown in FIG. 15b, when a positive transition occurs, the voltage at the node G will increase and the diode 4162.sub.2 will become conductive, thereby discharging the gate-source capacitance C.sub.GS to the capacitance C.sub.P2.

[0140] FIG. 16 shows a second embodiment of a rectification circuit 416b, wherein the switch 4166 is implemented with two FET 4168 and 4170.

[0141] Specifically, in the embodiment considered, the diodes 4162.sub.2/4164.sub.2 and a p-channel FET 4168 are connected in series between the node G and the node S, and the diodes 4162.sub.1/4164.sub.1 and an n-channel FET 4170 are connected in series between the node S and the node G.

[0142] Specifically, in the embodiment considered, the anode of the diode 4162.sub.2 is connected to the node G, the cathode of the diode 4162.sub.2 is connected to the anode of the diode 4164.sub.2 and the p-channel FET 4168 is used to connect selectively the cathode of the diode 4164.sub.2 to the node S. In the embodiment considered, the gate of the transistor 4168 is connected to the node G.

[0143] Conversely, the cathode of the diode 4164.sub.1 is connected to the node G, the anode of the diode 4164.sub.1 is connected to the cathode of the diode 4162.sub.1 and the n-channel FET 4170 is used to connect selectively the anode of the diode 4162.sub.1 to the node S. In the embodiment considered, the gate of the transistor 4170 is connected to the node G. For simplicity, the capacitances C.sub.P1 and C.sub.P2 are omitted in the figures.

[0144] Accordingly, also in this case, the diodes 4162.sub.1/4164.sub.1 and 4162.sub.2/4164.sub.2, respectively, represent two opposite conductive paths which may be enabled selectively.

[0145] Accordingly, when the gate-source voltage V.sub.GS is greater than the threshold voltage V.sub.TH of the transistors 4168 and 4170 (see FIG. 17a), the transistor 4168 is opened and the transistor 4170 is closed, i.e., only the diodes 4162.sub.1 and 4164.sub.1 are connected between the node S and the node G, thereby permitting only a charging of the node G. Conversely, when the gate-source voltage V.sub.GS is smaller than the threshold voltage V.sub.TH of the transistors 4168 and 4170 (see FIG. 17b), the transistor 4168 is closed and the transistor 4170 is opened, i.e., only the diodes 4162.sub.2 and 4164.sub.2 are connected between the node G and the node S, thereby permitting only a discharging of the node G.

[0146] FIG. 18 shows a further embodiment of a rectification circuit 416c.

[0147] Specifically, in the embodiment considered, the rectification circuit 416c comprises a single branch comprising two (or more) diodes 4162 and 4164 connected in cascade, i.e., with the anode of the diode 4164 connected to the cathode of the diode 4162, wherein a capacitance C.sub.P is associated with the intermediate point between the two diodes 4162 and 4164.

[0148] In the embodiment considered, the rectification circuit 416c comprises moreover switching means configured to connect either: [0149] the anode of the diode 4162 to the node G and the cathode of the diode 4164 to the node S, thereby permitting a discharging of the gate-source capacitance C.sub.GS, or [0150] the anode of the diode 4162 to the node S and the cathode of the diode 4164 to the node G, thereby permitting a charging of the gate-source capacitance C.sub.GS.

[0151] For example, in the embodiment considered, two p-channel transistors 4168 and 4172 are connected in series between the nodes G and S, wherein the body diode of the two transistors are opposite and directed to the intermediate point between the transistors 4168 and 4172. Similarly, in the embodiment considered, two n-channel transistors 4170 and 4174 are connected in series between the nodes G and S, wherein the body diode of the two transistors are opposite and directed to the intermediate point between the transistors 4170 and 4174.

[0152] In the embodiment considered, the anode of the diode 4162 is connected (e.g., directly) to the intermediate point between the transistors 4170 and 4174 and the cathode of the diode 4164 is connected (e.g., directly) to the intermediate point between the transistors 4168 and 4172.

[0153] In the embodiments considered, the gates of the transistors 4168 and 4170 are connected to the node G, and the gates of the transistors 4172 and 4174 are connected to the node S. Accordingly, when the gate-source voltage V.sub.GS is greater than the threshold voltage V.sub.TH of the transistors (see FIG. 19a), the transistors 4168 and 4174 are opened and the transistors 4170 and 4172 are closed, i.e., the diodes 4162 and 4164 are connected between the node S and the node G, thereby permitting only a charging of the node G. Conversely, when the source-gate voltage V.sub.SG=−V.sub.GS is greater than the threshold voltage V.sub.TH (i.e., V.sub.GS<−V.sub.TH) of the transistors (see FIG. 19b), the transistors 4168 and 4174 are closed and the transistors 4170 and 4172 are opened, i.e., the diodes 4162 and 4164 are connected between the node G and the node S, thereby permitting only a discharging of the node G. Generally, the transistors 4168, 4170, 4172 and 4174 could also be driven as a function of the signals SET and RESET in order to achieve a substantially similar operation.

[0154] Accordingly, in the embodiments considered, the rectification circuits 416a, 416b and 416c are configured to: [0155] when the switch 400 is on, i.e., when the gate-source voltage V.sub.GS is high: [0156] a) when a positive transition is applied to the node T1, transfer charge from the node S to a capacitance C.sub.P/C.sub.P1, while inhibiting a transfer of charge from the node G to the capacitance C.sub.P/C.sub.P1, and [0157] b) when a negative transition is applied to the node T1, transfer charge from the capacitance C.sub.P/C.sub.P1 to the node G; and [0158] when the switch 400 is off, i.e., when the gate-source voltage V.sub.GS is low: [0159] a) when a negative transition is applied to the node T1, transfer charge from the capacitance C.sub.P/C.sub.P2 to the node S, while inhibiting a transfer of charge from the node G to the capacitance C.sub.P/C.sub.P2, and [0160] b) when a positive transition is applied to the node T1, transfer charge from the node G to the capacitance C.sub.P/C.sub.P2.

[0161] Specifically, in the rectifications circuits 416a, 416b and 416c, this is achieved by means of switching means configured: [0162] a) when the switch 400 is on, i.e., when the gate-source voltage V.sub.GS is high, connect two diodes 4162 and 4164 between the node G and the node S, wherein the diodes 4162 and 4164 are connected in cascade (i.e., the anode of the second diode 4164 is connected to the cathode of the first diode 4162), and wherein a capacitance C.sub.P/C.sub.P1 is associated with the intermediate point between the diodes 4162/4164, such that a conductive path is created permitting a current flow only from the node S to the node G, and [0163] b) when the switch 400 is off, i.e., when the gate-source voltage V.sub.GS is low, connect two diodes 4162 and 4164 between the node S and the node G, wherein the diodes 4162 and 4164 are connected in cascade (i.e., the anode of the second diode 4164 is connected to the cathode of the first diode 4162), and wherein a capacitance C.sub.P/C.sub.P2 is associated with the intermediate point between the diodes 4162/4164, such that a conductive path is created permitting a current flow only from the node G to the node S.

[0164] In the embodiments considered, the rectifications circuits 414a and 414b use two separate branches and switching means (4166 or 4168/4170) configured to enable one of these branches. Conversely, the rectifications circuit 414c comprises a single branch and switching means (4168-4174) configured to change the orientation of this branch between the nodes G and S.

[0165] FIG. 20 shows a further embodiment, highlighting that the set circuit 412a and the reset circuit 414b are not necessarily connected directly to the node G as shown in FIGS. 11 and 12. The connection of the circuits 412b and 414a will not be repeated at this point and reference can be made to FIGS. 8 to 12 for this purpose.

[0166] Specifically, in the embodiment considered, the circuits 412a and 414b are connected to the intermediate point between the diodes 4162 and 4164.

[0167] Accordingly, as shown in FIG. 21a, when the switch has to be closed (with the signal SET being set, e.g., to high), the circuit 412a will apply a positive voltage to the anode of the diode 4164. In case the gate-source voltage V.sub.GS is low, this positive voltage will switch on the transistor 4172 and the node G will be charged. For this reason, the diode 4164 may also be an active diode driven by means of the signal SET.

[0168] Conversely, as shown in FIG. 21b, when the switch has to be closed (with the signal RESET being set, e.g., to high), the circuit 414b will apply preferably a negative voltage to the cathode of the diode 4162. In case the gate-source voltage V.sub.GS is high, this negative voltage will switch on the transistor 4174 and the node G will be discharged. For this reason, the diode 4162 may also be an active diode driven by means of the signal RESET.

[0169] The same solution may also be used in the circuit 416a shown in FIG. 13. For example, the circuit 412a may be connected to the anode of the diode 4164.sub.1 (being possibly an active diode driven by means of the signal SET) and the circuit 414b may be connected to the cathode of the diode 4162.sub.2 (being possibly an active diode driven by means of the signal RESET).

[0170] The above embodiments have the advantage that the active diodes 4124, 4164/4164.sub.1, 4154 and 4162/4162.sub.2 are preferably high-voltage active diodes implemented, e.g., with power MOSFET having a complex structure and high parasitic capacitances, thereby generating automatically a high parasitic capacitance C.sub.P/C.sub.P1/C.sub.P2 at the intermediate point between the diodes.

[0171] Of course, without prejudice to the principles of the present disclosure, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present disclosure. For example, while the solutions in the forgoing have been described with regards to n-channel transistors SW1 and SW2, also p-channel transistors could be used, e.g., by exchanging the signals SET and RESET.

[0172] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.