METHOD OF MAKING SEMICONDUCTOR FERROELECTRIC MEMORY ELEMENT, AND SEMICONDUCTOR FERROELECTRIC MEMORY TRANSISTOR

Abstract

[Object] To provide a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150, without impairing the data retention property of not less than 10.sup.5 seconds and the data rewrite withstand property of not less than 10.sup.8 times, of those that have hitherto been developed, and the FeFET allowing data to be written with a writing voltage whose absolute value is not more than 3.3 volts.

[Means for Solving] In methods of making a device in which an insulator, a film made of constituent elements of a bismuth layered perovskite crystalline ferroelectric and a metal are sequentially formed in the indicated order on a semiconductor substrate and thereafter are annealed for ferroelectric crystallization, thereby preparing the device composed of the semiconductor, insulator, ferroelectric and metal, a method of making a semiconductor ferroelectric memory element in which the film is composed of Ca. Sr, Bi, Ta and oxygen atoms, the metal is Ir or Pt or an alloy of Ir and Pt, or Ru, and the annealing for ferroelectric crystallization is performed in a mixed gas having oxygen added to nitrogen or a mixed gas having oxygen added to argon.

Claims

1. In methods of making a device comprising a semiconductor substrate, an insulator, a ferroelectric and a metal in which the insulator, a film made of constituent elements of a bismuth layer perovskite crystalline ferroelectric and the metal are sequentially formed in the indicated order on a semiconductor substrate and thereafter are subjected to annealing for ferroelectric crystallization, a method of making a semiconductor ferroelectric memory element, wherein: said film comprises one selected from the class which consists of a film composed of strontium, bismuth, tantalum and oxygen, a film of calcium, strontium, bismuth, tantalum and oxygen, a film of strontium, bismuth, tantalum, niobium and oxygen, and a film of calcium, strontium, bismuth, tantalum, niobium and oxygen; said metal is composed of one selected from the class which consists of Ir, Pt, an alloy of Ir and Pt, and R; and said annealing for ferroelectric crystallization is performed in a mixed gas selected from the class which consists of one having oxygen added to nitrogen and one having oxygen added to argon.

2. A method of making a semiconductor ferroelectric memory element as set forth in claim 1, wherein said semiconductor substrate has a source and a drain region, said semiconductor ferroelectric memory element being a transistor.

3. A method of making a semiconductor ferroelectric memory element as set forth in claim 1, wherein said annealing for ferroelectric crystallization is performed at a temperature of not less than 730 degrees Celsius and not more than 800 degrees Celsius.

4. A method of making a semiconductor ferroelectric memory element as set forth in claim 1, wherein said metal is Ir, and said mixed gas having oxygen added to nitrogen has oxygen added to nitrogen at a volume proportion of not less than 0.0002 and not more than 0.02.

5. A method of making a semiconductor ferroelectric memory element as set forth in claim 1, wherein said metal is Pt, and said mixed gas having oxygen added to nitrogen has oxygen added to nitrogen at a volume proportion of more than 0.0007 and not more than 0.01.

6. A method of making a semiconductor ferroelectric memory element as set forth in claim 1, wherein said metal is an alloy of Ir and Pt alloyed at a weight proportion of 1 to 1, and said mixed gas having oxygen added to nitrogen has oxygen added to nitrogen at a volume proportion of more than 0.0001 and not more than 0.0004.

7. A method of making a semiconductor ferroelectric memory element as set forth in claim 1, wherein said annealing for ferroelectric crystallization is performed under a pressure of not less than 0.001 MPa and not more than 1 atmospheric pressure.

8. A method of making a semiconductor ferroelectric memory element as set forth in claim 1, wherein said insulator is composed of a metal oxide containing at least one of metallic elements of hafnium, zirconium, lanthanum, yttrium, aluminum, magnesium and manganese and comprises a laminate of such metal oxides.

9. A method of making a semiconductor ferroelectric memory element as set forth in claim 8, wherein said insulator is of a nitride selected from the class which consists of hafnium nitride and aluminum nitride.

10. A method of making a semiconductor ferroelectric memory element as set forth in claim 9, wherein said insulator is selected from the class which consists of one which is composed of said nitride and said metal oxide and one which is constituted of a lamination of said nitride and said metal oxide laminate.

11. A method of making a semiconductor ferroelectric memory element as set forth in claim 10, wherein said nitride is hafnium nitride and said metal oxide is HfO2.

12. A method of making a semiconductor ferroelectric memory element as set forth in claim 8, wherein said metal oxide is in the form of a film of HfO.sub.2 having a film thickness of not less than 1.3 nm and not more than 13 nm.

13. A method of making a semiconductor ferroelectric memory element as set forth in claim 1, wherein said annealing for ferroelectric crystallization is followed by characteristic adjustment annealing which is at least one of annealing in an oxygen gas and annealing in a mixed gas having hydrogen mixed with nitrogen.

14. A method of making a semiconductor ferroelectric memory element as set forth in claim 13, wherein annealing in the oxygen gas in the characteristic adjustment annealing is effected at an annealing temperature of not less than 600 degrees C. and not more than 700 degrees C.

15. A method of making a semiconductor ferroelectric memory element as set forth in claim 13, wherein in characteristic adjustment annealing, annealing in the mixed gas having hydrogen mixed with nitrogen is effected at an annealing temperature of not less than 350 degrees C. and not more than 450 degrees C.

16. A method of making a semiconductor ferroelectric memory element as set forth in claim 13, wherein in the characteristic adjustment annealing, annealing in the mixed gas having hydrogen mixed with nitrogen is effected for a time period of not less than 3 minutes and not more than 30 minutes.

17. In methods of making a device comprising a semiconductor substrate, an insulator, a ferroelectric and a metal in which the insulator, a film made of constituent elements of a bismuth layer perovskite crystalline ferroelectric and the metal are sequentially formed in the indicated order on the semiconductor substrate and thereafter are subjected to annealing for ferroelectric crystallization, a method of making a semiconductor ferroelectric memory element, wherein: said film comprises one selected from the class which consists of a film composed of strontium, bismuth, tantalum and oxygen, a film of calcium, strontium, bismuth, tantalum and oxygen, a film of strontium, bismuth, tantalum, niobium and oxygen, and a film of calcium, strontium, bismuth, tantalum, niobium and oxygen; said metal is composed of one selected from the class which consists of Ir, Pt, an alloy of Ir and Pt, and R; and said annealing for ferroelectric crystallization is performed in an oxygen atmosphere under a pressure of not less than 10 Pa and not more than 100 Pa.

18. A method of making a semiconductor ferroelectric memory element as set forth in claim 9, wherein said hafnium nitride is formed upon reaction between NH.sub.3 gas and a complex containing Hf in a growth chamber by a metal organic chemical vapor deposition process which comprises the steps of preparing a raw material liquid solution having the complex with Hf dissolved in a solvent; dispersing the raw material liquid solution into a carrier gas to form a raw material gaseous medium in a state of gas and liquid two phases; introducing the raw material gaseous medium while in the state of gas and liquid two phases into a vaporizing chamber to form a vapor thereof; and introducing the vapor into a film forming chamber.

19. A method of making a semiconductor ferroelectric memory element as set forth in claim 18, wherein said complex that contains hafnium is one of TEMAHF and TDEAHF.

20. A semiconductor ferroelectric memory transistor, comprising a semiconductor substrate having a source and a drain region; and an insulator, a ferroelectric and a metal which are layered in this order on the semiconductor substrate, wherein: said ferroelectric is one selected from the class which consists of a bismuth layer perovskite ferroelectric composed of strontium, bismuth, tantalum and oxygen, a bismuth layer perovskite ferroelectric composed of calcium, strontium, bismuth, tantalum and oxygen, a bismuth layer perovskite ferroelectric composed of strontium, bismuth, tantalum, niobium and oxygen, and a bismuth layer perovskite ferroelectric composed of calcium, strontium, bismuth, tantalum, niobium and oxygen; said metal is one selected from the class which consists of Ir, Pt, an alloy of Ir and Pt, and Ru; and said ferroelectric has a film thickness of more than 59 nm and less than 150 nm, said semiconductor ferroelectric memory element being usable to write data with a writing voltage whose absolute value is not more than 3.3 volts, and having an ability to retain data for a time period of not less than 10.sup.5 seconds.

21. A semiconductor ferroelectric memory transistor as set forth in claim 20, wherein the transistor is capable of rewriting data not less than 10.sup.8 times.

22. A semiconductor ferroelectric memory transistor as set forth in claim 20, wherein an interfacial layer is formed between said semiconductor substrate and said insulator and has a thickness of less than 3.4 nm.

Description

BRIEF EXPLANATION OF THE DRAWING

[0052] FIG. 1 It is a sectional view illustrating a step in making a semiconductor ferroelectric memory element made in a first form of implementation of the present invention.

[0053] FIG. 2 It is a sectional view illustrating a step in making a semiconductor ferroelectric memory element made in a second form of implementation of the present invention.

[0054] FIG. 3 It is a sectional view of the semiconductor ferroelectric memory element made in the first form of implementation of the present invention.

[0055] FIG. 4 It is a sectional view of the semiconductor ferroelectric memory element made in the second form of implementation of the present invention.

[0056] FIG. 5 It is a sectional TEM photograph of Example 02B of the invention.

[0057] FIG. 6 It includes a graph (a) representing a relationship between a drain current and a gate voltage of a FeFET in Example 02B of the present invention and a graph (b) representing a relationship between a sweep amplitude V.sub.amp and a memory window.

[0058] FIG. 7 It is a sectional TEM photograph of Example 21C of the invention.

[0059] FIG. 8 It is a graphical representation of an electric capacitance with respect to a gate voltage between metal and a semiconductor substrate in Example 02A of the invention.

[0060] FIG. 9 It shows a relationship between a drain current and a gate voltage in Example 26C of the invention in which the gate lamination has a structure and a thickness of Ir (75 nm)/CSBT (x=0.2, 135 nm)/Hf—La—Al—O (5 nm)/Si, having the insulator 5 (I layer) of a composition ratio of HfO.sub.2:LaAlO.sub.3=7:3.

[0061] FIG. 10 It is a graph illustrating a relationship between a drain current and a gate voltage in Example 16A of the invention in which the gate lamination has a structure and a thickness of Ir (75 nm)/CSBT (x=0.25, 135 nm)/Zr—Y—O (5 nm)/Si, having the insulator 5 (I layer) of Zr—Y—O.

[0062] FIG. 11 It is a graph illustrating a relationship between a drain current and a gate voltage in Example 302B of the invention in which the gate lamination has a structure and a thickness of Ir (75 nm)/CSBT (x=0.2, 135 nm)/HfO.sub.2 (4 nm)/Si.

[0063] FIG. 12 It is a graph illustrating a relationship between a drain current and a gate voltage in Example 12B of the invention in which the gate lamination has a structure and a thickness of Ir (75 nm)/CSBT (x=0.2, 135 nm)/HfO.sub.2 (4 nm)/Si.

[0064] FIG. 13 It is a graph illustrating a relationship between a drain current and a gate voltage in Example 09F of the invention in which the gate lamination has a structure and a thickness of Ir (75 nm)/CSBT (x=0.15, 120 nm)/HfO.sub.2 (5 nm)/Si.

[0065] FIG. 14 It is a graph illustrating a relationship between a drain current and a gate voltage in Example 03C of the invention in which the gate lamination has a structure and a thickness of Ir (75 nm)/CSBT (x=0.2, 135 nm)/Hf—Mg—O (5 nm)/Si. Annealing for crystallization is performed in Ar—O.sub.2.

[0066] FIG. 15 It is a graph illustrating a relationship between a volume proportion of O.sub.2 to N.sub.2 in annealing for ferroelectric crystallization and a memory window of I.sub.d−V.sub.g characteristic in an embodiment of FeFET made using the volume proportion and metal 4 of Ir, according to the present invention.

[0067] FIG. 16 It is a graph illustrating a relationship between an annealing temperature of the process of annealing for ferroelectric crystallization and a memory window of I.sub.d−V.sub.g characteristic of a FeFET made according to the present invention.

[0068] FIG. 17 It is a graph in summary of Examples of the invention in which annealing for ferroelectric crystallization is performed in the environment of a pressure lower than one atmospheric pressure in accordance with the present invention.

[0069] FIG. 18 It is a graph illustrating a relationship between a thickness of HfO.sub.2 used for the insulator 2 and a memory window, according to the present invention.

[0070] FIG. 19 It is a graph illustrating I.sub.d−V.sub.g characteristics before and after annealing in a first process of characteristic adjustment annealing in Example 02B of the invention.

[0071] FIG. 20 It is a graph illustrating a relationship between an annealing temperature in the first process and a rate of change of memory window and a rate of change of SS value, according to the present invention.

[0072] FIG. 21 It is a graph illustrating relationships between a drain current and a gate voltage after (solid curve), and between those before (broken curve), annealing in a second process of characteristic adjustment is performed at a temperature of 400 degrees C. and a time period of 30 minutes in Example 21C of the invention.

[0073] FIG. 22 It is a graph illustrating relationships between a drain current and a gate voltage after (solid curve), and between those before (broken curve), annealing in a second process of characteristic adjustment is performed at a temperature of 400 degrees C. and a time period of 5 minutes in Example 23C of the invention.

[0074] FIG. 23 It is a graph illustrating results of data rewrite withstand tests for Example 02B of the invention, using rewrite pulses alternating between −3.3 volts and +3.3 volts.

[0075] FIG. 24 It is a graph illustrating results of measurement of data retention property for Example 02B (with rewrite voltages of +3.3 volts) of the invention.

[0076] FIG. 25 It is a graph illustrating results of data rewrite withstand tests for Example 27E of the invention.

[0077] FIG. 26 It is a graph illustrating results of data rewrite withstand tests for Example 12H of the invention.

[0078] FIG. 27 It is a graph illustrating results of data rewrite withstand tests for Example 27F of the invention.

[0079] FIG. 28 It is a graph illustrating results of data rewrite withstand tests for Example 12H of the invention.

[0080] FIG. 29 It is an explanatory view illustrating a process of making an Example 302B of the invention.

[0081] FIG. 30 It illustrates properties of FeFETs made by the prior art, including a graph (a) illustrating a relationship between a drain current and a gate voltage of a FeFET made of a ferroelectric of Ca.sub.0.2 Sr.sub.0.8 Bi.sub.2 Ta.sub.2 O.sub.9 and having a film thickness of 120 nm, a graph (b) illustrating that of a FeFET made of a ferroelectric of Ca.sub.0.2 Sr.sub.0.8 Bi.sub.2 Ta.sub.2 O.sub.9 and having a film thickness of 160 nm, (c) a graph illustrating a relationship between a memory window and a film thickness of prior-art FeFETs made of Ca.sub.0.2 Sr.sub.0.8 Bi.sub.2 Ta.sub.2 O.sub.9 and of 120 nm, 160 nm and 200 nm thick in which marked by O and S are ones annealed for 30 minutes at temperatures of 775 and 800 degrees C., respectively, and to obtain a memory window, a gate voltage sweep range I is set at 0.5 volts±3.3 volts, and a graph (d) illustrating a memory window with respect to a sweep amplitude of 3.3 volts and 5.0 volts.

[0082] FIG. 31 It is a diagram illustrating energy and voltage divisions found depth-wise at various gate parts when a positive data rewrite voltage is applied to the gate of FeFET composed of Pt/Sr Bi.sub.2 Ta.sub.2 O.sub.9/Hf—Al—O/Si.

FORMS OF IMPLEMENTING THE INVENTION

[0083] (Forms of Implementation)

[0084] FIG. 1 is a sectional view diagrammatically illustrating a course of making a semiconductor ferroelectric memory element made in a first form of implementation of the present invention. Numeral 1 designates a semiconductor substrate. FIG. 2 is a sectional view diagrammatically illustrating a course of making a semiconductor ferroelectric memory element made in a second form of implementation of the present invention. In the second form of implementation, a semiconductor substrate 1 is shown having a source region 6 and a drain region 7. The semiconductor substrate 1 is composed of silicon or a semiconductor having a silicon component. It may also be of a mixed crystal of Si and Ge or of SiC. In lieu of a semiconductor substrate, it may also be a SOI (silicon on insulator) substrate. Character 3a denotes a layer formed of a composition, as a ferroelectric predecessor, of constituent elements of a Bi layered perovskite crystal structure. Prior to annealing for ferroelectric crystallization, the composition has not yet be of Bi layered perovskite crystal structure. Representative are a film made of strontium, bismuth, tantalum and oxygen elements, a film of calcium, strontium, bismuth, tantalum and oxygen, a film of strontium, bismuth, tantalum, niobium and oxygen, and a film of calcium, strontium, bismuth, tantalum, niobium and oxygen. It may also be a film of bismuth, titan and oxygen, a film of bismuth, lanthanum, titanium and oxygen or a film of bismuth, neodymium, titanium and oxygen. Metal 4 may be Ir, Pt, Ru or an alloy of them.

[0085] After up to the meal are formed, the film 3a is annealed in a suitable environment for ferroelectric crystallization. This causes its composition to transform into a ferroelectric 3. The ferroelectric 3 is composed of a material mainly constituted by a Bi layer perovskite which has been found robust in the fatigue of polarization reversal of ferroelectrics. In accordance with a composition of elements of the film, the main constituent of such perovskite may be Sr.sub.2 Bi.sub.2 Ta.sub.2 O.sub.9; Ca.sub.x Sr.sub.1-x Bi.sub.2 Ta.sub.2 O.sub.9 as a substitute of a part of Sr with Ca in Sr.sub.2 Bi.sub.2 Ta.sub.2 O.sub.9; Sr Bi.sub.2 (Ta.sub.1-xNb.sub.z).sub.2 O.sub.9 and Ca in Sr.sub.2 Bi.sub.2 Ta.sub.2 O.sub.9 as substitutes of parts of Ta with Nb in Sr.sub.2 Bi.sub.2 Ta.sub.2 O.sub.9; Ca.sub.x Sr.sub.1-x Bi.sub.2 Ta.sub.2 O.sub.9 and Ca.sub.x Sr.sub.1-x Bi.sub.2 Ta.sub.2 O.sub.9; Bi.sub.4 Ti.sub.3 O.sub.12; (Bi, La).sub.4 Ti.sub.3 O.sub.12; and (Bi, Nd).sub.4 Ti.sub.3 O.sub.12. Ca.sub.x Sr.sub.1-x Bi.sub.2 Ta.sub.2, Sr Bi.sub.2 (Ta.sub.1-zNb.sub.z).sub.2 O.sub.9 and Sr Bi.sub.2 (Ta.sub.1-zNb.sub.z).sub.2 O.sub.9 are similar in crystal structure and properties and may interchangeably be used. It has been found that annealing the film 3a after formation of up to the metal 4 on the substrate makes an interfacial region between the ferroelectric 3 and the metal 4 stable in quality, this being connected with and leading to excellent data retention capability and exceeding data rewriting tolerance. Upon zealous investigations in annealing to crystallize the ferroelectric, it has been found important that annealing be performed in the environment of a mixed gas having oxygen added to an inert gas such as N.sub.2 or Ar. Passing through the annealing to crystallize the ferroelectric, the first form of implementation comes out whose cross section is diagrammatically shown in FIG. 3, Passing through the annealing to crystallize the ferroelectric, the second form of implementation comes out whose cross section is diagrammatically shown in FIG. 4. An interfacial layer 5 mainly composed of SiO.sub.2 is formed on a surface region of the semiconductor substrate 1. The term “interfacial layer 5” may hereinafter be so simply termed, suggesting that it be so composed. While the interfacial layer 5 which is of electrical insulating properties can be defined as included in an insulator 2, it may well be regarded as a part of the semiconductor substrate in the present invention. Either way, it is only a question of definition and mode. Electrical conduction in a semiconductor occurs at an interface between the interfacial layer and the internal semiconductor.

[0086] An embodiment of the invention that has been annealed for the ferroelectric crystallization is analyzed using a sectional transmission electron microscope (sectional TEM) and it has been found possible that the interfacial layer 5 mainly composed of SiO.sub.2 be made thinner than 3.4 nm. In Example 02B of the invention disclosed in FIG. 5, the interfacial layer 5 mainly composed of SiO.sub.2 has a thickness of 2.6 nm. A layer denoted by character IL in FIG. 5 is the interfacial layer 5. A FeFET in this Example has Ir having a thickness of 75 nm, CSBT (Ca Sr Bi Ta) of x=0.2 having a thickness of 135 nm and HfO.sub.2 having a thickness of 4 nm, which are formed on the semiconductor substrate. A ferroelectric of CSBT of x=0.2 signifies that the ferroelectric is mainly composed of Ca.sub.x Sr.sub.1-x Bi.sub.2 Ta.sub.2 O.sub.9 where x=0.2. This gate lamination is referred to briefly as Ir (75 nm)/CSBT (x=0.2, 135 nm)/HfO.sub.2 (4 nm)/Si. This brief reference will hereinafter be used suitably to the extent that it brings about no confusion. The relationship between a drain current and a gate voltage: I.sub.d−V.sub.g of the n channel FeFET is disclosed in FIG. 6(a). The drain current is represented in logarithm. This FeFET has a gate length (L) of 10 micro-m and a gate width of 200 micro-m. V.sub.g is swept around a center V.sub.c=0 volt, with a sweep amplitude V.sub.amp=3.3 V and in a sweep range which is V.sub.c+V.sub.amp=3.3 volts from V.sub.c−V.sub.amp=−3.3 volts. V.sub.g is swept in reciprocation between −3.3 volts and +3.3 volts. While there are Examples, too, hereafter in which measurement is made with V.sub.c that is not zero, it is ensured to achieve V.sub.c=0 by suitably selecting the kind and concentration of an impurity on the side of a semiconductor in the use of such technique as ion implantation. Note that a sweep amplitude V.sub.amp refers to the absolute value of a data writing voltage into the FeFET. While in measurement of I.sub.d−V.sub.g the sweep range may hereafter be referred to as Vc±Vamp, note that it signifies that V.sub.g is swept in reciprocation between V.sub.c−V.sub.amp and V.sub.c+V.sub.amp. Along the direction of the arrows as shown, the drain current is changed. The drain current (I.sub.d) as shown is normalized for a current per a gate width of 1 micro-m. In achieving this I.sub.d−V.sub.g relationship, the drain voltage (V.sub.d), source voltage (V.sub.s), and substrate voltage (V.sub.s) are so conditioned that V.sub.d=0.1 volt and V.sub.s=V.sub.sub=0 volt. Hereafter, unless otherwise indicated, an I.sub.d−V.sub.g relationship is measured under such V.sub.d, V.sub.s and V.sub.sub voltage conditions. If threshold voltages are defined as corresponding to I.sub.d=1×10.sup.−8 amperes per micro-m, in FIG. 6(a) they are seen to be gate voltages V.sub.a and V.sub.b at points (a) and (b), respectively. If a difference between them is defined as a memory window V.sub.w, it is seen in FIG. 6(a) that V.sub.w=V.sub.a−V.sub.b is equal to 0.59 volt which apparently is wide enough compared with values of the memory window in the prior art (shown in FIG. 30). In FIG. 6(b) there is shown a relationship between a sweep amplitude and a memory window. It is shown that at V.sub.amp=2.7 volts, =3.6 volts and =3.9 volts, Vw=0.40 volts, =0.69 volts and =079 volts, respectively. Compared with those of the prior art shown in FIG. 30d, the memory window here is markedly widened. Especially, even at a small writing voltage as V.sub.amp=2.7 volts, it becomes apparent that V.sub.w=0.40 volts. These manifest improvements are apparently due to a reduction in thickness of the interfacial layer down to a thickness of 2.6 nm which should lower the voltage applied thereto in data writing, thereby permitting an inversion in electric polarization to be initiated at a lower writing voltage.

[0087] In Example 21C of the invention disclosed in FIG. 7, it is found from a sectional TEM analysis that an interfacial layer 5 mainly composed of SiO.sub.2 has a thickness of 2.5 nm. In this Example, on a semiconductor substrate 1 after an oxide film on its surface is removed by a buffered hydroacid fluoride, the silicon surface is oxynitrided to a depth of 1.4 nm in an environment of reduced pressure, leaving “SiON (1.4 nm thick)/Si” as it is briefly termed. The lamination or structure of layers in this Example comprises a metal layer of Ir having a thickness of 150 nm, a ferroelectric layer of CSBT where x=0.2, and an insulator layer of HfO.sub.2 having a thickness of 6 nm. As disclosed in FIG. 7, the interfacial layer 5 is formed mainly composed of SiO.sub.2 initially united with a layer of oxynitride of 1.4 nm thick. A layer denoted by IL in FIG. 7 is the interfacial layer 5. The thickness of the interfacial layer 5 is 2.5 nm which is sufficiently thinner than 3.4 to 5 nm in the prior art.

[0088] Example 02A represents an embodiment of the first form of implementation 1 of the present invention. The laminated gate structure comprises Ir (75 nm)/CSBT (x=0, 2.135 nm)/HfO.sub.2 (4 nm)/Si. The semiconductor substrate is Si of p type. A relationship of electric capacitance with respect to gate voltage: C.sub.g−V.sub.g is measured, giving a graph shown in FIG. 8. Metal Ir is planar in form and of a square having a side of 100 micro-m. The gate voltage after rising from −3.3 volts to +3.3 volts is returned to −3.3 volts. An AC voltage having an amplitude of 0.1 volts and an AC frequency of 100 kHz is used. As seen from the Figure, a memory window V.sub.w of 0.56 volts is evaluated from the C.sub.g−V.sub.g curves. V.sub.w is evaluated with a gate voltage where C.sub.g=100 F/cm.sup.2.

[0089] Explanation is given in detail of forming of the laminated structure.

[0090] The semiconductor substrate 1 is of silicon or of a semiconductor having a silicon component. It may be a mixed crystal of Si and Ge, or SiC. In lieu of the semiconductor substrate there may be used an SOI (silicon on insulator) substrate. Prior to attaching an insulator 2 to the semiconductor substrate, it is important that an oxide film on its surface be removed. The process step of forming the insulator 2 is effected directly upon removal of the surface oxide film, or after the semiconductor substrate surface is nitrided or oxynitrided. The nitride or oxynitride film formed has a thickness preferably of not more than 1.5 nm. Any process may be used to make it. For example, the surface oxide film is removed by immersion in a solution of buffered or unbuffered fluorinated acid. A nitride film may, for example, be formed by introducing NH.sub.3 gas into an atmosphere of reduced pressure and effecting rapid thermal annealing (RTA). An oxynitride film may, for example, be formed by introducing O.sub.2 gas in an atmosphere of reduced pressure and effecting rapid thermal annealing (RTA) and thereafter introducing NH.sub.3 gas in an atmosphere of reduced pressure and effecting rapid thermal annealing (RTA).

[0091] Insulator 2

[0092] The insulator 2 is required to be elaborate and to diminish the leakage current between the gate and the semiconductor substrate surface. Further, in the process of making a FeFET, it is also requited, not to cause inter-diffusion of and to produce no chemical reaction product from, elements of the film 3a, the ferroelectric 3, the semiconductor substrate 1. Further, it is preferred that the insulator 2 be high in dielectric constant so that a gate voltage applied to the FeFET may effectively be applied to the ferroelectric 3. Furthermore, it is preferred that the insulator 2 should have an electron affinity (difference in energy between the vacuum level and the lowermost end of conduction bands) smaller than that of the ferroelectric 3, and further that the insulator 2 should have an ionization potential (difference in energy between vacuum level and the uppermost end of conduction bands) larger than that of the ferroelectric 3. If the electron affinity of the insulator 2 is larger than that of the ferroelectric 3, the insulator 2 between the ferroelectric 3 and the interfacial layer 5 mainly composed of SiO.sub.2 on the semiconductor substrate surface tends to become a well for conductive electrons. Due to a leakage current, electrons once they enter the well are hard to come off therefrom; the well providing for a collecting place for incoming electrons. As a result, electrons are extant in the insulator 2, and if they change, the threshold voltage of the FeFET will be caused to shift by a mechanism separate from that of switching between polarizations of the ferroelectric. If the ionization potential of the insulator 2 is lower than that of the ferroelectric, the insulator 2 between the ferroelectric 3 and the interfacial layer 5 mainly composed of SiO.sub.2 on the semiconductor substrate surface tends to become a well for positive holes. Due to a leakage current, positive holes once they enter the well are hard to come off therefrom; the well providing for a collecting place for incoming positive holes. As a result, positive holes are extant in the insulator 2, and if they change, the threshold voltage of the FeFET will be caused to shift by a mechanism separate from that of switching between polarizations of the ferroelectric. Note further that since the height of a barrier of SiO.sub.2 as of Si for electrons is smaller than for positive holes and injection of charges from the semiconductor substrate into the insulator 2 is more prone to occur with electrons than with positive holes, it is preferred that the electron affinity of the insulator 2 should be smaller than that of the ferroelectric 3, than that the ionization potential of the insulator 2 should be higher than that of the ferroelectric 3. The insulator 2, regardless of its kinds if they satisfy these requirements, should preferably be a single oxide or mixed oxides or layered oxides of elements such as hafnium, zirconium, lanthanum, yttrium, aluminum, magnesium and/or manganese. It is also useful to achieve the object of diminishing a leakage current to add nitrogen to the oxides listed. It is also preferable to compose the insulator 2 of one or more of aluminum nitride, hafnium nitride, and mixed nitride of aluminum and hafnium, which are found to act to reduce oxygen diffusing into the ferroelectric in the process step of annealing for its crystallization and thus to reduce the extent in which to form an interfacial layer 5 mainly composed of SiO.sub.2. It is preferable to use a composite compound and layered composite compounds of a nitride such as aluminum nitride, hafnium nitride, or a mixed nitride of aluminum and hafnium and an oxide as an insulator that satisfies the abovementioned requirements as to the insulator 2. In addition, a material may be used that is not an insulator prior to the process step of ferroelectric crystallization annealing and which thereafter comes to satisfy the abovementioned requirements to form the ferroelectric 2.

[0093] Since it is preferred that an interfacial layer 5 mainly composed of SiO.sub.2 be thinner than 3.4 nm as mentioned above, an SiO.sub.2 equivalent film thickness (EOT) of an insulator 2 be also smaller than 3.4 nm and let to stay not less than 0.2 nm and not more than 2 nm, so that a voltage may equally be applied to the interfacial layer 5 and to the insulator 2. Denoting a specific dielectric constant of the insulator 2 as kin and a dielectric constant of SiO.sub.2 as ksio.sub.2, it follows that the insulator has an actual film thickness of di=(kin/ksio.sub.2)*EOT. Using kin=25 and k sio.sub.2=3.9 if the insulator 2 is HfO.sub.2, it is seen that an actual film thickness of HfO.sub.2 that corresponds to the EOT that is not less than 0.2 nm and not more than 2 nm becomes not less than 1.3 nm and not more than 13 nm.

[0094] An insulator 2 may be formed by any process that meets the abovementioned requirements and may suitably be formed by pulse laser deposition, sputtering, metal organic chemical vapor deposition, atomic layer deposition or the like technique.

[0095] Film 3a

[0096] The film 3a is a film composed of elements constituting a Bi layer perovskite. Prior to a process step of crystallization annealing, the film has not yet had a Bi layer perovskite crystal structure. Representative of the film 3a are a film of elements of strontium, bismuth, tantalum and oxygen, a film of calcium, strontium, bismuth, tantalum and oxygen, a film of strontium, bismuth, tantalum, niobium and oxygen, and a film of calcium, strontium, bismuth, tantalum, niobium and oxygen, it may also be a film of bismuth, titanium and oxygen, a film of bismuth, tantalum, titanium and oxygen, or a film of bismuth, neodymium, titanium and oxygen.

[0097] The film 3a may be formed by pulse laser deposition, sputtering, or metal chemical vapor deposition, metal organic decomposition (MOD or sol-gel technique or the like.

[0098] Metal 4

[0099] The metal 4 may be selected to be a pure metal or an alloy thereof. By forming metal 4 on the film 3a and thereafter annealing the film to effect ferroelectric crystallization, there is yielded a FeFET that is excellent in data retention property and rewrite withstand property. Annealing for ferroelectric crystallization is effected preferably at a temperature of 700 to 820 degrees C. and for a time period of 10 to 60 minutes. A material is thus called for to meet the annealing conditions, After zealous investigations, it has been found that Ir, Pt, or an alloy of Ir and Pt, or Ru is suitable.

[0100] While there is no particular limitation in how metal 4 is formed, it may be formed, for example, by sputtering, metal organic chemical vapor deposition or electron beam vapor deposition technique.

[0101] Annealing for Ferroelectric Crystallization

[0102] After metal 4 is formed, annealing for ferroelectric crystallization is effected in a suitable temperature environment. This will transform the film 3a into a ferroelectric 3. The ferroelectric 3 is constituted by a material mainly composed of a Bi layered perovskite that is found robust in fatigue of ferroelectric polarization reversal. According to a composition of elements of the film 3a, its main component may be Sr.sub.2 Bi.sub.2 Ta.sub.2 O.sub.9; Ca.sub.x Sr.sub.1-x Bi.sub.2 Ta.sub.2 O.sub.9 as a substitute of a part of Sr with Ca in Sr.sub.2 Bi.sub.2 Ta.sub.2 O.sub.9; Sr Bi.sub.2 (Ta.sub.1-z Nb.sub.z).sub.2 O.sub.9 and Ca in Sr.sub.2 Bi.sub.2 Ta.sub.2 O.sub.9 as substitutes of parts of Ta with Nb in Sr.sub.2 Bi.sub.2 Ta.sub.2 O.sub.9; Ca.sub.x Sr.sub.1-x Bi.sub.2 Ta.sub.2 O.sub.9 and Ca.sub.x Sr.sub.1-x Bi.sub.2 Ta.sub.2 O.sub.9; Bi.sub.4 Ti.sub.3 O.sub.12; (Bi, La).sub.4 Ti.sub.3 O.sub.12; and (Bi, Nd).sub.4 Ti.sub.3 O.sub.12. It has been found that annealing after formation of up to the metal 4 makes an interfacial region between the ferroelectric 3 and the metal 4 stable in quality, this being connected with and leading to excellent data retention capability and exceeding data rewriting tolerance. Upon zealous investigations, in annealing to crystallize the ferroelectric it has been found important that it be performed in the environment of a mixed gas having oxygen added to an inert gas such as N.sub.2 or Ar. It has been confirmed by an X-ray analysis process that the ferroelectric 3 which has undergone annealing for ferroelectric crystallization has a Bi layered perovskite crystal structure. The ferroelectric should have a thickness df preferably such that 59 nm<d<150 nm. More specifically, to lessen forming an interfacial layer 5 mainly composed of SiO.sub.2, it is important that oxygen as a component of the gaseous atmosphere used in annealing for ferroelectric crystallization should be reduced as much as possible in nitrogen or argon as its main component. At the same time, in order to transform the film 3a into a ferroelectric 3 of Bi layer perovskite, the ferroelectric being an oxide requires that there exist a degree of oxygen in the atmospheric gas. It is further necessary that metal 4 should withstand the annealing. With Ir, Pt, an alloy of Ir and Pt, and Ru there are available suitable amounts, respectively, of oxygen gas.

[0103] Forming of the laminated structure is disclosed below in detail through Examples of the invention. In Example 26C, the insulator 2 is of a composite oxide of hafnium, lanthanum and aluminum: (Hf—La—Al—O), having a makeup molar ratio, HfO.sub.2: LaAlO.sub.3=7:3. The structure and thickness of a gate laminate are: Ir (75 nm)/CSBT (x=0.2, 135 nm)/Hf—La—Al—O (5 nm)/SL In an atmosphere having oxygen mixed with N.sub.2 (the volume ratio of N.sub.2 to O.sub.2 being 1:0.001), annealing for ferroelectric crystallization is effected at a temperature of 760 degrees C. and for a time period of 30 minutes. FIG. 9 is a result of measurement of I.sub.d−V.sub.g. With a gate voltage that is swept in a range from −3.3 volts to +3.3 volts there is observed a memory window: V.sub.w=0.49 volts. In Example 16A, the insulator 2 is of a composite oxide of zirconium and yttrium: (Zr—Y—O), having a makeup molar ratio, ZrO.sub.2: Y.sub.2O.sub.3=92:8. The structure and thickness of a gate laminate are: Ir (75 nm)/CSBT (x=0.25, 135 nm)/Zr—Y—O (5 nm)/Si. In an atmosphere having oxygen mixed with N.sub.2 (the volume ratio of N.sub.2 to O.sub.2 being 1:0.001), annealing for ferroelectric crystallization is effected at a temperature of 760 degrees C. and for a time period of 30 minutes. FIG. 10 is a result of measurement of I.sub.d−V.sub.g. With a gate voltage that is swept in a range from −3.3 volts to +3.3 volts there is observed a memory window: V.sub.w=0.37 volts. In Example 302B, the insulator 2 is of HfO.sub.2. The structure and thickness of a gate laminate are: Ir (75 nm)/CSBT (x=0.2, 135 nm)/Hf O.sub.2−(4 nm)/Si. In an atmosphere having oxygen mixed with N.sub.2 (the volume ratio of N.sub.2 to O.sub.2 being 1:0.001), annealing for ferroelectric crystallization is effected at a temperature of 750 degrees C. and for a time period of 30 minutes. FIG. 11 is a result of measurement of I.sub.d−V.sub.g. With a gate voltage that is swept in a range from 0.5-3.3 volts to 0.5+3.3 volts there is observed a memory window: V.sub.w=0.64 volts. In Example 20C, the ferroelectric contains Nb. The structure and thickness of a gate laminate are: Ir (75 nm)/Ca.sub.0.2 Sr.sub.0.8 Bi.sub.2 (Ta.sub.0.75 Nb.sub.0.28).sub.2 O.sub.9 (135 nm)/Hf O.sub.2 (5 nm)/Si. In an atmosphere having oxygen mixed with N.sub.2 (the volume ratio of N.sub.2 to O.sub.2 being 1:0.001), annealing for ferroelectric crystallization is effected at a temperature of 793 degrees C. and for a time period of 30 minutes. With a gate voltage that is swept in a range from −3.3 volts to +3.3 volts there is observed a memory window: V.sub.w=0.28 volts.

[0104] In Example 12B, the insulator 2 is a laminated film having a layer of hafnium nitride having a thickness of 2 nm deposited on Si and a layer of HfO.sub.2 having a thickness of 4 nm deposited on the Hf—N layer. The structure and thickness of a gate laminate are: Ir (75 nm)/CSBT (x=0.2, 135 nm)/HfO.sub.2 (4 nm)/Hf—N (2 nm)/Si. In an atmosphere having oxygen mixed with N.sub.2 (the volume ratio of N.sub.2 to O.sub.2 being 1:0.001), annealing for ferroelectric crystallization is effected at a temperature of 780 degrees C. and for a time period of 30 minutes. FIG. 12 is a result of measurement of I.sub.d−V.sub.g. With a gate voltage that is swept in a range from 0.5-3.3 volts to 0.5+3.3 volts there is observed a memory window: V.sub.w=0.57 volts. In Example 25C, the insulator 2 is a laminated film having a layer of hafnium nitride having a thickness of 2 nm deposited on Si and a layer of HfO.sub.2 having a thickness of 4 nm deposited on the Hf—N layer. The structure and thickness of a gate laminate are: Ir (75 nm)/CSBT (x=0.2, 135 nm)/HfO.sub.2 (4 nm)/Al—N (2 nm)/Si. In an atmosphere having oxygen mixed with N.sub.2 (the volume ratio of N.sub.2 to O.sub.2 being 1:0.001), annealing for ferroelectric crystallization is effected at a temperature of 780 degrees C. and for a time period of 30 minutes. A result of measurement of I.sub.d−V.sub.g: with a gate voltage that is swept in a range from −3.3 volts to +3.3 volts there is observed a memory window: Vw=0.52 volts. In Example 18C, the insulator 2 is a layer of hafnium nitride having a thickness of 5 nm. The structure and thickness of a gate laminate are: Ir (75 nm)/CSBT (x=0.2, 135 nm)/Hf—N (4 nm)/Si. In an atmosphere having oxygen mixed with N.sub.2 (the volume ratio of N.sub.2 to O.sub.2 being 1:0.0006), annealing for ferroelectric crystallization is effected at a temperature of 750 degrees C. and for a time period of 30 minutes. A result of measurement of I.sub.d−V.sub.g: with a gate voltage that is swept in a range from −3.3 volts to +3.3 volts there is observed a memory window: V.sub.w=0.39 volts. Example 402A is an Example in which use is made of CSBT of x=0.3. The structure and thickness of a gate laminate are: Ir (75 nm)/CSBT (x=0.3, 135 nm)/Hf O.sub.2−(5 nm)/Si. In an atmosphere having oxygen mixed with N.sub.2, annealing for ferroelectric crystallization is effected at a temperature of 793 degrees C. and for a time period of 30 minutes. A result of measurement of I.sub.d−V.sub.g: with a gate voltage that is swept in a range from −3.3 volts to +3.3 volts there is observed a memory window: V.sub.w=0.42 volts.

[0105] Results of Examples in which likewise in Example 12B, the insulator 2 is a laminated film formed of a layer of hafnium nitride (Hf—N) deposited on Si and a layer of HfO.sub.2 deposited on the Hf—N layer are put together in Table 1. The gate laminate is structured commonly of Ir/CSBT (x=0.2)/HfO.sub.2/Hf—N/Si. The memory window of I.sub.d−V.sub.g characteristic has values found with a gate voltage swept from V.sub.c−3.3 volts to V.sub.c+3.3 volts. Hf—N is formed by a metal organic chemical vapor deposition (MOCVD) technique.

[0106] Making conditions becoming a key to the MOCVD technique respectively for the Examples are listed in Table 1. The flow of NH.sub.3 should preferably be not less than 9 sccm and not more than 20 sccm. Ranging it so is found to achieve a memory window of not less than 0.4 volt. Also, the susceptor temperature should preferably be not less than 260 degrees C. and not more than 400 degrees C. Hf—N should have a thickness of not less than 1 nm and not more than 3.1 nm. The result of sectional TEM analysis indicates that the thickness of an interfacial layer mainly composed of SiO.sub.2 in Example 11A is 3.1 nm.

[0107] In Examples 02B, 21C, 02A, 26C, 16A, 302B and 12B, a film of Ir as metal 4 is formed by a sputtering technique and a film 3a by a pulse laser deposition technique. Of the insulator 2, hafnium nitride and aluminum nitride are formed by a metal organic chemical vapor deposition technique, and other materials by the pulse laser deposition technique. In Example 09F, the film 3a is made by the metal organic chemical vapor deposition technique. CSBT as the ferroelectric 3 has a thickness of 120 nm and has a Ca composition x where x=0.15. The structure and thickness of a gate laminate are Ir (75 nm)/CSBT (x=0.15, 120 nm)/HfO.sub.2 (5 nm)/Si. In an atmosphere having oxygen mixed with N.sub.2 (the volume ratio of N.sub.2 to O.sub.2 being 1:0.00026, annealing for ferroelectric crystallization is effected at a temperature of 780 degrees C. and for a time period of 30 minutes. FIG. 13 is a result of measurement of I.sub.d−V.sub.g. With a gate voltage that is swept in a range from 0.5-3.3 volts to 0.5+3.3 volts there is observed a memory window: V.sub.w=0.51 volts. In Example 09F, Ir and HfO.sub.2 are formed by the sputtering and pulse laser deposition techniques, respectively.

[0108] Annealing for ferroelectric crystallization may be carried out in an atmosphere having oxygen mixed with an inert gas. In Example 030C, The insulator 2 is of a composite oxide of hafnium and magnesium (Hf—Mg—O), having a makeup molar ratio of HfO.sub.2:MgO=7:3. The structure and thickness of a gate laminate are Ir (75 nm)/CSBT (x=0.2, 135 nm)/Hf—Mg—O (5 nm)/Si. In an atmosphere having oxygen mixed with Ar (the volume ratio of Ar to O.sub.2 being 1:0.001), annealing for ferroelectric crystallization is effected at a temperature of 760 degrees C. and for a time period of 30 minutes. FIG. 14 is a result of measurement of I.sub.d−V.sub.g. With a gate voltage that is swept in a range from −3.3 volts to +3.3 volts there is observed a memory window: V.sub.w=0.44 volts.

[0109] For annealing to crystallize a ferroelectric, investigations have been made in detail of the atmosphere having oxygen gas O.sub.2 mixed with N.sub.2 gas, the temperature and the pressure. First, with Ir used for metal 4 there has been found a relationship, as shown in FIG. 15, of a volume proportion y of N.sub.2 to O.sub.2 with respect to a memory window in an I.sub.d−V.sub.g characteristic measured, of a FeFET made using the volume proportion. The memory window as a variable along the ordinate axis has values with the gate voltage that is swept in the rage of −3.3 volts to +3.3 volts. The abscissa axis has a variable y representing a volume proportion of O.sub.2 to N.sub.2, viz. that y=(volume of O.sub.2 in the mixed gas)/(volume of N.sub.2 in the mixed gas). The marks in FIG. 15 individually represent embodiments of FeFET made. Commonly to all embodiments in FIG. 15, The structure and thickness of a gate laminate are Ir (75 nm)/CSBT (x=0.2, 135 nm)/HfO.sub.2 (4 nm)/Si, and the temperature and the time period of annealing to crystallize the ferroelectric are 780 degrees C. and 30 minutes, respectively. Ir and is formed by the sputtering technique, and CSBT and HfO.sub.2 are formed by the pulse laser deposition technique. After the annealing vessel is once evacuated to a vacuum, the gases are added at a selected proportion of mixture for ferroelectric crystallization annealing. Embodiments indicated by marks (.box-tangle-solidup.) in FIG. 15 are the case that annealing is effected in the presence of a flow of nitrogen and oxygen gases. More specifically, the flows of N.sub.2 and O.sub.2 are 1000 and 1000y, respectively. Embodiments of marks (.square-solid.) are the case that annealing is effected in the absence of the flow of nitrogen and oxygen gases. It has been found that favorable conditions to obtain good window are represented by a volume proportion of the gases, regardless of the presence or absence of the gases flowing. With Ir selected for metal 4, a preferred volume proportion of oxygen is not less than 0.0002 and not more than 0.02, achieving a memory window of not less than 0.4 volts.

[0110] In other embodiments, too, in which an FeFET is made of Ca composition X, a good memory window is achieved, regardless of presence or absence of gases flowing. In Example 24A, x=0.25, and the gate laminate is of Ir (75 nm)/CSBT (x=0.25, 135)/HfO.sub.2 (4 nm)/Si. Annealing for ferroelectric crystallization is performed under conditions of without gases flowing, y=0.01, 780 degrees C. and 30 minutes, yielding a memory window of 0.51 volts with the gate voltage that is swept in a rage from −3.3 volts to +3.3 volts. In Example 24B, x=0.25, and the gate laminate is of Ir (75 nm)/CSBT (x=0.25, 135)/HfO.sub.2 (4 nm)/Si. Annealing for ferroelectric crystallization is performed under conditions of in the presence of gases flowing, y=0.01, 780 degrees C. and 30 minutes, yielding a memory window of 0.51 volts with the gate voltage that is swept in a rage from −3.3 volts to +3.3 volts. In Example 24B, x=0.25, and the gate laminate is of Ir (75 nm)/CSBT (x=0.25, 135)/HfO.sub.2 (4 nm)/Si Annealing for ferroelectric crystallization is performed under conditions of in the presence of gases flowing, y=0.01, 780 degrees C. and 30 minutes, yielding a memory window of 0.48 volts with the gate voltage that is swept in a rage from −3.3 volts to +3.3 volts.

[0111] FIG. 16 is a graph illustrating a relationship between an annealing temperature in the process step of annealing for ferroelectric crystallization and a memory window in I.sub.d−V.sub.g characteristic of a FeFET made. The memory window as a variable along the ordinate axis has values with the gate voltage that is swept in the rage of −3.3 volts to +3.3 volts. The time period for annealing is 30 minutes. The marks in FIG. 16 individually represent embodiments of FeFET made. Embodiments indicated by marks (.box-tangle-solidup.) in FIG. 16 are the case that annealing is effected in the presence of a flow of nitrogen and oxygen gases. More specifically, the flows of N.sub.2 and O.sub.2 are 1000 and 1, respectively. Embodiments of marks (.square-solid.) are the case that annealing is effected in the absence of the flow of nitrogen and oxygen gases. In the embodiments marked with (.box-tangle-solidup.), the structure and thickness of a gate laminate are of Ir (75 nm)/CSBT (x=0.2, 135 nm)/HfO.sub.2 (5 nm)/Si. The structure and thickness of a gate laminate in the embodiments marked with (.square-solid.) are of Ir (75 nm)/CSBT (x=0.2, 135)/HfO.sub.2 (4 nm)/Si. The preferred temperature conditioned for ferroelectric crystallization annealing is not less than 730 degrees C. and not more than 800 degrees C., yielding memory window of not less than 0.4 volts.

[0112] Examples using embodiments of metal 4 other than Ir are shown in Table 4. In Examples 22A, 22B, 22C, 19E, 19B and 19C, Pt is used for metal 4. In those except Example 19, the memory window is not less than 0.40 volts. The volume proportion of oxygen gas to nitrogen gas varies from each other of the six Examples. Annealing at a temperature of 700 to 800 degrees C. in pure nitrogen not containing oxygen is found to cause Pt to come off or be detached. Note is taken of Examples in which oxygen is less contained, that is, y is small. In Example 19E where y=0.0003, I.sub.d−V.sub.g characteristic is obtainable, but there is much damage in Pt. In Examples of x=0.0001 tried, a keen detachment of Pt makes it impossible to measure I.sub.d−V.sub.g. In Example 22C where y=0.0007 which has practically no problem, an inspection with a FeSEM (field emission scanning electron microscope) indicates that Pt tends to break off. With Ir, annealing at 700 to 800 degrees C. in pure nitrogen produces no such detachment or breakage. Note then Examples 14A and 14B in which metal 4 is an alloy of Ir and Pt alloyed at 1:1 in weight and formed by the sputtering technique. In Example 14B of y=0.0004, no detachment of the metal is observed, but in Example A, a little breakage of the metal is seen. In Example 17C in which the metal is Ru, no breakage is observed of Ru that is annealed under y=0.0005.

[0113] In the Examples hereinbefore disclosed, annealing for ferroelectric crystallization is effected under one atmospheric pressure (1 atm). Annealing for ferroelectric crystallization is also effected in an environment of a reduced pressure, that is, a pressure lower than 1 atm. Their results are put together in FIG. 17 and Table 2 and 3. Adjacent to the marks in the Figure are denoted the names of the Examples in which the annealing conditions in detail can be confirmed in Tables 2 and 3. In Examples 12G, 12H, 12I, 21B and 16F, annealing is carried out in a mixed gas having oxygen mixed with nitrogen at a volume proportion of y=0.001. The pressure under which annealing is effected can be read out from FIG. 17 and Table 2. As seen from FIG. 17 and Table 2, the pressure condition of not less than 1 atm and not more than 0.001 MPa is preferred to achieve a memory window of not less than 0.4 volt.

[0114] After iterated investigations, it has been found that in annealing for ferroelectric crystallization it is also effective to use oxygen alone as the gas while reducing its pressure. As disclosed in FIG. 17 and Examples 12L and 12k noted in Table 3, note that if the pressure of oxygen alone as the gas introduced is not less than 10.sup.−5 MPa (namely 10 Pa) and not more than 10.sup.−4 MPa (namely 100 Pa), that is preferred to yield a memory window of 0.4 volts. Brining about such an environment of reduced pressure is deemed important in order to reduce the extent in which to form an interfacial layer mainly composed of SiO.sub.2 and to furnish necessary oxygen for annealing of a ferroelectric as an oxide, thereby constituting a favorable annealing condition.

[0115] FIG. 18 is a graph illustrating a relationship between a thickness of HfO.sub.2 used for the insulator 2 and a memory window. The marks in Figure individually represent embodiments of FeFET made. Embodiments of marks (.square-solid.) are the case that annealing is effected in the absence of a gaseous flow. Embodiments indicated by marks (.box-tangle-solidup.) in FIG. 15 are the case that annealing is effected in the presence of the gaseous flow. The structure and thickness of a gate laminate in the embodiments marked with (.square-solid.) are of Ir (75 nm)/CSBT (x=0.2, 135)/HfO.sub.2 (4 nm)/Si. The volume proportion of oxygen gas y=0.0001. FIG. 18 shows that the film of HfO.sub.2 (4 nm) most preferably has a thickness of not less than 2 nm and not more than 6 nm.

[0116] For adjusting the I.sub.d−V.sub.g characteristic for all the Fe FETs of the present invention described above, two additional annealing processes have been found out, each one of which is performed after all of process steps described above have been ended. The first process is to anneal in oxygen gas under a temperature condition lower than that in annealing for ferroelectric crystallization. The second process is to anneal in a gas containing hydrogen. The two characteristic adjustment annealing processes may be used in combination.

[0117] In the first process, annealing is effected at a temperature of not less than 500 degrees C. and not more than 700 degrees C. for a time period of not less than 10 minutes and not more than 60 minutes. FIG. 19 discloses the I.sub.d−V.sub.g characteristics of one FeFET on the chip in Example 02B before and after the characteristic adjustment annealing. The broken and solid curves represent them before and after the characteristic adjustment. It is seen that with respect to a change in the gate voltage the drain current evidently changes in a region of the gate voltage from to 1 volt, more sharply after the characteristic adjustment annealing than before the characteristic adjustment annealing. The characteristic is improved because of a larger change in current deemed in general better for a narrow change in voltage. Quantitatively, evaluation is made using an SS (sub-threshold swing) value. The SS value is defined as a gate voltage needed to change the drain current by one order of magnitude in a region of voltage lower than the threshold value, and it is better that the SS value is small. The SS value is found from the gradient of a curve at I.sub.d=10.sup.−10 A/micro-m. An average value of the SS value obtained from the hysteresis curves right and left is here adopted. Also, the memory window is evaluated at I.sub.d=10.sup.−8 A/micro-m. FIG. 19 (20) discloses the rate of change of the characteristic subsequent to annealing with respect to the temperature in the characteristic adjustment annealing. Marked with ◯ are the rate of change of the memory window, and marked with .square-solid. are the rate of change of the S value. Here, the rate of change is ([the physical quantity subsequent to annealing]−[the physical quantity prior to annealing])/[the physical quantity prior to annealing] and represented in percent (%). It is not good that the rate of the window subsequent to annealing decreases and it is good that the SS value decreases. As shown in FIG. 20, the rate of change of the memory window is small in a range of 500 to 700 degrees C. while the SS value diminishes largely as the temperature is risen. A decrease is seen in the SS value to the extent of 10% in the range of 500 to 700 degrees C. Since rise in temperature to an excess facilitates growth of an interfacial layer mainly composed of SiO.sub.2 and decreases the memory window, resulting in a decrease in the memory window, the upper limit of annealing temperature in the first process is determined. Annealing in oxygen is deemed to recover a defect in the interface between the interfacial layer and Si

[0118] The second process makes use of a mixed gas of hydrogen and nitrogen, containing 3 to 5% of hydrogen. The annealing temperature is preferably not less than 350 degrees C. and not more than 450 degrees C. The annealing time period is preferably not less than 3 minutes and not more than 30 minutes. A clear effect of the second process can be seen from FIGS. 21 and 22. As regards FIG. 21 and Example 21, annealing is effected at a temperature of 40 degrees C. for a time period of 30 minutes. It is seen that “after annealing” (solid curve) is more sharply changed clearly with respect to a change in the gate voltage than “before annealing” (broken curve). FIG. 22 shows results of the second process of annealing a FeFET at a temperature of 400 degrees C. for a time period of 5 minutes, the FeFET being on the chip in Example 23C. As with FIG. 21, the effect of improvement is observed. A hydrogen atom coming into a dangling bond between Si and an interfacial layer 5 mainly composed of SiO.sub.2 is deemed to decrease the state density in the interface, causing the effect of hydrogen annealing to be revealed. Inasmuch as a ferroelectric that is an oxide is decomposed at a higher temperature and for a longer period of time, the temperature and period of time are preferably as mentioned above.

[0119] A pulse rewrite withstand property and a data retention capability are disclosed if the writing voltage has its absolute value of 3.3 volts. Use is made of a FeFET in Example 02B. An alternating pulse having a cycle of a negatively poled pulse having a height of −3.3 volts and a width of 10 microseconds followed by a positively poled pulse having a height of +3.3 volts and a width of 10 microseconds is repetitively applied, constituting rewriting pulses. Upon applying a given cumulative number of alternating pulses, the I.sub.d−V.sub.g characteristic is measured to examine a rewriting tolerance. The gate voltage is swept in reciprocation between −3.3 and +3.3 volts. While the gate voltage is being swept, V.sub.a=0.1 volt and V.sub.s=V.sub.sub=0 volt. As explained in FIG. 6 where I.sub.d=10.sup.−8 A/microsecond is imparted, two gate voltages (threshold voltages) are taken. Thereafter, alternating pulses are applied again. After a given cumulative number is reached, the I.sub.d−V.sub.g characteristic is again measured to examine a rewriting tolerance. This is repeated to acquire a graph shown in FIG. 23. Marked with .Math. are values of threshold voltage obtained when the voltage is risen from −3.3 volts to +3.3 volts, and marked with .box-tangle-solidup. are values of threshold voltage obtained when the voltage is sunk from −3.3 volts to +3.3 volts.sub.o From FIG. 23, it is seen that this embodiment has a rewriting tolerance or rewrite withstand capability of 10.sup.9 times or more. According to the techniques described in pant documents 1 and non-p references 4 and 5, the prior art has a rewrite withstand capability of 10.sup.8 times or more. FIG. 23 shows that FeFETs of the invention have values of the rewriting tolerance which are much not less than the equivalent of the prior art.

[0120] As regards the data retention property, a state of data retention is entered upon applying a single negatively poled pulse having a height of −3.3 volts and a width of 0.1 second, and while the data is retained, V.sub.g=V.sub.d=V.sub.s=V.sub.b=0 volt. At a point of time of each mark .Math., a readout operation is performed. While the data is being read out, let it be held that V.sub.d=0.1 volt and V.sub.s=V.sub.sub=0 volts, and V.sub.g is swept from 1.0 volt to 0 volt to obtain an I.sub.d−V.sub.g characteristic. V.sub.g applied to yield I.sub.d=10.sup.−8 A/micro-m represents a threshold value which is plotted in FIG. 24. After the data is retained for a given time interval, a readout operation is performed. By repeating this, results at marks .Math. in the Figure are obtained until 10.sup.5 seconds are lapsed after the pulse is written. A state of data retention is entered upon applying a single positively poled pulse having a height of −3.3 volts and a width of 0.1 second Results of the same readout operations are represented at marks .Math. in the Figure, showing a good data retention property. After 10.sup.5 seconds are lapsed, it is found that the threshold voltage following a negatively poled pulse is higher by about 0.31 than the threshold voltage following a positively poled pulse. The mark .Math. at after 10.sup.4 seconds and the marks .Math. at after 10.sup.5 seconds are connected by a straight line (broken line) and extrapolated up to 10 years. Likewise, the mark .box-tangle-solidup. at after 10.sup.4 seconds and the marks .box-tangle-solidup. at after 10.sup.5 seconds are connected by a straight line (broken line) and extrapolated up to 10 years. This extrapolating operation indicates that the difference in threshold voltage after 10 years remains to be about 0.18 volt, showing that two storage states are sufficiently distinguishable from each other. It thus follows that a data retention property equivalent to the data retention property described in patent documents 1 to 3 and non-p references 1 to 9 is met by the present invention. Note that the end of a data retention time period refers to a point of time at which two states are no longer distinguishable from each other. It is herein defined as a time at which the difference between the two threshold voltages reaches 0.05 volt. Note further that the data retention property can also be rated by a method whereby in readout the drain current is measured with the gate voltage fixed. In this case, that the ratio of on current to off current is 3 corresponds virtually to that the difference in threshold voltage is 0.05 volt. Thus, the end of a data retention time period is defined in a method of measuring a drain current by a time at which the ratio of on current to off current reaches 3. According to this definition, the life of data retention of embodiments of the present invention is enough in excess of 10 years. The present invention thus provides a FeFET capable of writing data with a writing voltage whose absolute value is not more than 3.3 volts, without impairing either of two properties which in combination are had by a FeFET which has been developed, the two properties being 1) a data retention property of not less than 10.sup.5 seconds and 2) a data rewrite withstand capability of 10.sup.8 times.

[0121] A Fe FET according to the present invention provides a good device property by a writing voltage even if its absolute value is in excess of 3.3 volts. FIGS. 25 and 26 show results of a data rewriting tolerance test. FIG. 25 is a graph having results from Example 27E. The gate laminate in Example 27E has a structure and thickness such as Ir (75 nm)/CSBT (x=0.2, 135)/HfO.sub.2 (5 nm)/Si Annealing for ferroelectric crystallization is effected in a mixed gas (in the presence of a gas flow under 1 atm) having oxygen mixed with nitrogen at a volume proportion of y=0.001, at a temperature of 800 degrees C. and for a time period of 30 minutes. An alternating pulse constituted in one cycle of a negatively poled pulse having a height of −4.5 volts and a width of 10 microseconds followed by a positively poled pulse having a height of +4.5 volts and a width of 10 microseconds is repetitively applied forming alternating pulses for rewriting. While rewriting alternating pulses are being applied, it is held that V.sub.d=V.sub.s=V.sub.sub=0 volt. After a given cumulative number of alternating pulses are applied, a readout operation is performed. In the readout operation, first after writing with a negatively poled pulse of −4.5 volts high and 10 microseconds wide, the gate voltage is swept in a narrow range such that a threshold voltage can be measured. In this case, the gate voltage is swept from 0.9 volt to 0.1 volt. While the gate voltage is being swept, I.sub.d is measured with that V.sub.d=0.1 volt and V.sub.s=V.sub.b=0 volt. The gate voltage applied to yield I.sub.d=10.sup.−8 A/micro-m becomes a threshold voltage after the negatively poled pulse is applied. Next, after writing with a positively poled pulse of +4.5 volts high and 10 microseconds wide, the gate voltage is likewise swept from 0.9 volt to 0.1 volt to measure I.sub.d under the conditions of V.sub.d=0.1 volt and V.sub.s=V.sub.sub=0 volt. The gate voltage applied to yield I.sub.d=10.sup.−8 A/micro-m becomes a threshold voltage after the positively poled pulse is applied. When this readout operation is ended, alternating pulses are applied again. When a given cumulative number is reached, the readout operation is again performed. This is repeated. In this ways is yielded the graph of FIG. 25. Results from FIG. 25 demonstrate that the present embodiment has a rewrite withstand capability of not less than 10.sup.8 times. It is known that A NAND flash memory made of a transistor having a floating gate has a rewrite withstand capability of; at most, not less than 10.sup.5 times. In comparison, it is a markedly better rewrite withstand capability.

[0122] FIG. 26 represents results from Example 12H. The gate laminate in Example 12H has a structure and thickness such as Ir (75 nm)/CSBT (x=0.2, 135)/HfO.sub.2 (5 nm)/Si. Annealing for ferroelectric crystallization is effected in a mixed gas (in the presence of a gas flow) having oxygen mixed with nitrogen at a volume proportion of y=0.001, at a temperature of 750 degrees C. and for a time period of 30 minutes. The graph in FIG. 25 is obtained from measurement using the same process as those mentioned above. Only a portion that differs numerically is mentioned. An alternating pulse, for a cycle of 20 microseconds, constituted of a negatively poled pulse having a height of −4.5 volts and a width of 10 microseconds followed by a positively poled pulse having a height of +4.5 volts and a width of 10 microseconds is used. After a given cumulative number of the alternating pulses, a readout operation is performed. In reading out, the gate voltage is swept from 0.6 to −0.4 volt. FIG. 26 graphically shows a rewrite withstand capability not less than 10.sup.9 times.

[0123] FIGS. 27 and 28 graphically show results of the data retention property. FIG. 27 represents results from Example 27F. The gate laminate in Example 27F has a structure and a thickness such as Ir (75 nm)/CSBT (x=0.2, 135)/HfO.sub.2 (5 nm)/Si. Annealing for ferroelectric crystallization is effected in a mixed gas (in the presence of a gas flow under 1 atm) having oxygen mixed with nitrogen at a volume proportion of y=0.001, at a temperature of 750 degrees C. and for a time period of 30 minutes. After a single negatively poled pulse having a height of −4.5 volts and a width of 10 microseconds is applied, a state of data retention is entered. While the data is retained, it is held that V.sub.d=V.sub.s=V.sub.sub=0 volt. At a point of time represented by the mark , an readout operation is performed. While the data is being read out, it is held that V.sub.d=0.1 volt and V.sub.s=V.sub.sub=0 volt, and V.sub.g is swept from 0.3 volt to −0.4 volt to obtain an I.sub.d−V.sub.g characteristic. V.sub.g applied to yield I.sub.d=10.sup.−8 A/micro-m represents a threshold value which is plotted in the graph of FIG. 27. After a single positively pulse having a height of 4.5 volts and a width of microseconds is applied. A state of data retention is entered. Results of the data readout operation that is likewise performed are shown marked with ◯. After a lapse of 10.sup.5 seconds, the threshold voltage following the negatively poled pulse is found to be larger by about 0.5 volt higher than the threshold voltage following the positively poled pulse. showing a good data retention property. FIG. 28 shows results from Example 12H. Thickness of a gate laminate and condition of annealing for ferroelectric crystallization of the Example 12H are as mentioned above. The negatively poled pulse for writing has a height of −4.5 volts and a width of 10 microseconds. The positively poled pulse for writing has a height of +4.5 volts and a width of 10 microseconds. While data is being retained, it is held that V.sub.g=V.sub.d=V.sub.s=V.sub.sub=0 volt. While the data is being read out, it is held that V.sub.d=0.1 volt and V.sub.s=V.sub.sub=0 volts, and V.sub.g is swept from 0.6 volt to −0.4 volt to obtain an I.sub.d−V.sub.g characteristic. V.sub.g applied to yield I.sub.d=10.sup.−8 A/micro-m represents a threshold value which is plotted in the graph of FIG. 28. After a lapse of 10.sup.5 seconds, the threshold voltage following the negatively poled pulse is found to be larger by about 0.25 volt higher than the threshold voltage following the positively poled pulse. showing a good data retention property. As shown by the embodiments in Example 12H, the FeFET provides both excellent data retention property and excellent data rewrite withstand capability at the same time.

[0124] While the method of making a FeFET according to the present invention can be implemented in various forms that are not limitative, mention is made of two Examples of them.

Example 302B

1. Preparation of Si Substrate and Surface Treatment

[0125] A source and a drain region are formed and a Si substrate of p-type covered with a SiO.sub.2 surface layer having a thickness of 35 nm is prepared. The substrate is immersed in buffered hydrofluoric acid to remove the protective SiO.sub.2 film on its surface, a state as shown in FIG. 29(a).

2. Forming an Insulator 2

[0126] A pulse laser deposition technique is used to form an insulator 2. Its target is HfO.sub.2 and the laser is KrF excimer laser, having a wavelength of 248 nm, a pulse projection number of 10 per second and a laser energy of 250 mJ. The substrate is held at a temperature of 220 degrees C., and N.sub.2 is introduced at a rate of flow of 4 sccm and under a pressure of 15 Pa and for a time period of 8 minutes and 57 seconds. The insulator 2 is formed in the form of a film of HfO.sub.2. Note that the rate of forming the film varying with the state of equipment and target is seized separately by a monitor. The film forming time is adjusted to give a selected film thickness.

3. Forming a Film 3a

[0127] A pulse laser deposition technique is used to form a film 3a. The target is Ca—Sr—Bi—Ta—O. Ca and Sr contained in the target are of molar a ratio, Ca: Sr=0.2:0.8. Note that it is confirmed by Rutherford backscattering spectrometry that the molar ratio is held in a FeFET completed through annealing for ferroelectric crystallization. The laser is KrF excimer laser, having a wavelength of 246 nm, a pulse projection number of 50 per second and a laser energy of 250 mJ. The substrate is held at a temperature of 415 degrees C., and O.sub.2 is introduced at a rate of flow of 3.1 sccm and under a pressure of 11 Pa and for a time period of 17 minutes and 47 seconds to form a film 3a. The film 3a formed is of Ca—Sr—Bi—Ta—O. Note that the rate of forming the film varying with the state of equipment and target is seized separately by a monitor. The film forming time is adjusted to give a selected film thickness.

4. Forming a Metal 4

[0128] An Rf magnetron scattering technique is used to form a metal 4. The target is metal Ir and the substrate is not heated. Argon is introduced at a rate of flow of 1.4 sccm and under a pressure of 0.15 Pa. Rf power is 40 W and held for 22 minutes and 30 seconds to form a film of Ir having a thickness of 75 nm, as the metal. Past process steps 2, 3 and 4, a state as shown in FIG. 29(b) is had.

5. Forming a Gate Metal Configuration

(1) Photolithographic Process Step

[0129] A photoresist of the gate configuration is left by an ordinary photographic technique. FeFETs of 8 kinds have a gate length of 10 micrometers and a gate width of 200 to 10 micrometers

(2) Etching of Metal 4

[0130] An ion milling technique is used to remove portions of Ir metal which are not covered with the photoresist.

(3) Removal of the Photoresist

[0131] The Example specimen is immersed in acetone to remove the photoresist, the specimen being thereafter cleansed in ultrapure water, bringing about a state as shown in FIG. 29c).

6. Annealing for Ferroelectric Crystallization

[0132] An infrared gold-image furnace is used to perform annealing for ferroelectric crystallization. The furnace vessel having the Example specimen set is evacuated to vacuum. Then, after a gas containing oxygen and nitrogen is introduced while a volume proportion thereof is maintained at y=0.001 into the furnace vessel, the gas introduction is halted. The Example specimen has a temperature risen from room temperature to 750 degrees C. for a time period of 10 minutes and is annealed at the temperature of 750 degrees C. under a pressure of 1 atm in the absence of flow for a time period of 30 minutes.

7. Forming a Hole for contact of Source and Drain

(1) Photolithographic Process Step

[0133] An ordinary photolithographic technique is used to remove the resist at a portion of the hole for contact of the source and drain.

(2) Etching Process Step

[0134] An ion milling technique is used to remove portions of the ferroelectric and insulator 2.

(3) Removal of the Photoresist

[0135] The Example specimen is immersed in acetone to remove the photoresist.

[0136] Past this process step, a state as shown in FIG. 29(d) is reached, making it possible to measure an I.sub.d−V.sub.g characteristic and others. The process step of annealing for ferroelectric crystallization is effected intervening between the process steps of FIG. 29(c) and 2(d), transforming the film 3a in FIG. 29(c) into a ferroelectric 3. Note, further, that the interfacial layer 5 mainly composed of SiO.sub.2 is omitted from illustration.

[0137] The two sorts of annealing may be performed at need and after process steps 6 and 7.

Example 12B

[0138] (1) Preparation of Si Substrate 1 and Surface Treatment, (3) Forming a Film 3a, (4) Forming a Metal 4, (5) Forming a Gate Metal Configuration and (7) Forming a Hole for contact of Source and Drain are the same as in Example 302B. However, in (3) Forming a Film 3a, the time period for film forming is varied in view of a change in rate of film forming. Also, (6) Annealing for Ferroelectric Crystallization is the same as in Example 302B, except that the annealing temperature is changed to 780 degrees C.

[0139] In (2) Forming an Insulator 2, this Example has hafnium nitride (Hf—N) formed having a thickness of 2 nm and thereafter HfO.sub.2 formed having a thickness of 4 nm. Forming of HfO.sub.2 is the same as in Example 302B. However, the time period for film forming is varied in consideration of a change in rate of film forming.

[0140] Mention is here made of forming a film of hafnium nitride (Hf—N) in detail A film of hafnium nitride (Hf—N) is formed using a metal organic chemical vapor deposition technique of the type in which a raw material liquid solution is prepared having a complex compound containing Hf and dissolved in a solvent, the raw material liquid solution being dispersed into a carrier gas to form a raw material gaseous medium in a state of gas and liquid two phases; the raw material gaseous medium while in the state of gas and liquid two phases is introduced into a vaporizing chamber to form a vapor thereof and the vapor is introduced into a film forming chamber.

[0141] The complex compound containing Hf is preferably Hf [N (C.sub.2 H.sub.5) (CH.sub.3)].sub.4, tetrakis-dimethyl amino hafnium, which is abbreviated as TEMAHF. It can be confirmed that a complex compound expressed by chemical formula: Hf (N (C.sub.2 H.sub.5).sub.2].sub.4, tetrakis diethylamido hafnium abbreviated as TDEAHF can also be used to form a film of Hf—N. For the solvent, use is made of ethyl cyclohexane (ECH). The carrier gas uses nitrogen gas, but may be argon gas. Ammonia (NH.sub.3) gas is also introduced in to the growth chamber. It is important that a preferred rate of flow of NH.sub.3 gas be selected. Further, It is necessary that the temperature of a susceptor holding the substrate (i.e. an Example specimen being made) be suitably selected. In the raw material liquid solution having TEMAHF dissolved in ECT, the concentration of TEMAHF in ECT is preferably 0.1 mol to 0.2 mol per liter. In the raw material liquid solution, to, having TDEAHF dissolved in ETC, the concentration of TDEAHF in ECT is preferably 0.1 mol to 0.2 mol per liter. The rate of liquid flow of the raw material liquid solution is preferably 0.1 to ccm to 0.3 ccm. The pressure of the growth chamber is 200 Pa to 700 Pa. While the rate of NH.sub.3 gas is not less than 5 sccm and not more than 30 sccm, and the susceptor temperature is not less than 260 degrees C. and not more than 400 degrees C., it has been found that they are preferable to form a film of hafnium nitride satisfying a stoichiometric mixture ratio of Hf.sub.3N.sub.4. When under the conditions a film of Hf—N having a thickness of 35 nm is formed on the test specimen not of FeFET (but a silicon wafer) and its composition is analyzed by the Rutherford backscattering spectroscopic technique, the ratio in number of atoms of Hf and N, [number of N atoms]/[number of Hf atoms], is found to be =1.36. This shows that the composition of hafnium nitride formed into a film according to the present invention is close to the composition of hafnium nitride (4/3=1.33) known in chemical formula of Hf.sub.3N.sub.4.

EXPLANATION OF REFERENCE CHARACTERS

[0142] 1 a semiconductor substrate [0143] 2 an insulator [0144] 3a a film a [0145] 3 a ferroelectric [0146] 4 a metal [0147] 5 an interfacial layer (II) mainly composed of SiO.sub.2 [0148] 6 a source region [0149] 7 a drain region

TABLE-US-00001 TABLE 1 Making Conditions of FeFET with a Gate Laminate of Ir (75 nm)/CSBT (x = 0.2)/HfO.sub.2 (5 nm)/Si, and Memory Window therein Making Conditions of Hf—N Annealing for Ferroelectric NH.sub.3 CSBT Crystallization Flow Susceptor HfO.sub.2 (x = 1) Gaseous Oxygen Example Rate temperature Thickness Thickness Thickness Flow Vol. Temp. Memory Name (sccm) (° C.) (nm) (nm) (nm) ◯orX Prop. y (° C.) Window 11A 9 260 1 3 135 X 0.001 780 0.54 11B 9 260 1 3 135 X 0.001 780 0.47 11C 9 260 1.5 3 135 X 0.001 780 0.51 11D 9 260 1.5 4 135 X 0.0005 780 0.42 12A 9 260 2 3 135 X 0.001 780 0.5 12B 9 260 2 4 135 X 0.001 780 0.57 04A 20 260 1 3 135 X 0.001 780 0.53 04B 20 260 1 4 135 X 0.0005 780 0.54 04C 20 260 1.5 3 135 X 0.001 780 0.53 05A 20 260 2 4 135 X 0.001 780 0.56 23A 20 400 1 4 135 X 0.001 780 0.47 24A 20 400 1.5 4 135 X 0.001 780 0.43

TABLE-US-00002 TABLE 2 Conditions of Examples in which Annealing is effected in a Mixed Gas of Nitrogen and Oxygen under a Reduced Pressure, and Memory Window therein F Layer Oxygen Vol. I Layer CSBT M Layer Temp. in Gas Flow Prop. To Pressure HfO.sub.2 (x = 2) Ir Annealing in Nitrogen in Example Thickness Thickness Thickness T.sub.an Annealing in Annealing Memory Name (nm) (nm) (nm) (° C.) ◯orX Annealing (MPa) Window 12G 5 135 75 750 ◯ 0.001 0.04 0.44 12H 5 135 75 750 ◯ 0.001 0.01 0.45 12I 5 135 75 750 ◯ 0.001 0.001 0.40 21B 4 135 75 780 ◯ 0.001 0.001 0.51 16F 4 135 75 780 X 0.001 0.0475 0.54

TABLE-US-00003 TABLE 3 Conditions of and Memory Window in Examples In which Annealing is effected under a Reduced Pressure F Layer Oxygen Vol. I Layer CSBT M Layer Temp. in Gas Flow Prop. To Pressure HfO.sub.2 (x = 2) Ir Annealing in Nitrogen in Example Thickness Thickness Thickness T.sub.an Annealing in Annealing Memory Name (nm) (nm) (nm) (° C.) ◯orX Annealing (MPa) Window 12K 5 135 75 750 ◯ 12L 5 135 75 750 ◯

TABLE-US-00004 TABLE 4 Examples using Pt, IrPt and Ru for Metal Annealing for Ferroelectric Insulator Ferroelectric Metal Crystallization HfO2 CSBT Technique Gaseous Oxygen Example Thickness X = 0.2 Material for Thickness Flow Vol. Temp. Memory Name (nm) (nm) Type Deposition (nm) ◯orX Prop. Y (° C.) Window 22A 4 135 Pt Electron 150 ◯ 0.003 780 0.46 Beam Depo. 22B 4 135 Pt Electron 150 ◯ 0.006 780 0.40 Beam Depo/ 22C 4 135 Pt Electron 150 ◯ 0.0007 780 0.42 Beam Depo. 19A 5 135 Pt Electron 150 ◯ 0.0003 780 0.30 Beam Depo. 19B 5 135 Pt Electron 150 ◯ 0.001 780 0.49 Beam Depo. 19C 5 135 Pt Electron 150 ◯ 0.01 780 0.40 Beam Depo. 14A 4 146 IrPt Spattering 75 ◯ 0.0001 780 0.56 alloy 14B 4 146 IrPt Spattering 75 ◯ 0.0004 780 0.49 alloy 17C 4 135 Ru Spattering 70 ◯ 0.0005 740 0.40