ANALOG FRONT-END CIRCUIT

Abstract

One embodiment provides an analog front-end circuit. When a chopping signal has a first logical value, a non-inverting instrumentation preamplifier subtracts a second input voltage from a first input voltage and generates a first output voltage by amplifying a subtraction voltage while outputting the second input voltage as a second output voltage. When the chopping signal has a second logical value, the non-inverting instrumentation preamplifier subtracts the first input voltage from the second input voltage and generates the first output voltage by amplifying and then inverting the polarity of a subtraction voltage while outputting the second input voltage as the second output voltage.

Claims

1. An analog front-end circuit including: an instrumentation preamplifier which receives a first input voltage and a second input voltage and outputs a first output voltage and a second output voltage; a switch unit which outputs the first output voltage and the second output voltage of the instrumentation preamplifier by alternately switching them according to a logical transition of a chopping signal; an AD converter which converts an analog difference voltage between the first output voltage and the second output voltage that are output from the switch unit into a digital signal; and a data calculator which performs an averaging processing on two successive data that are output from the AD converter every time the logic transition of the chopping signal occurs, wherein, when the chopping signal has a first logical value, the instrumentation preamplifier performs calculations
VOUTP=VINP+G×(VINP−VINN)
VOUTN=VINN, and when the chopping signal has a second logical value, the instrumentation preamplifier performs calculations
VOUTP=VINP+G×(VINN−VINP)×(−1)
VOUTN=VINN, where VINP is the first input voltage, VINN is the second input voltage, VOUTP is the first output voltage, VOUTN is the second output voltage, and G is a gain of the instrumentation preamplifier.

2. The analog front-end circuit of claim 1, wherein the instrumentation preamplifier includes: a first switch having a second input terminal and a first input terminal which receives the first input voltage; a second switch having a first input terminal and a second input terminal which receives the first input voltage; a first operational amplifier having a non-inverting input terminal to which an output terminal of the first switch is connected and an inverting input terminal to which an output terminal of the second switch is connected; a third switch having a first input terminal to which an output terminal of the first operational amplifier is connected and a second input terminal to which the output terminal of the first operational amplifier is connected via an inversion circuit; a first resistor having one end which is connected to the second input terminal of the first switch and the first input terminal of the second switch and the other end which receives the second input voltage; and a second resistor connected between an output terminal of the third switch and a connecting point of the second input terminal of the first switch and the first input terminal of the second switch, wherein, when the chopping signal has the first logical value, the first input terminal is selected in each of the first switch, the second switch and the third switch, wherein, when the chopping signal has the second logical value, the second input terminal is selected in each of the first switch, the second switch and the third switch, and wherein the first output voltage is output from the output terminal of the third switch, and the first input voltage is output as the second output voltage.

3. The analog front-end circuit of claim 1, wherein the instrumentation preamplifier includes: a first switch having a second input terminal and a first input terminal which receives the first input voltage; a second switch having a first input terminal and a second input terminal which receives the first input voltage; a first operational amplifier having a non-inverting input terminal to which an output terminal of the first switch is connected and an inverting input terminal to which an output terminal of the second switch is connected; a third switch having a first input terminal to which an output terminal of the first operational amplifier is connected and a second input terminal to which the output terminal of the first operational amplifier is connected via a first inversion circuit; a seventh switch having a first input terminal and a second input terminal which receives the second input voltage; an eighth switch having a second input terminal and a first input terminal which receives the second input voltage; a second operational amplifier having an inverting input terminal to which an output terminal of the seventh switch is connected and a non-inverting input terminal to which an output terminal of the eighth switch is connected; a ninth switch having a first input terminal to which an output terminal of the second operational amplifier is connected and a second input terminal to which the output terminal of the second operational amplifier is connected via a second inversion circuit; a first resistor connected between a connecting point of the second input terminal of the first switch and the first input terminal of the second switch and a connecting point of the first input terminal of the seventh switch and the second input terminal of the eighth switch; and a second resistor connected between an output terminal of the third switch and a connecting point of the second input terminal of the first switch and the first input terminal of the second switch, wherein an output terminal of the ninth switch is connected to the first input terminal of the seventh switch and the second input terminal of the eighth switch, wherein, when the chopping signal has the first logical value, the first input terminal is selected in each of the first switch, the second switch, the third switch, the seventh switch, the eighth switch and the ninth switch, wherein, when the chopping signal has the second logical value, the second input terminal is selected in each of the first switch, the second switch, the third switch, the seventh switch, the eighth switch and the ninth switch, and wherein the first output voltage is output from the output terminal of the third switch, and the second output voltage is output from the output terminal of the ninth switch.

4. The analog front-end circuit of claim 1, further including: a sixth switch which is connected between the AD converter and the data calculator, and has a first input terminal to which an output terminal of the AD converter is connected and a second input terminal to which the output terminal of the AD converter is connected via a data inverter, wherein, when the chopping signal has the first logical value, the first input terminal is selected in the sixth switch, wherein, when the chopping signal has the second logical value, the second input terminal is selected in the sixth switch, and wherein the data calculator performs addition processing on data that are received from the sixth switch, as the averaging processing.

5. The analog front-end circuit of claim 1, wherein the data calculator performs subtraction processing on data that are received from the AD converter, as the averaging processing.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0068] FIG. 1 is a circuit diagram of an analog front-end circuit according to a first embodiment.

[0069] FIG. 2 is a circuit diagram of an analog front-end circuit according to a second embodiment

[0070] FIG. 3 is a circuit diagram of an analog front-end circuit of a first comparison example.

[0071] FIG. 4 is a circuit diagram of an analog front-end circuit of a second comparison example.

[0072] FIG. 5A is a table showing input/output states of an instrumentation preamplifier of the analog front-end circuit shown in FIG. 1. FIG. 5B is a table showing input/output states of an instrumentation preamplifier of the analog front-end circuit shown in FIG. 2. FIG. 5C is a table showing input/output states of an instrumentation preamplifier of the analog front-end circuit shown in FIG. 3. FIG. 5D is a table showing input/output states of an instrumentation preamplifier of the analog front-end circuit shown in FIG. 4.

DETAILED DESCRIPTION

Embodiment 1

[0073] FIG. 1 shows an analog front-end circuit 10A according to a first embodiment. The analog front-end circuit 10A is equipped with a non-inverting instrumentation preamplifier 11A which amplifies the difference between input voltages VINP and VINN that are input from a sensor 1 and outputs output voltages VOUTP and VOUTN, switches SW4 and SW5 (switch unit) each of which switches between the output voltages VOUTP and VOUTN, an AD converter 22 (AD converter) for converting the difference between the output voltages VOUTP and VOUTN that are output from the switches SW4 and SW5 into a digital signal, a switch circuit 13 which passes the output data of the AD converter 12 as it is or after inverting its polarity, and a data calculator 14 (data calculator) for calculating average data of two data that are output from the switch circuit 13 successively.

[0074] The non-inverting instrumentation preamplifier 11A is composed of switches SW and SW2 each of which switches between input voltages VINP and VINN, an operational amplifier OP1 for amplifying the difference between the input voltages VINP and VINN that have passed the switches SW1 and SW2, gain-setting resistors R1 and R2, and a switch circuit 11a which has an inversion circuit 11a1 and a switch SW3 and passes an output voltage of the operational amplifier OP1 as it is or after inverting its polarity.

[0075] The switch circuit 13 has a switch SW6 which passes input data as it is or outputs the input data as polarity-inverted by a data inverter 13a.

[0076] A chopping signal CHOP is a signal that “0” and “1” occur repeatedly and alternately at a prescribed cycle. Each of the switches SW1-SW6 selects the input terminals “0” and “1” when the chopping signal CHOP is “0” and “1,” respectively.

[0077] In FIG. 1, symbols Vos1 and Vos3 denote an offset component etc. occurring on the non-inverting input side of the operational amplifier OP1 and an offset component etc. occurring on the data input side of the AD converter 12, respectively.

[0078] In the analog front-end circuit 10A, an output voltage VO.sub.CHOP=0 of the switch circuit 13 when the chopping signal CHOP is “0” is given by

[00008]$\begin{array}{cc}{\mathrm{VO}}_{\mathrm{CHOP}=0}=\left(\mathrm{VINP}-\mathrm{VINN}\right)\times \left(1+\frac{R.Math..Math.2}{R.Math..Math.1}\right)+\mathrm{Vos}.Math..Math.1\times \left(1+\frac{R.Math..Math.2}{R.Math..Math.1}\right)+\mathrm{Vos}.Math..Math.3.& \left(14\right)\end{array}$

[0079] On the other hand, an output voltage VO.sub.CHOP=1 of the switch circuit 13 when the chopping signal CHOP is “1” is given by

[00009]$\begin{array}{cc}{\mathrm{VO}}_{\mathrm{CHOP}=1}=\left\{-\left(\mathrm{VINP}-\mathrm{VINN}\right)\times \left(1+\frac{R.Math..Math.2}{R.Math..Math.1}\right)+\mathrm{Vos}.Math..Math.1\times \left(1+\frac{R.Math..Math.2}{R.Math..Math.1}\right)+\mathrm{Vos}.Math..Math.3\right\}\times \left(-1\right)=\left(\mathrm{VINP}-\mathrm{VINN}\right)\times \left(1+\frac{R.Math..Math.2}{R.Math..Math.1}\right)-\mathrm{Vos}.Math..Math.1\times \left(1+\frac{R.Math..Math.2}{R.Math..Math.1}\right)-\mathrm{Vos}.Math..Math.3.& \left(15\right)\end{array}$

[0080] Thus, an output OUT of the data calculator 14, that is, the average of two successive output voltages VO.sub.CHOP=0 and VO.sub.CHOP=1 of the switch circuit 13, is given by

[00010]$\begin{array}{cc}\mathrm{OUT}=\frac{{\mathrm{VO}}_{\mathrm{CHOP}=0}+{\mathrm{VO}}_{\mathrm{CHOP}=1}}{2}=\left(\mathrm{VINP}-\mathrm{VINN}\right)\times \left(1+2\times \frac{R.Math..Math.2}{R.Math..Math.1}\right).& \left(16\right)\end{array}$

In Equation (16), the offset components etc. Vos1 and Vos3 are eliminated.

[0081] FIG. 5A shows example input voltages VINP and VINN and output voltages VOUTP and VOUTN of the non-inverting instrumentation preamplifier 11A of the analog front-end circuit 10A shown in FIG. 1 in which the input voltages VINP and VINN are 2 V and 1 V, respectively. When the chopping signal CHOP is “0,” the input voltages VINP and VINN pass the switches SW1 and SW2 as they are, respectively, and hence the output voltages VOUTP and VOUTN and the amplification factor GAIN are given by

[00011]$\begin{array}{cc}\mathrm{VOUTP}=\mathrm{VINP}+\frac{R.Math..Math.2}{R.Math..Math.1}\times \left(\mathrm{VINP}-\mathrm{VINN}\right)& \left(17\right)\\ \mathrm{VOUTN}=\mathrm{VINN}& \left(18\right)\\ \mathrm{GAIN}=\frac{\mathrm{VOUTP}-\mathrm{VOUTN}}{\mathrm{VINP}-\mathrm{VINN}}=1+\frac{R.Math..Math.2}{R.Math..Math.1}.& \left(19\right)\end{array}$

[0082] Where the amplification factor GAIN is 10, R2/R1 is calculated to be 9 from Equation (19). Thus, the output voltages VOUTP and VOUTN are calculated as

VOUTP=2+9×1=11(V)

VOUTN=1(V).

[0083] On the other hand, when the chopping signal CHOP is “1”, the output voltages VOUTP and VOUTN are given by

[00012]$\begin{array}{cc}\mathrm{VOUTP}=\mathrm{VINP}+\frac{R.Math..Math.2}{R.Math..Math.1}\times \left(\mathrm{VINN}-\mathrm{VINP}\right)\times \left(-1\right)& \left(20\right)\\ \mathrm{VOUTN}=\mathrm{VINN}.& \left(21\right)\end{array}$

[0084] Thus,

VOUTP=2+9×(−1)×(−1)=11(V)

VOUTN=1(V).

[0085] As described above, in the analog front-end circuit 10A shown in FIG. 1, the output voltages VOUTP and VOUTN do not become negative. That is, even if a single-ended signal in which the input voltage VINN is fixed and the input voltage VINP varies, the output voltages VOUTP and VOUTN are not saturated and their signal ranges are widened to a large extent.

Embodiment 2

[0086] FIG. 2 shows an analog front-end circuit 10B according to a second embodiment. The analog front-end circuit 10B is different from the analog front-end circuit 10A shown in FIG. 1 in a non-inverting instrumentation preamplifier 11B. The non-inverting instrumentation preamplifier 11B is different from the non-inverting instrumentation preamplifier 11A shown in FIG. 1 in being added with, as a voltage follower circuit, an operational amplifier OP2, switches SW7 and SW8, and a switch circuit 11b which has an inversion circuit 11b1 and a switch SW9 and passes an output voltage of the operational amplifier OP2 as it is or after inverting its polarity.

[0087] Each of the switches SW1 and SW2 switches between input voltages for the operational amplifier OP1, and each of the switches SW7 and SW8 switches between input voltages for the operational amplifier OP2.

[0088] Each of the switches SW1-SW6 selects the input terminals “0” and “1” when the chopping signal CHOP is “0” and “1,” respectively. In FIG. 2, symbols Vos1, Vos2, and Vos3 denote an offset component etc. occurring on the non-inverting input side of the operational amplifier OP1, an offset component etc. occurring on the non-inverting input side of the operational amplifier OP2, and an offset component etc. occurring on the input side of the AD converter 12, respectively.

[0089] In the analog front-end circuit 10B, an output voltage VO.sub.CHOP=0 of the switch circuit 13 when the chopping signal CHOP is “0” is given by

[00013]$\begin{array}{cc}{\mathrm{VO}}_{\mathrm{CHOP}=0}=\left(\mathrm{VINP}-\mathrm{VINN}\right)\times \left(1+\frac{R.Math..Math.2}{R.Math..Math.1}\right)+\left(\mathrm{Vos}.Math..Math.1-\mathrm{Vos}.Math..Math.2\right)\times \left(1+\frac{R.Math..Math.2}{R.Math..Math.1}\right)+\mathrm{Vos}.Math..Math.3.& \left(22\right)\end{array}$

[0090] On the other hand, an output voltage VO.sub.CHOP=1 of the switch circuit 13 when the chopping signal CHOP is “1” is given by

[00014]$\begin{array}{cc}{\mathrm{VO}}_{\mathrm{CHOP}=1}=\left\{-\left(\mathrm{VINP}-\mathrm{VINN}\right)\times \left(1+\frac{R.Math..Math.2}{R.Math..Math.1}\right)+\left(\mathrm{Vos}.Math..Math.1-\mathrm{Vos}.Math..Math.2\right)\times \left(1+\frac{R.Math..Math.2}{R.Math..Math.1}\right)+\mathrm{Vos}.Math..Math.3\right\}\times \left(-1\right)=\left(\mathrm{VINP}-\mathrm{VINN}\right)\times \left(1+\frac{R.Math..Math.2}{R.Math..Math.1}\right)-\left(\mathrm{Vos}.Math..Math.1-\mathrm{Vos}.Math..Math.2\right)\times \left(1+\frac{R.Math..Math.2}{R.Math..Math.1}\right)-\mathrm{Vos}.Math..Math.3.& \left(23\right)\end{array}$

[0091] Thus, an output OUT of the data calculator 14, that is, the average of two successive output voltages VO.sub.CHOP=0 and VO.sub.CHOP=1 of the switch circuit 13, is given by

[00015]$\begin{array}{cc}\mathrm{OUT}=\frac{{\mathrm{VO}}_{\mathrm{CHOP}=0}+{\mathrm{VO}}_{\mathrm{CHOP}=1}}{2}=\left(\mathrm{VINP}-\mathrm{VINN}\right)\times \left(1+\frac{R.Math..Math.2}{R.Math..Math.1}\right).& \left(24\right)\end{array}$

In Equation (24), the offset components etc. Vos1, Vos2 and Vos3 are eliminated.

[0092] FIG. 5B shows example input voltages VINP and VINN and output voltages VOUTP and VOUTN of the non-inverting instrumentation preamplifier 11B of the analog front-end circuit 10B shown in FIG. 2. Since the switches SW7 and SW8, the switch circuit 11b, and the operational amplifier OP2 serve as a voltage follower, the input voltages VINP and VINN and the output voltages VOUTP and VOUTN of the non-inverting instrumentation preamplifier 11B are the same as those of the non-inverting instrumentation preamplifier 11B shown in FIG. 1.

[0093] In the analog front-end circuit 10B shown in FIG. 2, since the impedance relating to the output voltage VOUTN is isolated from the impedance relating to the input voltage VINN, a phenomenon can be prevented that the bias voltage of the AD converter 12 is affected by the impedance on its input side.

Other Embodiments

[0094] In the analog front-end circuits 10A and 10B shown in FIGS. 1 and 2, the data calculator 14 performs averaging processing by adding together two successive output data of the switch circuit 13. The switch circuit 13 can be omitted if the data calculator 14 is configured so as to calculate a difference between two successive input data.