DOUBLE LAYER CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

Abstract

Provided is a double layer circuit board and a manufacturing method thereof. The double layer circuit board comprises a substrate, a first circuit layer formed on a first surface of the substrate, a second circuit layer formed on a second surface of the substrate, and at least one connecting pillar formed in and covered by the substrate. Each one of the at least one connecting pillar includes a first end connected to the first circuit layer and a second end connected to the second circuit layer. A terminal area of the second end is greater than a terminal area of the first end. Therefore, the second circuit layer is firmly connected to the first circuit layer through the at least one connecting pillar. A yield rate of the double layer circuit board may be increased.

Claims

1. A double layer circuit board comprising: a first circuit layer including a first circuit; at least one connecting pillar formed on the first circuit, each one of the at least one connecting pillar having a first end connected to the first circuit and a second end opposite to the first end; a substrate formed on the first circuit and the at least one connecting pillar to cover the first circuit and the at least one connecting pillar after the at least one connecting pillar is formed, the substrate comprising a first surface and a second surface opposite to the first surface; a second circuit layer formed on the second surface of the substrate and including a second circuit connected to the second end of the at least one connecting pillar; and wherein a terminal area of the first end of the connecting pillar is a connecting area between the first circuit layer and the connecting pillar, a terminal area of the second end is a connecting area of the connecting pillar between the second circuit layer and the connecting pillar, and the terminal area of the second end is greater than the terminal area of the first end; wherein a surface of the first circuit layer and the first surface of the substrate are in a same plane; wherein a plating layer is formed between the at least one connecting pillar and the substrate; wherein another plating layer is formed between the second circuit and the second surface of the substrate.

2. A manufacturing method of a double layer circuit board comprising steps of: providing a baseboard; wherein a first plating layer is formed on a surface of the baseboard; forming a first photoresist layer on the first plating layer; patterning the first photoresist layer to form a groove of a first circuit pattern in the first photoresist layer; wherein the first plating layer is exposed in the groove of the first circuit pattern; forming a first circuit groove in the groove of the first circuit pattern by plating the first plating layer to fill the groove of the first circuit pattern; forming a second photoresist layer on the surface of the baseboard to cover the first circuit and the first photoresist layer; patterning the second photoresist layer to form at least one via to expose a top surface of the first circuit; forming a second plating layer on a surface of the second photoresist layer and in the at least one via; forming at least one connecting pillar that fills the at least one via by plating the second plating layer in the at least one via; wherein each one of the at least one connecting pillar comprises a first end and a second end, the first end is opposite to the second end, and the first end is connected to the first circuit; forming a third photoresist layer on the at least one connecting pillar and the plated second plating layer; patterning the third photoresist layer to cover the at least one second end of the at least one connecting pillar; removing a portion of the second plating layer that is uncovered by the third photoresist layer; removing the first photoresist layer, the second photoresist layer, and the third photoresist layer, and maintaining the first circuit and the at least one connecting pillar; forming a substrate on the baseboard to cover the first circuit and the at least one connecting pillar; wherein the substrate comprises a first surface and a second surface, the first surface is opposite to the second surface, and the first surface faces to the baseboard; drilling the second surface of the substrate by laser to expose the at least one second end of the at least one connecting pillar out of the second surface of the substrate; forming a third plating layer on the second surface of the substrate; wherein the third plating layer is electronically connected to the at least one connecting pillar; forming a fourth photoresist layer on a surface of the third plating layer; patterning the fourth photoresist layer to form a groove of a second circuit pattern in the fourth photoresist layer; wherein the third plating layer is exposed in the groove of the second circuit pattern; forming a second circuit in the groove of the second circuit pattern on the third plating layer by plating the third plating layer; removing the fourth photoresist layer to expose the third plating layer, and maintaining the second circuit to form a second circuit layer; wherein a portion of the third plating layer is uncovered by the second circuit; removing the portion of the third plating layer that is uncovered by the second circuit; removing the baseboard; and removing the first plating layer, and maintaining the first circuit to form a first circuit layer.

3. The manufacturing method of the double layer circuit board as claimed in claim 2, wherein an area of the patterned third photoresist layer covering the at least one connecting pillar is greater than a section area of the at least one connecting pillar.

4. The manufacturing method of the double layer circuit board as claimed in claim 2, wherein the first to fourth photoresist layers are processed by exposure and development to form specific patterns on the first to fourth photoresist layers.

5. The manufacturing method of the double layer circuit board as claimed in claim 3, wherein the first to fourth photoresist layers are processed by exposure and development to form specific patterns on the first to fourth photoresist layers.

6. The manufacturing method of the double layer circuit board as claimed in claim 2, wherein the first to fourth photoresist layers are removed by stripper.

7. The manufacturing method of the double layer circuit board as claimed in claim 3, wherein the first to fourth photoresist layers are removed by stripper.

8. The manufacturing method of the double layer circuit board as claimed in claim 2, wherein the first to third plating layers are removed by etchant.

9. The manufacturing method of the double layer circuit board as claimed in claim 3, wherein the first to third plating layers are removed by etchant.

10. The manufacturing method of the double layer circuit board as claimed in claim 2, wherein the first to fourth photoresist layers are dry films.

11. The manufacturing method of the double layer circuit board as claimed in claim 3, wherein the first to fourth photoresist layers are dry films.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIG. 1 is a sectional view of an embodiment of a double layer circuit board;

[0047] FIG. 2 is a flowchart of an embodiment of a manufacturing method of a double layer circuit board;

[0048] FIGS. 3A-3V are schematic views of an embodiment of manufacturing a double layer circuit board;

[0049] FIG. 4 is a sectional view of a conventional double layer circuit board;

[0050] FIGS. 5A-5H are schematic views of manufacturing a conventional double layer circuit board.

DETAILED DESCRIPTION OF THE INVENTION

[0051] The present invention is a double layer circuit board and a manufacturing method thereof.

[0052] With reference to FIG. 1, the double layer circuit board comprises a substrate 10, a first circuit layer including a first circuit 11, a second circuit layer including a second circuit 12, and at least one connecting pillar 13.

[0053] The substrate 10 comprises a first surface and a second surface, and the first surface is opposite to the second surface.

[0054] The first circuit layer is formed on the first surface of the substrate 10.

[0055] The second circuit layer is formed on the second surface of the substrate 10.

[0056] The at least one connecting pillar 13 is formed in and covered by the substrate 10. Each one of the at least one connecting pillar 13 includes a first end and a second end, and the first end is opposite to the second end. The first end of the each one of the at least one connecting pillar 13 is connected to the first circuit 11. The second end of each one of the at least one connecting pillar 13 is connected to the second circuit 12.

[0057] The at least one first end and the at least one second end of the at least one connecting pillar 13 are respectively exposed out of the first surface and the second surface of the substrate 10. The first circuit 11 is formed on the first surface of the substrate 10 and connected to the at least one first end of the at least one connecting pillar 13, and the second circuit 12 is formed on the second surface of the substrate 10 and connected to the at least one second end of the at least one connecting pillar 13. Therefore, a depression may not be formed on a portion of the first circuit 11 and the second circuit 12 corresponding to the at least one connecting pillar 13.

[0058] Further, a terminal area of the at least one second end of the at least one connecting pillar 13 is greater than a terminal area of the at least one first end of the at least one connecting pillar 13. The terminal area of the at least one first end of the at least one connecting pillar 13 is a connecting area between the at least one connecting pillar 13 and the first circuit 11. A surface of the first circuit layer and the first surface of the substrate 10 are in a same plane, a plating layer is formed between the at least one connecting pillar 13 and the substrate 10, and another plating layer is formed between the second circuit 12 and the second surface of the substrate 10.

[0059] Therefore, when the second surface of the substrate 10 is drilled to expose the at least one second end of the at least one connecting pillar 13, a center of a hole drilled by laser is misaligned with a center of the at least one connecting pillar 13. A bottom of the hole drilled by laser may still expose the at least one second end of the at least one connecting pillar 13, and the second circuit 12 is firmly connected to the at least one second end of the at least one connecting pillar 13. Then, the second circuit 12 is firmly connected to the first circuit 11 through the at least one connecting pillar 13, and connecting strength between the first circuit layer and the second circuit layer is improved. A yield rate of the double layer circuit board is also improved.

[0060] With reference to FIG. 2, the manufacturing method of the double layer circuit board comprises the following steps:

[0061] providing a baseboard (S201);

[0062] forming a first photoresist layer on the first plating layer (S202);

[0063] patterning the first photoresist layer (S203);

[0064] forming a first circuit (S204);

[0065] forming a second photoresist layer (S205);

[0066] patterning the second photoresist layer to form at least one via (S206);

[0067] forming a second plating layer (S207);

[0068] forming at least one connecting pillar (S208);

[0069] forming a third photoresist layer (S209);

[0070] patterning the third photoresist layer (S210);

[0071] removing a portion of the second plating layer that is uncovered by the third photoresist layer (S211);

[0072] removing the first photoresist layer, the second photoresist layer, and the third photoresist layer (S212);

[0073] forming a substrate on the baseboard (S213);

[0074] drilling the second surface of the substrate (S214);

[0075] forming a third plating layer (S215);

[0076] forming a fourth photoresist layer (S216);

[0077] patterning the fourth photoresist layer (S217);

[0078] forming a second circuit (S218);

[0079] removing the fourth photoresist layer (S219);

[0080] removing a portion of the third plating layer that is uncovered by the second circuit (S220);

[0081] removing the baseboard (S221);

[0082] removing the first plating layer (S222).

[0083] Further with reference to FIGS. 2 and 3A-3V, in FIG. 3A, as recited in the step (S201), a baseboard 20 is provided, and a first plating layer 201 is formed on a surface of the baseboard 20.

[0084] In FIG. 3B, as recited in the step (S202), a first photoresist layer 21 is formed on the first plating layer 201.

[0085] In FIG. 3C, as recited in the step (S203), the first photoresist layer 21 is patterned to form a groove of a first circuit pattern in the first photoresist layer 21. The first plating layer 201 is exposed in the groove of the first circuit pattern.

[0086] In FIG. 3D, as recited in the step (S204), a first circuit 11 is formed in the groove of the first circuit pattern by plating the first plating layer 201 to fill the groove of the first circuit pattern.

[0087] In FIG. 3E, as recited in the step (S205), a second photoresist layer 22 is formed on the surface of the baseboard 20 to cover the first circuit 11 and the first photoresist layer 21.

[0088] In FIG. 3F, as recited in the step (S206), the second photoresist layer 22 is patterned to form at least one via 221 to expose a top surface of the first circuit 11.

[0089] In FIG. 3G, as recited in the step (S207), a second plating layer 202 is formed on a surface of the second photoresist layer 22 and in the at least one via 221.

[0090] In FIG. 3H, as recited in the step (S208), at least one connecting pillar 13 that fills the at least one via 221 is formed by plating the second plating layer 202 in the at least one via 221. Each one of the at least one connecting pillar 13 comprises a first end and a second end, and the first end is opposite to the second end. The first end is connected to the first circuit 11.

[0091] In FIG. 3I, as recited in the step (S209), a third photoresist layer 23 is formed on the at least one connecting pillar 13 and the plated second plating layer 202.

[0092] In FIG. 3J, as recited in the step (S210), the third photoresist layer 23 is patterned to cover the at least one second end of the at least one connecting pillar 13.

[0093] In FIG. 3K, as recited in the step (S211), a portion of the second plating layer 202 that is uncovered by the third photoresist layer 23 is removed.

[0094] In FIG. 3L, as recited in the step (S212), the first photoresist layer 21, the second photoresist layer 22, and the third photoresist layer 23 are removed, and the first circuit 11 and the at least one connecting pillar 13 are maintained.

[0095] In FIG. 3M, as recited in the step (S213), a substrate 10 is formed on the baseboard 20 to cover the first circuit 11 and the at least one connecting pillar 13. The substrate 10 comprises a first surface and a second surface, and the first surface is opposite to the second surface. The first surface faces to the baseboard 20.

[0096] In FIG. 3N, as recited in the step (S214), the second surface of the substrate 10 is drilled by laser to expose the at least one second end of the at least one connecting pillar 13 out of the second surface of the substrate 10.

[0097] In FIG. 3O, as recited in the step (S215), a third plating layer 203 is formed on the second surface of the substrate 10. The third plating layer 203 is electronically connected to the at least one connecting pillar 13.

[0098] In FIG. 3P, as recited in the step (S216), a fourth photoresist layer 24 is formed on a surface of the third plating layer 203.

[0099] In FIG. 3Q, as recited in the step (S217), the fourth photoresist layer 24 is patterned to form a groove of a second circuit pattern in the fourth photoresist layer 24. The third plating layer 203 is exposed in the groove of the second circuit pattern.

[0100] In FIG. 3R, as recited in the step (S218), a second circuit 12 is formed in the groove of the second circuit pattern on the third plating layer 203 by plating the third plating layer 203.

[0101] In FIG. 3S, as recited in the step (S219), the fourth photoresist layer 24 is removed to expose the third plating layer 203, and the second circuit 12 is maintained to form a second circuit layer. A portion of the third plating layer 203 is uncovered by the second circuit 12.

[0102] In FIG. 3T, as recited in the step (S220), the portion of the third plating layer 203 that is uncovered by the second circuit 12 is removed.

[0103] In FIG. 3U, as recited in the step (S221), the baseboard 20 is removed.

[0104] In FIG. 3V, as recited in the step (S222), the first plating layer 201 is removed, and the first circuit 11 is maintained to form a first circuit layer.

[0105] When the first circuit 11 is formed on the baseboard 20, the at least one connecting pillar 13 is formed by the first photoresist layer 21, the second photoresist layer 22, and the third photoresist layer 23. The at least one connecting pillar 13 is formed before the substrate 10 is formed. When the substrate 10 is formed, the substrate 10 covers the at least one connecting pillar 13. The at least one connecting pillar 13 is not formed by filling at least one via of the substrate 10. When the first circuit 11 and the second circuit 12 are formed, no via of the substrate 10 needs to be filled, and no depression may be formed on a portion of the first circuit 11 and the second circuit 12 corresponding to the at least one connecting pillar 13.

[0106] Therefore, regardless of a thickness of the substrate 10, the at least one connecting pillar 13 is formed before the substrate 10 is formed, and no depression may be formed on the portion of the first circuit 11 and the second circuit 12 corresponding to the at least one connecting pillar 13.

[0107] Further, the at least one connecting pillar 13 is not formed by simultaneously plating two plating layers, and an interspace may not be easily formed in the at least one connecting pillar 13. A yield rate of the double layer circuit board may be increased, and the double layer circuit board may not explode when a temperature of the double layer circuit board is raised.

[0108] When the first to fourth photoresist layers 21, 22, 23, 24 are patterned, the first to fourth photoresist layers 21, 22, 23, 24 are processed by exposure and development to form specific patterns on the first to fourth photoresist layers 21, 22, 23, 24.

[0109] When the first to fourth photoresist layers 21, 22, 23, 24 are removed, the first to fourth photoresist layers 21, 22, 23, 24 are removed by stripper.

[0110] When the first to third plating layers 201, 202, 203 are removed, the first to third plating layers 201, 202, 203 are removed by etchant.

[0111] In the embodiment, the first to fourth photoresist layers 21, 22, 23, 24 are dry films.

[0112] In the embodiment, an area of the patterned third photoresist layer 23 covering the at least one connecting pillar 13 is greater than a section area of the at least one connecting pillar 13. Therefore, when the exposed and plated second plating layer 202 is removed, a terminal area of the at least one second end of the at least one connecting pillar 13 will be greater than a terminal area of the at least one first end of the at least one connecting pillar 13. The terminal area of the at least one first end of the at least one connecting pillar 13 is a connecting area between the at least one connecting pillar 13 and the first circuit 11.

[0113] Therefore, when the second surface of the substrate 10 is drilled by laser to expose the at least one second end of the at least one connecting pillar 13 and a center of a hole drilled is misaligned with a center of the at least one connecting pillar 13, a bottom of the hole drilled by laser may still expose the at least one second end of the at least one connecting pillar 13. The second circuit 12 is well connected to the at least one second end of the at least one connecting pillar 13. Then, the second circuit 12 is well connected to the first circuit 11 through the at least one connecting pillar 13, and a yield rate of the double layer circuit board may be increased.

[0114] Even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only. Changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.