INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION

Abstract

Integrated circuits with electrostatic discharge (ESD) protection and methods of providing ESD protection in an integrated circuit are provided. An ESD protection circuit the ESD protection circuit may incorporate a transistor, such as a MOSFET, and a voltage limiter coupled to a gate of the transistor. The voltage limiter may be configured such that with an ESD disturbance on the voltage supply rail, Vdd, a gate voltage of the transistor of the ESD protection circuit is held below the supply voltage (Vdd) inducing base current, Isub, within the transistor to effectively shunt a current arising from the ESD event from the voltage supply rail Vdd to the voltage supply rail Vss.

Claims

1. An integrated circuit electrostatic discharge protection circuit comprising: a transistor having a drain operatively coupled to a first rail of the integrated circuit and a source operatively coupled to a second rail of the integrated circuit; a trigger circuit operatively coupled to drive a gate of the transistor in response to an ESD event occurring on one of the first and second rails, wherein the trigger circuit includes a voltage limiter operatively coupled from the gate to the source of the transistor the voltage limiter selectively limiting the gate voltage to a voltage less than a full turn on voltage of the transistor, but sufficient to induce a current flow within the transistor responsive to the ESD event.

2. The integrated circuit of claim 1, wherein the first rail has a voltage Vdd, and wherein the voltage limiter is configured to limit the voltage to the gate to less than Vdd.

3. The integrated circuit of claim 2, wherein the voltage limiter is configured to limit the voltage to the gate to less than or equal to one-half Vdd.

4. The integrated circuit of claim 2, wherein Vdd is equal to 2.5 volts (V), and the voltage limiter is configured to limit the voltage to the gate to approximately 1V.

5. The integrated circuit of claim 1, wherein the voltage limiter is configured to limit the voltage to the gate such that the transistor is not fully turned on.

6. The integrated circuit of claim 1, wherein the voltage limiter is configured to limit the voltage to the gate such that a parasitic current is induced within the transistor.

7. The integrated circuit of claim 1, wherein the voltage limiter is configured to limit the voltage to the gate such that a base, Isub current is induced within the transistor.

8. The integrated circuit of claim 1, wherein the voltage limiter comprises a diode.

9. The integrated circuit of claim 1, wherein the voltage limiter comprises a plurality of diodes arranged in series.

10. A method providing electrostatic discharge protection in an integrated circuit comprising: disposing a transistor coupled between a first rail and a second rail of the integrated circuit; and inducing a parasitic current within the transistor responsive to an ESD event occurring on one of the first and second rails.

11. The method of claim 10, wherein inducing a parasitic current within the transistor comprises limiting a turn on voltage applied to a gate of the transistor.

12. The method of claim 10, wherein inducing a parasitic current within the transistor comprises limiting a turn on voltage applied to a gate of the transistor to less than a full turn on voltage for the transistor.

13. The method of claim 11, wherein with first rail has a voltage Vdd, and limiting a turn on voltage applied to a gate of the transistor comprises limiting the turn on voltage to be less than Vdd.

14. The method of claim 13, wherein the first rail has a voltage Vdd, and limiting a turn on voltage applied to a gate of the transistor comprises limiting the turn on voltage to less than one-half Vdd.

15. The integrated circuit of claim 13, wherein Vdd is 2.5 volts (V), and the method comprises limiting the turn on voltage to approximately 1V.

16. A method of providing electrostatic discharge (ESD) protection in an integrated circuit, the integrated circuited including a transistor coupled between a first rail and a second rail of the integrated circuit, the method comprising: providing a voltage limited gate turn-on voltage to a gate of the transistor responsive to an ESD events, and inducing a current between the first rail and the second rail via the transistor.

17. The method of claim 16, wherein inducing the current comprises inducing a parasitic current within the transistor.

18. The method of claim 16, wherein providing the voltage limited gate turn-on voltage to the gate comprises limiting a turn on voltage applied to the gate to less than a full turn on voltage for the transistor.

19. The method of claim 16, wherein the first rail has a voltage Vdd, and limiting a turn on voltage applied to a gate of the transistor comprises limiting the turn on voltage to less than Vdd.

20. The method of claim 16, wherein the first rail has a voltage Vdd, and limiting a turn on voltage applied to a gate of the transistor comprises limiting the turn on voltage to less than one-half Vdd.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:

[0016] FIG. 1 is a schematic circuit diagram of an integrated circuit with an electrostatic discharge protection circuit in accordance with herein described embodiments;

[0017] FIG. 2 is a schematic circuit diagram of a voltage limiter that may be used in the ESD protection circuit shown in FIG. 1; and

[0018] FIG. 3 graphically depicts performance of an electrostatic discharge protection circuit in accordance with the herein described embodiments.

DETAILED DESCRIPTION

[0019] The following detailed description is merely exemplary in nature and is not intended to limit the various embodiments or the application and uses thereof. Furthermore, there is no intention to be bound by any theory presented in the preceding background or the following detailed description. Embodiments of the present disclosure are generally directed to integrated circuits, and methods for configuring and operating the same. The various structures, elements, tasks and steps described herein may be incorporated into a more comprehensive structure, procedure or process having additional elements, steps or functionality not described in detail herein. In particular, many structures, designs and methods of producing integrated circuits are well-known and so, in the interest of brevity, many conventional aspects of IC will only be mentioned briefly herein or will be omitted entirely without providing the well-known details.

[0020] Referring to the exemplary embodiment depicted in FIG. 1, an integrated circuit 10 includes an ESD event triggered ESD protection circuit 20. The ESD protection circuit 20 protects a Vdd power supply rail 22 from a positive ESD event, graphically depicted in FIG. 1 as ESD event 12, referenced to grounded Vss power supply rail 24. ESD protection circuit 20 includes a trigger circuit 26, a buffer circuit 28 and a N-channel MOSFET clamp transistor 30.

[0021] The trigger circuit 26 is designed as a resistor-capacitor (RC) transient detector, utilizing a resistive element, shown as resistor 32 and a capacitive element, shown as capacitor 34. It will be appreciated that implementations of ESD protection circuit 20 may use virtually any suitable resistive and capacitive structures to form trigger circuit 26, and designing and forming resistive and capacitive structures within an integrated circuit is well within the ability of the person of ordinary skill in the art.

[0022] The buffer circuit 28 drives the gate 36 of the transistor 30 relative to a voltage at node 38 of the trigger circuit 26. As shown, the buffer circuit 28 may include one, but typically more than one inverter 40, and as illustrated in FIG. 1, in one implementation the buffer circuit incorporates three (3) operatively coupled inverters 40.

[0023] ESD events such as ESD event 12 typically occur during off-chip handling and processing when the circuit incorporating the IC 10 is generally not assembled. In response to the ESD event 12 inducing a rapid positive voltage increase on the Vdd rail 22, trigger circuit 26 initially holds the node 38 around zero voltage. The buffer circuit 28, with an input connected to node 38, then attempts to drive the gate 36 of transistor 30 to the voltage of Vdd rail 22 in order to turn on the transistor 30, i.e., Vg˜=Vdd. It is noted that as used herein Vdd denotes the voltage of Vdd rail 22, which during an ESD event may denote a voltage of the ESD protection clamp voltage level of the Vdd rail 22. This value of Vdd may not necessarily be equal to the regular or normal operating voltage of the IC 10, which also during normal operating mode is generally referred to as Vdd.

[0024] Further shown in FIG. 3 a voltage limiter 50 is coupled from the gate 36 to the transistor source, which is also coupled to and held at the grounded Vss rail 24 potential. The voltage limiter 50 is configured to limit the gate voltage (Vg) to a value less than Vdd as described below.

[0025] When configured as a nMOSFET, the transistor 30 has a drain-body-source parasitic bipolar transistor component illustrated for discussion purposes in FIG. 1 as transistor 52 which conducts the parasitic current, Isub. In contrast, a pMOSFET would have a PNP transistor. Although this parasitic current conducting transistor effect must be prevented for normal MOSFET operation, in accordance with the herein described embodiments, this otherwise parasitic effect may be utilized during ESD events.

[0026] As the voltage rise on Vdd rail 22 continues in response to the ESD event, the drain voltage increases so that impact ionization (II) begins to occur within the drain-body-source parasitic bipolar transistor 52, which creates the so called parasitic current, Isub, flowing into the substrate. However, it is commonly known that baseline MOSFETS have a peak value of Isub at a certain gate bias (Vg), not too low, not too high, and a typical value is around Vg=1˜2V. The gate voltage limiter 50 is here configured to limit the gate voltage such that the induced current, Isub, is maximized.

[0027] Generally speaking, the current amplifying factor beta (β) of the transistor 52 is not very high, for example the amplifying value may be from about 1 to about 10. A parasitic PNP has an even lower amplifying factor β. The above-mentioned Isub forms as a base current and is amplified as β*Isub, which is sufficient for the transistor 30 to discharge ESD current from Vdd rail 22 to Vss rail 24.

[0028] For a given transistor construction and manufacturing process, the gate voltage value to achieve peak Isub will vary. Ideally, the gate voltage limiter is selected to achieve peak Isub. The value of gate voltage to achieve peak Isub for any given transistor construction is well characterized and known to the designer. Generally speaking, in an embodiment wherein Vdd is at or held at ˜=2.5V, the voltage limiter may be configured to hold the gate voltage, Vg, to half or less than Vdd. Still further, the voltage limiter may be configured to limit the gate voltage, Vg, to approximately 1V, i.e., Vg˜=1V. In any event, the value of the gate voltage, Vg, will be selected to maximize the value of Isub.

[0029] Once the current Isub is induced within the transistor 52, the transistor 30 acts as a low resistance shunt between the Vdd rail 22 and the Vss rail 24. Transistor 30 will remain in this state for a period of time, which is determined by the RC time constant of trigger circuit 26. As a result, this RC time constant should be set long enough to exceed the maximum expected duration of an ESD event, typically three to five hundred nanoseconds, while short enough to avoid false triggering of the protection circuit 20 during normal ramp-up of the Vdd rail 22. This Vdd ramp-up during normal operation typically requires two to five milliseconds. Note that once Vdd reaches a constant power supply level as is associated with normal operation, transistor 30 is biased in a nonconductive state as is required for normal operation.

[0030] The voltage limiter 50 may be of any suitable construction. A possible embodiment is shown in FIG. 2 as a stack of N diodes 54. As shown in FIG. 2, the voltage limiter 50 is formed by two (2) diodes 54. It should be appreciated that any suitable number of diodes may be used, and generally, the voltage limiter 50 may be constructed of Nx diodes, where x is a non-zero, positive integer, in order to achieve approximately the desired gate clamp voltage. As is known to the designer, transistor stacks, diode stacks, and other such structures having known, fixed voltage clamping characteristics may be used.

[0031] With the configuration of the voltage limiter 50 depicted in FIG. 2, the gate voltage Vg˜=N*Vdio, where Vdio is the single diode voltage drop and N is the number of diodes, for example. Using two (2) diodes provides a gate clamp voltage of Vg˜=1V, which for the embodiments shown here approximately maximizes the induced current, Isub, in the transistor 30.

[0032] FIG. 3 illustrates the effectiveness of an electrostatic discharge protection circuit, such as circuit 20, in accordance with the herein described embodiments. FIG. 3 plots transmission line pulse (TLP) test data for an ESD protection circuit of traditional construction in comparison to an ESD protection circuit in accordance with one or more of the herein described embodiments. In particular, data is shown in FIG. 3 for an ESD protection circuit in accordance with an embodiment in which a single diode voltage limiter, limiter 50, is applied to the gate of the ESD protection clamp transistor, transistor 30. The TLP test and resulting data are otherwise standard.

[0033] Illustrated in FIG. 3 along the Y and X axes are TLP current in amperes (A) and TLP voltage in volts (V), respectively. The upper X axis provides leakage current in amperes (A). The TLP test depicts actual test data using a pulse width of 100 ns and a rise of time of 2 ns, referenced as 100/2 ns, and simulation data of the same conditions, referenced as 100_Simu. ESD protection transistor, e.g., transistor 30, Idsat is shown in high, typical and low ampere (A) values. Leakage current, referenced to the upper X axis, is shown sampled at 2.5V. And, It2, the second breakdown current, which indicates when the device has failed, is illustrated for both the traditional ESD protection circuit and the ESD protection circuit in accordance with the herein described embodiments.

[0034] As is readily apparent from the data depicted is the marked improvement in It2 provided by ESD protection circuits as herein described over traditional constructions. The data depicted in FIG. 3 supports a conclusion that the herein described ESD protection circuits provide up to 50 percent better It2 performance. Further illustrated in FIG. 3 is the improvement in ESD current conduction before leakage breakdown, as shown by the comparison of leakage current for the traditional ESD protection circuit and the ESD protection circuit in accordance with the herein described embodiments.

[0035] As disclosed and described herein, improvement in ESD protection may be obtained notwithstanding the limitations on MOSFET size and turn on capability of traditional ESD protection circuits. Advantageously, the parasitic current conducting transistor effect of the MOSFET is leveraged to improve ESD current conduction. This transistor affect is induced by limiting the turn on gate voltage of the MOSFET and taking advantage of the induced current Isub and transistor amplifier effect B. In an ESD circuit, a voltage limiter may be coupled between the gate and the source of the MOSFET, where the voltage limiter is configured to limit the gate voltage to a predetermined value selected to maximize Isub within the MOSFET.

[0036] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the application in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing one or more embodiments, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope, as set forth in the appended claims.