Liquid crystal display device

Abstract

Disclination of an active matrix liquid crystal display device is reduced. Portions of pixel electrodes are formed so as to mutually overlap with a convex portion. If the height of the convex portion is too tall, the amount of light leakage increases due to liquid crystals orienting diagonally with respect to a substrate surface. (See FIG. 1C.) If the height of the convex portion is low, the disclination reduction effect is low. The optimal convex portion height is thus determined.

Claims

1. A display device comprising: a semiconductor layer over a substrate; a gate wiring comprising a first conductive material over the substrate; a source wiring comprising a second conductive material over the substrate, the source wiring intersecting the gate wiring; a convex portion over the substrate, the convex portion having a first part extending in parallel with the gate wiring and second and third parts each extending in parallel with the source wiring; and a pixel electrode electrically connected to the semiconductor layer, a first edge of the pixel electrode overlapping with the second part of the convex portion and a second edge of the pixel electrode overlapping with the third part of the convex portion, wherein the convex portion includes a pattern comprising the first conductive material, wherein a first part of the semiconductor layer intersects the first part of the convex portion, and wherein the semiconductor layer is not overlapped with the second and third parts of the convex portion.

2. The display device according to claim 1, wherein the pixel electrode is provided on an interlayer insulating film.

3. The display device according to claim 1, further comprising a storage capacitor over the substrate, the storage capacitor comprising a first electrode comprising the semiconductor layer.

4. The display device according to claim 1, wherein the convex portion comprises a film provided on an interlayer insulating film.

5. The display device according to claim 4, wherein the film is selected from the group consisting of a photosensitive organic resin film, an organic resin film, a silicon oxide film, a silicon nitride film and a silicon oxynitride film.

6. The display device according to claim 1, wherein a taper angle of the convex portion is less than 90°.

7. The display device according to claim 1, wherein the display device is a reflective type liquid crystal display device.

8. The display device according to claim 1, wherein the display device is a transmission type liquid crystal display device.

9. The display device according to claim 1, wherein the display device is applied to an electronic equipment selected from the group consisting of a video camera, a digital camera, a projector, a head mounted display, a mobile computer, a portable telephone and an electronic notebook.

10. A display device comprising: a semiconductor layer over a substrate; a gate wiring comprising a first conductive material over the substrate; a source wiring comprising a second conductive material over the substrate, the source wiring intersecting the gate wiring; a convex portion over the substrate, the convex portion having a first part extending in parallel with the gate wiring and second and third parts each extending in parallel with the source wiring; and a pixel electrode electrically connected to the semiconductor layer, a first edge of the pixel electrode overlapping with the second part of the convex portion and a second edge of the pixel electrode overlapping with the third part of the convex portion, wherein the first part of the convex portion intersects the source wiring and a first part of the semiconductor layer, wherein the convex portion includes a pattern comprising the first conductive material, and wherein the semiconductor layer is not overlapped with the second and third parts of the convex portion.

11. The display device according to claim 10 wherein the pixel electrode is provided on an interlayer insulating film.

12. The display device according to claim 10, further comprising a storage capacitor over the substrate, the storage capacitor comprising a first electrode comprising the semiconductor layer.

13. The display device according to claim 10, wherein the convex portion comprises a film provided on an interlayer insulating film.

14. The display device according to claim 13, wherein the film is selected from the group consisting of a photosensitive organic resin film, an organic resin film, a silicon oxide film, a silicon nitride film and a silicon oxynitride film.

15. The display device according to claim 10, wherein a taper angle of the convex portion is less than 90°.

16. The display device according to claim 10, wherein the display device is a reflective type liquid crystal display device.

17. The display device according to claim 10, wherein the display device is a transmission type liquid crystal display device.

18. The display device according to claim 10, wherein the display device is applied to an electronic equipment selected from the group consisting of a video camera, a digital camera, a projector, a head mounted display, a mobile computer, a portable telephone and an electronic notebook.

19. A display device comprising: a thin film transistor comprising a semiconductor layer over a substrate; a gate wiring comprising a first conductive material over the substrate; a source wiring comprising a second conductive material over the substrate, the source wiring intersecting the gate wiring; an interlayer insulating film over the thin film transistor; a convex portion over the substrate, the convex portion having a first part extending in parallel with the gate wiring and second and third parts each extending in parallel with the source wiring; and a pixel electrode electrically connected to the thin film transistor through a contact hole of the interlayer insulating film, a first edge of the pixel electrode overlapping with the second part of the convex portion and a second edge of the pixel electrode overlapping with the third part of the convex portion, wherein the convex portion includes a pattern comprising the first conductive material, wherein a first part of the semiconductor layer intersects the first part of the convex portion, and wherein the semiconductor layer is not overlapped with the second and third parts of the convex portion.

20. The display device according to claim 19, wherein the pixel electrode is provided on the interlayer insulating film.

21. The display device according to claim 19, further comprising a storage capacitor over the substrate, the storage capacitor comprising a first electrode comprising the semiconductor layer.

22. The display device according to claim 19, wherein the convex portion comprises a film provided on the interlayer insulating film.

23. The display device according to claim 22, wherein the film is selected from the group consisting of a photosensitive organic resin film, an organic resin film, a silicon oxide film, a silicon nitride film and a silicon oxynitride.

24. The display device according to claim 19, wherein a taper angle of the convex portion is less than 90°.

25. The display device according to claim 19, wherein the display device is a reflective type liquid crystal display device.

26. The display device according to claim 19, wherein the display device is a transmission type liquid crystal display device.

27. The display device according to claim 19, wherein the display device is applied to an electronic equipment selected from the group consisting of a video camera, a digital camera, a projector, a head mounted display, a mobile computer, a portable telephone and an electronic notebook.

28. The display device according to claim 1, wherein each of the gate wiring, the source wiring, and the pattern has a multi-layer structure.

29. The display device according to claim 10, wherein each of the gate wiring, the source wiring, and the pattern has a multi-layer structure.

30. The display device according to claim 19, wherein each of the gate wiring, the source wiring, and the pattern has a multi-layer structure.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the accompanying drawings:

(2) FIGS. 1A to 1C are cross sectional diagrams showing the principles of the present invention;

(3) FIG. 2 is a cross sectional diagram showing a simulation model of the present invention;

(4) FIG. 3 is a cross sectional diagram showing simulation results when there is no convex portion;

(5) FIG. 4 is a cross sectional diagram showing simulation results when there is a convex portion having a height of 0.3 μm;

(6) FIG. 5 is a cross sectional diagram showing simulation results when there is a convex portion having a height of 0.7 μm;

(7) FIG. 6 is a cross sectional diagram showing simulation results when there is a convex portion having a height of 1.0 μm;

(8) FIG. 7 is a cross sectional diagram showing simulation results when there is a convex portion having a height of 1.5 μm;

(9) FIG. 8 is a cross sectional diagram showing simulation results when there is a convex portion having a height of 3.0 μm;

(10) FIG. 9 is a diagram showing the relationship between: the height of a convex portion with respect to a cell gap; and the amount of light leakage and the width of disclination;

(11) FIG. 10 is a cross sectional diagram showing the definition of a horizontal direction electric field and a vertical direction electric field;

(12) FIG. 11 is a cross sectional diagram showing simulation results when there is no convex portion;

(13) FIG. 12 is a cross sectional diagram showing simulation results when a pixel electrode does not overlap with a convex portion;

(14) FIG. 13 is a cross sectional diagram showing simulation results when there is a pixel electrode on a side portion of a convex portion;

(15) FIG. 14 is a cross sectional diagram showing simulation results when there is a pixel electrode in a side portion and an upper edge portion;

(16) FIG. 15 is a cross sectional diagram showing simulation results when there is a pixel electrode in a side portion and an upper edge portion;

(17) FIGS. 16A and 16B are diagrams showing the relationship between the width of a first region of a pixel electrode and a disclination width;

(18) FIG. 17 is an upper surface diagram showing an example of an embodiment mode of the present invention;

(19) FIG. 18 is an upper surface diagram shown an example of an embodiment mode of the present invention;

(20) FIG. 19 is an upper surface diagram shown an example of an embodiment mode of the present invention;

(21) FIG. 20 is an upper surface diagram shown an example of an embodiment mode of the present invention;

(22) FIGS. 21A to 21C are cross sectional diagrams showing a process of manufacturing an active matrix substrate (Embodiment 1);

(23) FIGS. 22A to 22C are cross sectional diagrams showing the process of manufacturing an active matrix substrate (Embodiment 1);

(24) FIG. 23 is a cross sectional diagram showing the process of manufacturing an active matrix substrate (Embodiment 1);

(25) FIG. 24 is a cross sectional diagram showing the process of manufacturing an active matrix substrate (Embodiment 1);

(26) FIG. 25 is an upper surface diagram showing a pixel portion of an active matrix substrate (Embodiment 1);

(27) FIG. 26 is a cross sectional diagram showing a liquid crystal display device (Embodiment 3);

(28) FIG. 27 is a cross sectional diagram showing a process of manufacturing an active matrix substrate (Embodiment 2);

(29) FIG. 28 is a cross sectional diagram showing the process of manufacturing an active matrix substrate (Embodiment 2);

(30) FIG. 29 is an upper surface diagram showing a pixel portion of an active matrix substrate (Embodiment 2);

(31) FIGS. 30A to 30F are diagrams showing examples of electronic devices (Embodiment 4);

(32) FIGS. 31A to 31D are diagrams showing examples of electronic devices (Embodiment 4);

(33) FIGS. 32A to 32C are diagrams showing examples of electronic devices (Embodiment 4);

(34) FIGS. 33A to 33C are diagrams showing an electrode and a convex portion of an experimental substrate;

(35) FIGS. 34A to 34D are diagrams showing the change in liquid crystal orientation due to a first width of a pixel electrode;

(36) FIG. 35 is a cross sectional diagram showing an electric power supply line when a convex portion has a taper;

(37) FIG. 36 is a diagram showing the relationship between: the height of a convex portion with respect to a cell gap; and the amount of light leakage and the width of disclination; and

(38) FIGS. 37A and 37B are diagrams showing the polarity of a voltage applied to a pixel when performing source line inversion drive.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(39) Embodiment Mode

(40) An embodiment mode of the present invention is shown in FIGS. 17 to 20. Note that the same reference symbols are used in FIGS. 17 to 20 for portions having identical functions.

(41) The upper surface diagram of a pixel shown in FIG. 17 shows a semiconductor layer 306, a gate wiring 301 which becomes a gate electrode of the semiconductor layer, a source wiring 302 which is electrically connected to a source region of the semiconductor layer, and a pixel electrode 303 electrically connected to a drain region of the semiconductor layer through a contact hole 305. In FIG. 17A, a convex portion 304 of the present invention is formed on the source wiring 302, parallel to the source wiring. There is an effect of reducing disclination and light leakage formed parallel to the source wiring in edge portion of the pixel electrode when performing source line inversion drive. Showing the effect of the present invention is a first region of the pixel electrode formed overlapping with an upper edge portion of the convex portion, and a second region of the pixel electrode formed in a side portion of the convex portion. The convex portion is therefore formed mutually overlapping with the pixel electrode.

(42) When gate line inversion drive is performed, the convex portion of the present invention may be formed parallel to the gate wiring.

(43) An upper surface of the pixel shown in FIG. 18 has the convex portion 304 of the present invention formed parallel to the source wiring 302 and the gate wiring 301. For example, the horizontal direction electric field develops not only in the space between adjacent electrodes sandwiched by the source wirings, but also between adjacent pixel electrodes sandwiched by the gate wirings when source line inversion drive is performed. FIG. 18 possesses effects of lowering disclination and light leakage formed by the horizontal direction electric field between adjacent pixel electrodes sandwiched by the gate wirings. The convex portion is the same as that of FIG. 17, and is formed in a region mutually overlapping with the pixel electrode.

(44) An upper surface of the pixel shown in FIG. 19 has the convex portion 304 of the present invention formed in parallel with the source wiring 302 and the gate wiring 301. In FIG. 18, the convex portion is tall, and the fiber tips of a rubbing cloth do not reach a concave portion in a gap between the convex portions 304 of FIG. 18, and rubbing irregularities may develop. In order to make the rubbing uniform in FIG. 19, convex portions are also formed as dummy patterns in portions at which the convex portions and the pixel electrodes 303 do not overlap.

(45) The height of the convex portions may be set equal to no greater than 4.4% of the cell gap, and equal to or less than 22.5% of the cell gap, preferably between 4.4% and 15.6% of the cell gap, when the cell gap is equal to or greater than 3.0 μm, and equal to or less than 4.5 μm, in FIGS. 17 to 19. Further, when the cell gap is less than 3.0 μm, it is preferable to set the height of the convex portions equal to or less than 15.6% of the cell gap, more preferably equal to or less than 6.7% of the cell gap. It is preferable that the height of the convex portions be equal to or less than 15.6% of the cell gap if the cell gap is greater than 4.5 μm.

(46) An upper surface of the pixel shown in FIG. 20 has the convex portion of the present invention formed in parallel with the source wiring 302 and the gate wiring 301. The height of the convex portion changes depending upon location. For example, the horizontal direction electric field when source line inversion drive is performed is formed not only between adjacent pixel electrodes sandwiched by the source wirings 302, but also between adjacent pixel electrodes sandwiched by the gate wirings 301. The horizontal direction electric field between the adjacent pixel electrodes sandwiched by the source wirings is larger, of course. Considering the way that the electric force lines formed between the adjacent pixel electrodes are formed, the height of the convex portion may be changed. In FIG. 20, a convex portion 307 having a first height, and a convex portion 308 having a second height are shown. The height of the convex portions may be additionally changed depending on the way the electric field is formed. For example, it is also possible to make the convex portion having the first height relatively higher than the convex portion having the second height, depending on the way the lines of electric force are formed.

(47) The heights of the convex portion having the first height and the convex portion having the second height are preferably equal to or greater than 4.4%, and equal to or less than 22.5%, of the cell gap, and may be set equal to or greater than 4.4%, and equal to or less than 15.6%, of the cell gap when the cell gap is from 3.0 μm to 4.5 μm. Further, if the cell gap is less than 3.0 μm, it is preferable that the convex portion having the first height and the convex portion having the second height be equal to or less than 15.6% of the cell gap, more preferably equal to or less than 6.7% of the cell gap. When the cell gap is greater than 4.5 μm, it is preferable that the convex portion having the first height and the convex portion having the second height be equal to or less than 15.6% of the cell gap.

(48) The convex portions may be formed by patterning a photosensitive organic resin film, or an organic resin film, by a photolithography process. It is also possible, of course, to form the convex portion by patterning an inorganic film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

(49) The light sensitive resin film may be formed twice in order to change the height of the pixel portions by location. Further, substrate elements such as semiconductor layers, gate wirings, and source wirings may also be formed in locations at which one wants to increase the height of the convex portions, and may be formed selectively in a convex shape before forming the pixel electrodes.

(50) Further, in FIGS. 17 to 20 the width of the first region of the pixel electrode formed in the upper portion of the convex portion may be set equal to or greater than 0.5 μm, preferably equal to or greater than 1.0 μm.

(51) The present invention is not limited by the above stated embodiment mode, and it is also possible to combine the characteristics of the embodiment mode.

(52) Embodiments

(53) [Embodiment 1]

(54) An embodiment of the present invention is explained using FIGS. 21A to 25.

(55) Note that a description is set forth regarding a step for fabricating a pixel TFT; a switching element of the pixel portion and TFTs for driver circuit (a signal line driver circuit and a scanning line driver circuit) provided in the pixel portion of a display device using the driver method of the present invention and periphery portion of the pixel portion. For the simplicity of the explanation, a CMOS circuit, which is a fundamental structure circuit for the driver circuit portion, and the n-channel TFT for the pixel TFT of the pixel portion are shown in figures by a cross-sectional figure according to the path.

(56) First, as shown in FIG. 21A, a base film 401 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, is formed on a substrate 400 made of a glass such as barium borosilicate glass or aluminum borosilicate glass, typically a glass such as Coming Corp. #7059 glass or #1737 glass. For example, a lamination film of a silicon oxynitride film 401a, manufactured from SiH.sub.4, NH.sub.3, and N.sub.2O by plasma CVD, and formed having a thickness of 1.0 to 200 nm (preferably between 50 and 100 nm), and a hydrogenated silicon oxynitride film 401b, similarly manufactured from SiH.sub.4 and N.sub.2O, and formed having a thickness of 50 to 200 nm (preferably between 100 and 150 nm), is formed. A two-layer structure is shown for the base film 401 in Embodiment 1, but a single layer film of the insulating film, and a structure in which more than two layers are laminated, may also be formed.

(57) Island shape semiconductor layers 402 to 406 are formed by crystalline semiconductor films made from a semiconductor film having an amorphous structure, using a laser crystallization method or a known thermal crystallization method. The thickness of the island shape semiconductor layers 402 to 406 may be formed from 25 to 80 nm (preferably between 30 and 60 nm). There are no limitations placed on the materials for forming a crystalline semiconductor film, but it is preferable to form the crystalline semiconductor films by silicon or a silicon germanium (SiGe) alloy.

(58) A laser such as a pulse oscillation type or continuous light emission type excimer laser, a YAG laser, or a YVO.sub.4 laser can be used to fabricate the crystalline semiconductor films by the laser crystallization method. A method of condensing laser light emitted from a laser oscillator into a linear shape by an optical system and then irradiating the light to the semiconductor film may be used when these types of lasers are used. The crystallization conditions may be suitably selected by the operator, but when using the excimer laser, the pulse oscillation frequency is set to 30 Hz, and the laser energy density is set form 100 to 400 mJ/cm.sup.2 (typically between 200 and 300 mJ/cm.sup.2). Further, when using the YAG laser, the second harmonic is used and the pulse oscillation frequency is set from 1 to 10 kHz, and the laser energy density may be set from 300 to 600 ml/cm.sup.2 (typically between 350 and 500 mJ/cm.sup.2). The laser light condensed into a linear shape with a width of 100 to 1000 μm, for example 400 μm, is then irradiated over the entire surface of the substrate. This is performed with an overlap ratio of 80 to 98% for the linear laser light.

(59) A gate insulating film 407 is formed covering the island shape semiconductor layers 402 to 406. The gate insulating film 407 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by plasma CVD or sputtering. A 120 nm thick silicon oxynitride film is formed in Embodiment 1. The gate insulating film is not limited to this, type of silicon oxynitride film, of course, and other insulating films containing silicon may also be used in a single layer or in a lamination structure. For example, when using a silicon oxide film, it can be formed by plasma CVD with a mixture of TEOS (tetraethyl orthosilicate) and O.sub.2, at a reaction pressure of 40 Pa, with the substrate temperature set from 300 to 400° C., and by discharging at a high frequency (13.56 MHZ) electric power density of 0.5 to 0.8 W/cm.sup.2. Good characteristics as a gate insulating film can be obtained by subsequently performing thermal annealing, at between 400 and 500° C., of the silicon oxide film thus manufactured.

(60) A first conductive film 408 and a second conductive film 409 are then formed on the gate insulating film 407 in order to form gate electrodes. The first conductive film 408 is formed of a TaN film with a thickness of 50 to 100 nm, and the second conductive film 409 is formed of a W film having a thickness of 100 to 300 nm, in Embodiment 1.

(61) The W film is formed by sputtering with a W target, which can also be formed by thermal CVD using tungsten hexafluoride (WF.sub.6). Whichever is used, it is necessary to make the film become low resistance in order to use it as the gate electrode, and it is preferable that the resistivity of the W film be made equal to or less than 20 μΩcm. The resistivity can be lowered by enlarging the crystal grains of the W film, but for cases in which there are many impurity elements such as oxygen within the W film, crystallization is inhibited, thereby the film becomes high resistance. A W target having a purity of 99.9999% is thus used in sputtering. In addition, by forming the W film while taking sufficient care that no impurities from the gas phase are introduced at the time of film formation, the resistivity of 9 to 20 μΩcm can be achieved.

(62) Note that, although the first conductive film 408 is a TaN film and the second conductive film 409 is a W film in Embodiment 1, both may also be formed from an element selected from the group consisting of Ta, W, Ti, Mo, Al, and Cu, or from an alloy material having one of these elements as its main constituent, and a chemical compound material. Further, a semiconductor film, typically a polycrystalline silicon film into which an impurity element such as phosphorus is doped, may also be used. Examples of preferable combinations other than that used in Embodiment 1 include: forming the first conductive film 408 by tantalum nitride (TaN) and combining it with the second conductive film 409 formed from a W film; forming the first conductive film 408 by tantalum nitride (TaN) and combining it with the second conductive film 409 formed from an Al film; and forming the first conductive film 408 by tantalum nitride (TaN) and combining it with the second conductive film 409 formed from a Cu film.

(63) Then, masks 410 to 415 are formed from resist, and a first etching treatment is performed in order to form electrodes and wirings. An ICP (inductively coupled plasma) etching method is used in Embodiment 1. An etching gas is mixed, and a plasma is generated by applying a 500 W RF electric power (13.56 MHZ) to a coil shape electrode at 1 Pa. A 100 W RF electric power (13.56 MHZ) is also applied to the substrate side (test piece stage), effectively applying a negative self-bias voltage. By the etching gas is selected appropriately, the W film and the Ta film are etched to the approximately same level.

(64) Edge portions of the first conductive layer and the second conductive layer are made into a tapered shape in accordance with the effect of the bias voltage applied to the substrate side under the above etching conditions by using a suitable resist mask shape. The angle of the tapered portions is from 15 to 45°. The etching time may be increased by approximately 10 to 20% in order to perform etching without any residue remaining on the gate insulating film. The selectivity of a silicon oxynitride film with respect to a W film is from 2 to 4 (typically 3), and therefore approximately 20 to 50 nm of the exposed surface of the silicon oxynitride film is etched by this over-etching process. First shape conductive layers 417 to 422 (first conductive layers 417a to 422a and second conductive layers 417b to 422b) are thus formed of the first conductive layers and the second conductive layers in accordance with the first etching process. Reference numeral 416 denotes a gate insulating film, and the regions not covered by the first shape conductive layers 417 to 422 are made thinner by etching of about 20 to 50 nm.

(65) A first doping process is then performed, and an impurity element which imparts n-type conductivity is added. Ion doping or ion injection may be performed for the method of doping. Ion doping is performed under the conditions of a dose amount of from 1×10.sup.13 to 5×10.sup.14 atoms/cm.sup.2 and an acceleration voltage of 60 to 100 keV. A periodic table group 15 element, typically phosphorus (P) or arsenic (As) is used as the impurity element which imparts n-type conductivity, and phosphorus (P) is used here. The conductive layers 417 to 420 become masks with respect to the n-type conductivity imparting impurity element in this case, and first impurity regions 423 to 426 are formed in a self-aligning manner. The impurity element which imparts n-type conductivity is added to the first impurity regions 423 to 426 with a concentration in the range of 1×10.sup.20 to 1×10.sup.21 atoms/cm.sup.3. (FIG. 21B)

(66) Second etching treatment is then conducted as shown in FIG. 21C. In this etching treatment, ICP etching is employed, a reaction gas is introduced to chambers, and plasma is generated by giving RF (13.56 MHz) power of 500 W to a coiled electrode at a pressure of 1 Pa. RF (13.56 MHz) power of 50 W is also given to the substrate side (sample stage) so that a self-bias voltage lower than that of the first etching treatment can be applied. The W film is subjected to anisotropic etching and the second shape conductive films 427 to 432 are obtained.

(67) A second doping process is then performed, as shown in FIG. 21C. The dose amount is smaller than that of the first doping process in this case, and an impurity element which imparts n-type conductivity is doped under high acceleration voltage conditions. For example, doping performed with the acceleration voltage set from 70 to 120 keV, and a dose amount of 1×10.sup.13 atoms/cm.sup.3, and a new impurity region is formed inside the first impurity region is formed inside the first impurity region formed in the island shape semiconductor layers of FIG. 21B. The second conductive layers 427 to 433 are used as masks with respect to the impurity element, and doping is performed so as to also add the impurity element into regions under the first conductive layers 427a to 433a. The second impurity regions 433 to 437, which is overlapped with the first conductive layer 427a to 430a is formed. The impurity elements which imparts an n-type conductivity is made its concentration range of 1×10.sup.17 to 1×10.sup.18 atoms/cm.sup.3 in the second impurity region.

(68) By etching the gate insulating film 416, TaN which is the first conductive layer is backward by the etching simultaneously, so that there are formed third conductive layers 438 through 443 (first conductive layers 438a to 443a and second conductive layers 438b to 443b). Reference numeral 444 denotes a gate insulating film, and regions not covered by the third shape conductive layers 438 to 443 are additionally etched on the order of 20 to 50 nm, forming thinner regions.

(69) By the third etching, there are formed third impurity regions 445 to 449 overlapping the first conductive layers 438a to 441a and the forth impurity regions 450 to 454 at the external of the third impurity region as shown in FIG. 22A. Thus, the concentration of the impurity elements imparting an n-type conductivity in the third impurity region and the forth impurity region is as same as that in the second impurity region.

(70) Fourth impurity regions 458 to 461 added with an impurity element having a conductivity type which is the opposite of a conductivity type impurity element, are then formed as shown in FIG. 22B in the island shape semiconductor layers 403, 406 which form p-channel TFTs. The third shaped conductive layers 439, 441 is used as a mask with respect to the impurity element, and the impurity regions are formed in a self-aligning manner. The island shape semiconductor films 402, 404, 405 which form n-channel TFTs, are covered over their entire surface areas by resist masks 455 to 457. Phosphorus is added to the impurity regions 458 to 461 at a different concentration, and ion doping is performed here using diborane (B.sub.2H.sub.6), so that the respective impurity regions have the impurity concentration of 2×10.sup.20 to 2×10.sup.21 atoms/cm.sup.3.

(71) Impurity regions are formed in the respective island shape semiconductor layers by the above processes. The conductive layers (the conductive layers forming the gate electrode) 438 to 441 overlapping the island shape semiconductor layers function as gate electrodes. The reference numeral 442 functions as a source wiring and 443 functions as a wiring in the driver circuit.

(72) A process of activating the impurity elements added to the respective island shape semiconductor layers is then performed with the aim of controlling conductivity type as shown in FIG. 22C. Thermal annealing using an annealing furnace is performed for this process. In addition, laser annealing and rapid thermal annealing (RTA) can also be applied Thermal annealing is performed with an oxygen concentration equal to or less than 1 ppm, preferably equal to or less than 0.1 ppm, in a nitrogen atmosphere at 400 to 700° C., typically between 500 and 600° C. Heat treatment is performed for 4 hours at 500° C. in Embodiment 1. However, for cases in which the wiring material used in the third conductive layers 438 to 443 is weak with respect to heat, it is preferable to perform activation after forming an interlayer insulating film (having silicon as its main constituent) in order to protect the wirings and the like.

(73) In addition, heat treatment is performed for 1 to 12 hours at 300 to 450° C. in an atmosphere containing between 3 and 100% hydrogen, performing hydrogenation of the island shape semiconductor layers. This process is one of terminating dangling bonds in the island shape semiconductor layers by hydrogen which is thermally excited. Plasma hydrogenation (using hydrogen excited by a plasma) may also be performed as another means of hydrogenation.

(74) A first interlayer insulating film 472 is then formed from a silicon oxynitride film having a thickness of 100 to 200 nm, as shown in FIG. 23. An acrylic resin film or a polyimide resin film is then formed with a thickness of 1.8 μm on the first interlayer insulating film 472 as a second interlayer insulating film 473. An etching process is performed next in order to form contact holes.

(75) A conductive metallic film is then formed by sputtering or vacuum evaporation. A Ti film having a thickness of 50 to 150 μm is formed, contacts with the semiconductor layers forming source regions or drain regions of the island shape semiconductor films, an aluminum (Al) film is formed having a thickness of 300 to 400 nm on the Ti film, and in addition, a Ti film or a titanium nitride (TiN) film is formed having a thickness of 100 to 200 nm, resulting in a three layer structure.

(76) Source wirings 474 to 476 for forming contacts with the source regions of the island shape semiconductor film in the driver circuit portion, and drain wirings 477 to 479 for forming contacts with the drain regions, are then formed.

(77) Further, a connection electrode 480, a gate wiring 481, a drain electrode 482, and an electrode 492 are formed in the pixel portion.

(78) The connection electrode 480 electrically connects a source wiring 483 and a first semiconductor film 484. Although not shown in the figures, the gate wiring 481 is electrically connected to a conductive layer 485 forming a gate electrode, through a contact hole. The drain electrode 482 is electrically connected to a drain region of the first semiconductor film 484. The electrode 492 is electrically connected to a second semiconductor film 493, and the second semiconductor layer 493 functions as an electrode of a storage capacitor 505.

(79) Next, as shown in FIG. 24, a photolithography process is performed using a photosensitive resin film, and a convex portion 600 is formed having a thickness of 0.32 μm on the source wiring 483. As a photosensitive resin film, a material in which JSR Corporation product BPR-107VL is diluted by PGNEA (propylene glycol monomethyl ether acetate), reducing its viscosity, is used. In the upper surface diagram of the pixel portion, flat convex portion is patterned into a thin, long rectangular shape and the width of its minor axis is set to 4.0 μm.

(80) A transparent conductive film is then formed over the entire surface, as shown in FIG. 23 and FIG. 24, and a pixel electrode 491 is formed by a patterning process and an etching process using a photomask. The pixel electrode 491 is formed on the second interlayer insulating film 473, and portions overlapping with the drain electrode 482 and the electrode 492 of the pixel 11.1 are formed, forming a connective structure. The width of a first region 601 of the pixel electrode 491 formed in the upper edge portion of the convex portion is set to be 1.0 μm.

(81) The transparent conductive film can be formed by a method such as sputtering or vacuum evaporation using a material such as indium oxide (In.sub.2O.sub.3), or an alloy of indium oxide and tin oxide (In.sub.2O.sub.3—SnO.sub.2; ITO). The etching process for this type of material may be performed by a hydrochloric acid solution. However, residue easily develops with etching of ITO in particular, and therefore an alloy of indium oxide and zinc oxide (In.sub.2O.sub.3—ZnO) may also be used in order to improve the etching workability. The indium oxide and zinc oxide alloy has superior surface smoothness, and is also superior to ITO in its thermal stability, and therefore a corrosive reaction with AL contacting at the edge surfaces of the drain electrode 482 can be prevented. Similarly, zinc oxide (ZnO) is also a suitable material, and in addition, a material such as zinc oxide to which gallium (Ga) is added (ZnO:Ga) in order to increase the optical light transmittivity and the conductivity can also be used.

(82) An active matrix substrate corresponding to a transmission type liquid crystal display device can thus be completed.

(83) A driver circuit portion having an n-channel TFT 501, a p-channel TFT 502, and an n-channel TFT 503, and a pixel portion having a pixel TFT 504 and a storage capacitor 505 can thus be formed on the same substrate. This type of substrate is referred to as an active matrix substrate in this specification, for convenience. (See FIG. 23.)

(84) The n-channel 501 of the driver circuit portion has the channel forming region 462, the third impurity region 445 (GOLD region) overlapping with the conductive layer 438 forming a gate electrode, the fourth impurity region 450 (LDD region) formed on the outside of the gate electrode, and the first impurity region 423 which functions as a source region or a drain region. The p-channel 502 has the channel forming region 463, the fifth impurity region 446 overlapping with the conductive layer 439 forming a gate electrode, and the sixth impurity region 451 which functions as a source region or a drain region. The n-channel TFT 503 has the channel forming region 464, the third impurity region 447 (GOLD region) which overlaps with the conductive layer 440 forming a gate electrode, the fourth impurity region 452 (LDD region) formed on the outside of the gate electrode, and the first impurity region 425 which functions as a source region or a drain region.

(85) The pixel TFT 504 of the pixel portion has the channel forming region 465, the third impurity region 448 (GOLD region) which overlaps with the conductive layer 485 forming a gate electrode, the fourth impurity region 453 (LDD region) formed on the outside of the gate electrode, and the first impurity region 426 which functions as source region or a drain region. Further, an impurity element imparting p-type conductivity is added to the semiconductor film 493, which functions as one electrode of the storage capacitor 505. The storage capacitor is formed by the semiconductor layer 485, which forms the gate electrode, and an insulating layer (the same layer as the gate insulating film) formed therebetween.

(86) Cross sections in which the upper surface diagram of FIG. 25 is cut along the dashed line A-A′ and the dashed line B-B′ correspond to the cross sections in which FIG. 23 is cut along the dashed line A-A′ and the dashed line B-B′. A cross section in which the upper surface diagram of FIG. 25 is cut along the dashed line C-C′ corresponds to the cross section in which FIG. 24 is cut along the dashed line C-C′. Reference numerals 801 to 805 of FIG. 25 denote contact holes.

(87) The convex portion formed on the source line in the upper surface diagram of FIG. 25 is made into a rectangular island shape. However, it is also possible to use a stripe shape in which the pixel portions of adjacent pixels are mutually connected.

(88) [Embodiment 2]

(89) A portion of the method of manufacturing the active matrix substrate manufactured by Embodiment 1 can be applied to a reflection type liquid crystal display device.

(90) Processing is first performed in accordance with FIGS. 21A to 22C of Embodiment 1.

(91) The first interlayer insulating film 472 is then formed from a silicon oxynitride film having a thickness of 100 to 200 nm, as shown in FIG. 27. An acrylic resin film or a polyimide film is then formed with a thickness of 1.8 μm on the first interlayer insulating film 472 as the second interlayer insulating film 473. An etching process is performed next in order to form contact holes.

(92) Next, as shown in FIG. 28, a photolithography process is performed using a photosensitive resin film, and the convex portion 600 is formed having a thickness of 0.32 μm on the source wiring 483. A material in which JSR Corporation product BPR-107VL is diluted by PGMEA (propylene glycol monomethyl ether acetate), reducing its viscosity, is used.

(93) A conductive metallic film is then formed by sputtering or vacuum evaporation, as shown in FIGS. 27 and 28. A Ti film having a thickness of 50 to 150 μm is formed, contacts with the semiconductor layers forming source regions or drain regions of the island shape semiconductor films, an aluminum (Al) film is formed to have a thickness of 300 to 400 nm on the Ti film, and in addition, a Ti film or a titanium nitride (TiN) film is formed to have a thickness of 100 to 200 nm, resulting in a three layer structure.

(94) The source wirings 474 to 476 for forming contacts with the source regions of the island shape semiconductor film in the driver circuit portion, and the drain wirings 477 to 479 for forming contacts with the drain regions, are then formed.

(95) Further, the connection electrode 480, the gate wiring 481, and the drain electrode 482 are formed in the pixel portion. The drain electrode 482 has a function as a pixel electrode of the reflecting liquid crystal display device in Embodiment 2. Note that, as shown in FIG. 28, the upper edge portion of the convex portion and the drain electrode 482 mutually overlap. The width of a first region 602 of the drain electrode is set to 1.5 μm.

(96) The connection electrode 480 electrically connects the source wiring 483 and the first semiconductor film 484. Although not shown in the figures, the gate wiring 481 electrically connects to the conductive layer 485 forming a gate electrode, through a contact hole. The drain electrode 482 electrically connects to a drain region of the first semiconductor film 484. In addition, the drain electrode 482 is electrically connected to the first semiconductor film 493, and the second semiconductor film 493 functions as an electrode of the storage capacitor 505.

(97) The second semiconductor films 493 formed in each pixel, and the conductive layers 485 forming the gate electrodes are made into electrodes of the storage capacitor. The gate insulating film 444 functions as a dielectric film of the storage capacitor. The second semiconductor film 493 becomes the same electric potential as the drain electrode 482. The semiconductor layer 485 becomes the same electric potential as the gate wiring.

(98) An active matrix substrate corresponding to a reflection type liquid crystal display device can thus be completed.

(99) A driver circuit portion having the n-channel TFT 501, the p-channel TFT 502, and the n-channel TFT 503, and a pixel portion having the pixel TFT 504 and the storage capacitor 505 can thus be formed on the same substrate. This type of substrate is referred to as an active matrix substrate within this specification, for convenience.

(100) The n-channel TFT 501 of the driver circuit portion has the channel forming region 462, the third impurity region 445 (GOLD region) overlapping with the conductive layer 438 forming a gate electrode, the fourth impurity region 450 (LDD region) formed on the outside of the gate electrode, and the first impurity region 423 which functions as a source region or a drain region. The p-channel TFT 502 has the channel forming region 463, the fifth impurity region 446 overlapping with the conductive layer 439 forming a gate electrode, and the sixth impurity region 451 which functions as a source region or a drain region. The n-channel TFT 503 has the channel forming region 464, the third impurity region 447 (GOLD region) which overlaps with the conductive layer 440 forming a gate electrode, the fourth impurity region 452 (LDD region) formed on the outside of the gate electrode, and the first impurity region 425 which functions as a source region or a drain region.

(101) The pixel TFT 504 of the pixel portion has the channel forming region 465, the third impurity region 448 (GOLD region) which overlaps with the conductive layer 485 forming a gate electrode, the fourth impurity region 453 (LDD region) formed on the outside of the gate electrode, and the first impurity region 426 which functions as sweet area source region or a drain region. Further, an impurity element imparting p-type conductivity is added to the semiconductor film 493, which functions as one electrode of the storage capacitor 505. The storage capacitor is formed by the semiconductor layer 485, which forms the gate electrode, and an insulating layer (the same layer as the gate insulating film) formed in between.

(102) Cross sections taken along the dashed line D-D′ and the dashed line E-E′ in a top view of FIG. 29 correspond to the cross sections taken along the dashed line D-D′ and the dashed line E-E′ in FIG. 27, respectively. A cross section taken along the dashed line F-F′ in the top view of FIG. 29 corresponds to the cross section in which FIG. 28 is cut along the dashed line F-F.

(103) [Embodiment 3]

(104) In this embodiment, the manufacturing process of an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 is described below. FIG. 26 is used for explanation.

(105) First, in accordance with Embodiment 1, the active matrix substrate is obtained. FIG. 26 shows a cross-sectional view taken along the line A-N and C-C′ of the pixel portion of the active matrix substrate shown in FIG. 25. In an active matrix substrate, the driver circuit portion 506 and the pixel portion 507 are formed.

(106) First, an orientation film 512 is formed on the active matrix substrate, and is subjected to a rubbing process. Note that, in this embodiment, before the formation of the orientation film 512, a columnar spacer for maintaining a gap between the substrates is formed at a desired position by patterning an organic resin film such as an acrylic resin film. The columnar spacer having 4.0 μm height is used in this embodiment. Further, spherical spacers may be scattered on the entire surface of the substrate in place of the columnar spacer.

(107) Next, an opposing substrate 508 is prepared. On the opposing substrate 508, there are formed a colored layers, a light shielding layer and color filters arranged to correspond to the respective pixels. Further, the driver circuit portion is also provided with a light-shielding layer. A leveling film is provided to cover the color filters and the light-shielding layer. Next, in the pixel portion an opposing electrode 510 is formed from a transparent conductive film on the leveling film, an orientation film 511 is formed on the entire surface of the opposing substrate, and a rubbing process is conducted thereon.

(108) Then, the active matrix substrate on which a pixel portion and a driver circuit are formed is stuck with the opposing substrate by a sealing agent 513. A filler is mixed in the sealing agent 513, and the two substrates are stuck with each other while keeping a uniform gap by this filler and the columnar spacer. Thereafter, a liquid crystal material 514 is injected between both the substrates to encapsulate the substrates completely by an encapsulant (not shown). A known liquid crystal material may be used as the liquid crystal material 514. Thus, the active matrix liquid crystal display device shown in FIG. 26 is completed. Then, if necessary, the active matrix substrate and the opposing substrate are parted into desired shapes. In addition, by using a known technique, a phase difference plate, a polarizing plate or the like may be suitably provided. Then, an FPC is stuck with the substrate using a known technique.

(109) Thus, the liquid crystal display panel manufactured according to above-mentioned steps can be used as a display portion of various electronic devices.

(110) This embodiment can be combined with Embodiment 2.

(111) In this embodiment, the edge of pixel electrode 491 is formed overlapping with a convex portion 600 which have 0.32 μm height. The height of the convex portion becomes 8% of the cell gap because the height of the cell gap is 4.0 μm. It is understood that the height of the convex portion has an effect to decrease disclination and light leakage by a graphic chart of FIG. 9 and FIG. 36.

(112) [Embodiment 4]

(113) The liquid crystal display device formed by implementing an embodiment among above-mentioned Embodiments 1 to 3 can be applied to various electro-optical equipments. Thus the present invention can be applied to all of the electronic equipments having these electro-optical devices as the display portion.

(114) The following can be given as examples of the electronic equipment: video cameras; digital cameras; projectors; head mounted displays (goggle type display); car navigation systems; car stereo; personal computers; portable information terminals (such as mobile computers, portable telephones and electronic notebook). An example of these is shown in FIGS. 30, 31 and 32.

(115) FIG. 30A shows a personal computer, and it includes a main body 2001, an image input section 2002, a display portion 2003, and a keyboard 2004. The present invention is applicable to the display portion 2003.

(116) FIG. 30B shows a video camera, and it includes a main body 2101, a display portion 2102, a voice input section 2103, operation switches 2104, a battery 2105, and an image receiving section 2106. The present invention is applicable to the display portion 2102.

(117) FIG. 30C shows a mobile computer, and it includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display portion 2205. The present invention is applicable to the display portion 2205.

(118) FIG. 30D shows a goggle type display, and it includes a main body 2301; a display portion 2302; and an arm section 2303. The present invention is applicable to the display portion 2302.

(119) FIG. 30E shows a player using a recording medium which records a program (hereinafter referred to as a recording medium), and it includes a main body 2401; a display portion 2402; a speaker section 2403; a recording medium 2404; and operation switches 2405. This player uses DVD (digital versatile disc), CD, etc. for the recording medium, and can be used for music appreciation, film appreciation, games and Internet. The present invention is applicable to the display portion 2402.

(120) FIG. 30F shows a digital camera, and it includes a main body 2501; a display portion 2502; a view finder 2503; operation switches 2504; and an image receiving section (not shown in the figure). The present invention can be applied to the display portion 2502.

(121) FIG. 31A is a front-type projector, and it includes a projection device 2601 and a screen 2602. The present invention is applicable to a liquid crystal display device 2808 which comprises one of the projection device 2601.

(122) FIG. 31B is a rear-type projector, and it includes a main body 2701, a projection device 2702, a mirror 2703, and a screen 2704. The present invention is applicable to a liquid crystal display device 2808 which comprises one of the projection device 2702.

(123) FIG. 31C is a diagram showing an example of the structure of the projection devices 2601, 2702 in FIGS. 31A and 31B. The projection device 2601 or 2702 comprises a light source optical system 2801, mirrors 2802, 2804 to 2806, dichroic mirrors 2803, a prism 2807, liquid crystal display devices 2808, phase difference plates 2809, and a projection optical system 2810. The projection optical system 2810 is composed of an optical system including a projection lens. This example shows an example of three-plate type but not particularly limited thereto. For instance, the invention may be applied also to a single plate type optical system. Further, in the light path indicated by an arrow in FIG. 31C, an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, and an IR film may be suitably provided by a person who carries out the invention.

(124) FIG. 31D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 31C. In this embodiment, the light source optical system 2801 comprises a reflector 2811, a light source 2812, lens arrays 2813, 2814, a polarization conversion element 2815, and a condenser lens 2816. The light source optical system shown in FIG. 31D is merely an example, and is not particularly limited to the illustrated structure For example, a person who carries out the invention is allowed to suitably add to the light source optical system an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, and an IR film.

(125) Note that a transmission electro-optical device is used as the projector shown in FIG. 31, a reflection type electro-optical device is not illustrated.

(126) FIG. 32A is a portable telephone, and it includes a main body 2901, an audio output section 2902, an audio input section 2903, a display portion 2904, operation switches 2905, and an antenna 2906. The present invention can be applied to the display portion 2904.

(127) FIG. 32B is a portable book (electronic book), and it includes a main body 3001, display portions 3002 and 3003, a recording medium 3004, operation switches 3005, and an antenna 3006. The present invention can be applied to the display portions 3002 and 3003.

(128) FIG. 32C is a display, and it includes a main body 3101, a support stand 3102, and a display portion 3103. The present invention can be applied to the display portion 3103. The display of the present invention is advantageous for a large size screen in particular, and is advantageous for a display equal to or greater than 10 inches (especially equal to or greater than 30 inches) in diagonal.

(129) The applicable range of the present invention is thus extremely wide, and it is possible to apply the present invention to electronic equipment in all fields. Further, the electronic equipment of Embodiment 4 can be realized by using a constitution of any combination of Embodiments 1 to 3.

(130) Orientation irregularities of liquid crystals, in which there is disclination and light leakage of a liquid crystal display device when displaying a black level, can thus be reduced in accordance with the present invention, and a liquid crystal display device having high contrast and good visibility can be provided.