Silicon carbide semiconductor device and fabrication method of silicon carbide semiconductor device

Abstract

A P.sup.+ type region, a p-type region, and a P.sup.− type region are disposed in a surface layer of a silicon carbide substrate base and are disposed in a breakdown voltage structure portion surrounding an active region to make up an element structure of Schottky junction. The p.sup.− type region surrounds the P.sup.+ type region and the p-type region to form a junction termination structure. A Schottky electrode forms a Schottky junction with an n-type silicon carbide epitaxial layer. The Schottky electrode and an electrode pad have end portions positioned on the P.sup.+ type region and the end portion of the Schottky electrode is exposed from the end portion of the electrode pad. As a result, the region of the breakdown voltage structure portion can be made smaller while the active region can be made larger, and a semiconductor device is easily fabricated.

Claims

1. A silicon carbide semiconductor device comprising: a first-conductivity-type wide band gap semiconductor substrate; a first-conductivity-type wide band gap semiconductor deposition layer deposited on a surface of the first-conductivity-type wide band gap semiconductor substrate and having an impurity concentration that is lower than that of the first-conductivity-type wide band gap semiconductor substrate; an element structure configured by a first metal film that forms a Schottky junction with the first-conductivity-type wide band gap semiconductor deposition layer; a second metal film for an electrode formed on the first metal film; a first second-conductivity-type semiconductor region having its width of about 5 μm and selectively disposed in a surface layer of the first-conductivity-type wide band gap semiconductor deposition layer on a side opposite to the first-conductivity-type wide band gap semiconductor substrate, to surround a peripheral portion of the element structure; a second second-conductivity-type semiconductor region surrounding a peripheral portion of the first second-conductivity-type semiconductor region, to make up a junction termination structure; and an insulation film that covers at least the second second-conductivity-type semiconductor region, and is disposed from a side of the second second-conductivity-type semiconductor region to a portion of a surface of the first second-conductivity-type semiconductor region, wherein end portions of the first metal film and the second metal film are positioned on the first second-conductivity-type semiconductor region and within the width of about 5 μm of the first second-conductivity-type semiconductor region, with the end portion of the first metal film exposed on the insulation film, and the end portion of the second metal film is positioned closer to the element structure as compared to the end portion of the first metal film.

2. A fabrication method of a silicon carbide semiconductor device, the fabrication method comprising: depositing on a surface of a first-conductivity-type wide band gap semiconductor substrate, a first-conductivity-type wide band gap semiconductor deposition layer having an impurity concentration that is lower than that of the first-conductivity-type wide band gap semiconductor substrate; forming an element structure by forming a first metal film that forms a Schottky junction with the first-conductivity-type wide band gap semiconductor deposition layer; forming a second metal film for an electrode on the first metal film; selectively forming a first second-conductivity-type semiconductor region having its width of about 5 μm and in a surface layer of the first-conductivity-type wide band gap semiconductor deposition layer, to surround a peripheral portion of the element structure; selectively forming in a surface layer of the first-conductivity-type wide band gap semiconductor deposition layer, a second second-conductivity-type semiconductor region having an impurity concentration that is lower than that of the first second-conductivity-type semiconductor region, the second second-conductivity-type semiconductor region formed to surround a peripheral portion of the first second-conductivity-type semiconductor region and form a junction termination structure; forming an insulation film to cover at least the second second-conductivity-type semiconductor region, wherein the insulation film is formed from a side of the second second-conductivity-type semiconductor region to a portion of a surface of the first second-conductivity-type semiconductor region, end portions of the first metal film and the second metal film are positioned on the first second-conductivity-type semiconductor region and within the width of about 5 μm of the first second-conductivity-type semiconductor region, with the end portion of the first metal film exposed on the insulation film, and the end portion of the second metal film is positioned closer to the element structure as compared to the end portion of the first metal film.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device according to an embodiment; and

(2) FIG. 2 is a cross-sectional view of a Schottky barrier diode (SBD) of a conventional technique.

BEST MODE(S) FOR CARRYING OUT THE INVENTION

(3) Preferred embodiments of a silicon carbide semiconductor device and a fabrication method of a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In this description and the accompanying drawings, layers and regions prefixed with n or p mean that majority carriers are electrons or holes, respectively. Additionally, + and − added to n or p mean that the impurity concentration is higher and lower, respectively, than layers and regions without + and −.

(4) (Embodiment)

(5) A semiconductor device according to the present invention is formed by using a wide band gap semiconductor. In an embodiment, a silicon carbide semiconductor device produced by using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described by taking a diode in a Schottky junction (Schottky) structure as an example. FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device according to the embodiment. As depicted in FIG. 1, the silicon carbide semiconductor device according to the embodiment has an n-type silicon carbide epitaxial layer (wide band gap semiconductor deposition layer) 2 disposed on a principal plane of an n.sup.+type silicon carbide substrate (wide band gap semiconductor substrate) 1.

(6) The n.sup.+ type silicon carbide substrate 1 is a silicon carbide monocrystalline substrate doped with nitrogen (N), for example. The n-type silicon carbide epitaxial layer 2 is a low-concentration n-type drift layer doped with, for example, nitrogen, at an impurity concentration that is lower than the n.sup.+ type silicon carbide substrate 1. In the following description, a silicon carbide semiconductor base refers to the n.sup.+ type silicon carbide substrate 1 alone, or refers to the n.sup.+ type silicon carbide substrate 1 and the n-type silicon carbide epitaxial layer 2, collectively. In a surface layer of the n-type silicon carbide epitaxial layer 2 on the side opposite to the n.sup.+ type silicon carbide substrate 1 (on the front surface side of the silicon carbide semiconductor base), a ring-shaped P.sup.+ type region 3 is disposed, and a p-type region 4 and a p.sup.− type region 5 are disposed in this order on the outer periphery of the P.sup.+ type region 3.

(7) The p.sup.+ type region 3 (first second-conductivity-type semiconductor region) is disposed in a breakdown voltage structure portion (edge portion) disposed in a peripheral portion of the active region to surround an active region. The breakdown voltage structure portion is a region retaining a breakdown voltage. The p.sup.+ type region 3 is disposed closer to the active region provided with a diode element structure and is in contact with a Schottky electrode 7 forming the Schottky junction with the n-type silicon carbide epitaxial layer 2. The Schottky electrode 7 will be described later.

(8) The p.sup.+ type region 3 is doped with, for example, aluminum (Al) at a high impurity concentration. The p.sup.+ type region 3 has a function of avoiding electric field concentration on an end portion of junction between the n-type silicon carbide epitaxial layer 2 and the Schottky electrode 7. The p-type region 4 and the p.sup.− type region 5 make up a junction termination extension (JTE) structure further dispersing an electric field in the peripheral portion of the active region. The p-type region 4 and the p.sup.−type region 5 are respectively doped with aluminum, for example.

(9) Although not depicted, multiple p.sup.+ type regions (second-conductivity-type semiconductor regions) may be disposed in the active region at predetermined intervals to make up an element structure of a junction barrier Schottky structure (JBS structure). The p.sup.+ type regions are disposed separately from the p.sup.+ type region 3.

(10) An interlayer insulation film 6 is disposed on the breakdown voltage structure portion to cover the P.sup.+ type region 3, the p-type region 4, and the p.sup.− type region 5. The Schottky electrode 7 making up an anode electrode is disposed on a surface of the n-type silicon carbide epitaxial layer 2 on the side opposite to the n.sup.+ type silicon carbide substrate 1 (on the front surface of the silicon carbide semiconductor base). The Schottky electrode 7 is disposed across the active region and a portion of the breakdown voltage structure portion.

(11) A back surface electrode (ohmic electrode) 10 forming ohmic junction with the n.sup.+ type silicon carbide substrate 1 is disposed on a surface of the n.sup.+ type silicon carbide substrate 1 on the side opposite to the n-type silicon carbide epitaxial layer 2 (on the back surface of the silicon carbide semiconductor base). The back surface electrode 10 makes up a cathode electrode.

(12) For example, the Schottky electrode 7 covers the entire surface of the n-type silicon carbide epitaxial layer 2 (the front surface of the silicon carbide semiconductor base) exposed in the active region and comes into contact with the p.sup.+ type region 3 in the peripheral portion of the active region. The Schottky electrode 7 is disposed to extend from the active region to the breakdown voltage structure portion and overhangs the interlayer insulation film 6. The Schottky electrode 7 covers the p.sup.+ type region 3 via the interlayer insulation film 6. Therefore, an end portion 7a of the Schottky electrode 7 most extended into the breakdown voltage structure portion is terminated on the p.sup.+ type region 3 for the JTE structure.

(13) The Schottky electrode 7 is preferably made of the following materials because the effects of the present invention notably appear. The Schottky electrode 7 is preferably made of a group IVa metal, group Va metal, group VIa metal, aluminum, or silicon. Alternatively, the Schottky electrode 7 is preferably made of a composite film having two or three elements of the group IVa metal, group Va metal, group VIa metal, aluminum, and silicon. Particularly, the Schottky electrode 7 is made of titanium (Ti), aluminum, or silicon, or is preferably a composite film having two or three elements among titanium, aluminum, and silicon. More preferably, in the Schottky electrode 7, a portion forming the Schottky junction with the n-type silicon carbide epitaxial layer 2 is made of titanium (Ti), for example.

(14) If the silicon carbide semiconductor device according to the embodiment is used as a high-voltage semiconductor device, the Schottky barrier height of the Schottky electrode 7 and the n-type silicon carbide epitaxial layer 2 is preferably greater than or equal to 1 eV, for example. If the silicon carbide semiconductor device according to the embodiment is used as a power source device, the Schottky barrier height of the Schottky electrode 7 is preferably greater than or equal to 0.5 eV and less than 1 eV, for example.

(15) For example, an electrode pad 8 made of aluminum is disposed on the Schottky electrode 7. The electrode pad 8 is extended from the active region to the breakdown voltage structure portion, and an end portion 8a thereof most extended into the breakdown voltage structure portion is terminated on the Schottky electrode 7. The end portion 8a is positioned closer to the active region as compared to the end portion 7a of the Schottky electrode 7. Therefore, the end portion 7a of the Schottky electrode 7 is located outside with respect to the end portion 8a of the electrode pad 8 so that a portion thereof is exposed.

(16) A protection film 9 such as a passivation film made of, for example, polyimide, is disposed on the JTE structure to cover the end portions of the Schottky electrode 7 and the electrode pad 8 most extended into the breakdown voltage structure portion. The protection film 9 has a function of discharge prevention.

(17) The Schottky electrode 7 and the electrode pad 8 of the configuration described above are fabricated according to the procedure of the following steps 1 to 6: 1. deposition of Ti by sputtering; 2. resist patterning through resist application and photolithography; 3. wet etching of Ti with ammonia hydrogen peroxide water to form the Schottky electrode 7; 4. deposition of Al—Si by sputtering; 5. resist patterning through resist application and photolithography; and 6. wet etching of Al—Si with phosphoric/nitric/acetic-acid mixture liquid to cover the Schottky electrode 7. In this case, Ti is not wet-etched by the mixture liquid. Subsequently, to remove remaining Si (called nodules), dry etching (particle etching) is performed by using carbon tetrafluoride and oxygen as source gas to form the electrode pad 8.

(18) The Schottky electrode 7 is about 0.2 μm thick and, according to the fabrication method, when the exposed Schottky electrode 7 is wet-etched, a side-etching amount (etching amount in the width direction) relative to the end portion 7a is as small as 0.5 to 1 μm. Therefore, the width of the p.sup.+ type region 3 can be reduced to about 5 μm. As described above, even if the width of the p.sup.+ type region 3 is reduced, the end portion 7a of the Schottky electrode 7 can be positioned within the p.sup.+ type region 3.

(19) According to the configuration, since the width of the p.sup.+ type region 3 can be made smaller, the size (width) of the breakdown voltage structure portion (edge portion) can be made smaller and the size (width) of the active region can be made relatively larger. For example, although the p.sup.+ type region 3 conventionally requires a width of 20 μm, the width can be set to 5 μm in this embodiment.

(20) This difference of 15 μm is generated at one end portion of the active region of FIG. 1, and the width of the active region can be increased by a total of 30 μm, including the other end portion. For example, assuming that an area of the active region is 1 mm.sup.2 in the conventional case, the area can be 1.06 mm.sup.2 in this embodiment. As described above, since the active region can be made larger, current capacity can be increased and positive bias V.sub.F (V) can be reduced. Since the breakdown voltage structure portion has a smaller width, the die size is not increased.

(21) As described above, according to the embodiment, both the Schottky electrode and the electrode pad can be positioned on the p.sup.+ type region for the JTE structure. Particularly, since the electrode pad having a predetermined thickness is disposed inside (closer to the active region) with respect to the Schottky electrode and the end portion of the Schottky electrode is exposed from the end portion of the electrode pad, the semiconductor device is easily fabricated. With regard to etching of the end portion of the Schottky electrode, since the Schottky electrode itself is thin, even if the p.sup.+ type region has a narrower width, the end portion of the Schottky electrode can be positioned easily within the p.sup.+ type region and the semiconductor device is easily fabricated.

(22) The present invention is not limited to the diode element structure described in the embodiment and the same effect can be acquired even from a MOSFET element structure.

INDUSTRIAL APPLICABILITY

(23) As described above, the silicon carbide semiconductor device and the fabrication method of a silicon carbide semiconductor device according to the present invention are useful for a high-voltage semiconductor device used in power conversion equipment and power source devices of various industrial machines.

EXPLANATIONS OF LETTERS OR NUMERALS

(24) 1 n.sup.+ type silicon carbide substrate

(25) 2 n-type silicon carbide epitaxial layer

(26) 3 p.sup.+ type region

(27) 4 p-type region

(28) 5 p.sup.− type region

(29) 6 interlayer insulation film

(30) 7 Schottky electrode

(31) 7a end portion of Schottky electrode

(32) 8 electrode pad

(33) 8a end portion of electrode pad

(34) 9 protection film

(35) 10 back surface electrode