Gate driver, display apparatus and gate driving method of outputting a multi-pulse waveform

Abstract

The present disclosure discloses a gate driver, a display apparatus and a gate driving method, to achieve a function of outputting a multi-pulse waveform by the gate driver. The gate driver according to the present disclosure comprises multiple groups of driving units, each group of driving units comprising N driving units each of which comprises a shift register and a logic circuit, wherein N is an integer larger than 1, and an output of a shift register is connected to a logic circuit in each driving unit. The shift registers multiplex multiple clock signals with different timings. Each of the shift registers outputs an output signal to a corresponding logic circuit. A part of a clock signal is selected by the logic circuit for output. In this way, a function of outputting a multi-pulse waveform by the gate driver is achieved, which prepares for a shift register having a function of threshold voltage compensation, to make a shift register capable of multi-row scanning become feasible on a display panel.

Claims

1. A gate driver, comprising: multiple groups of driving units, each group of driving units comprising N driving units each of which comprises a shift register and a logic circuit, wherein N is an integer larger than 1, and an output of the shift register is connected to the logic circuit in each driving unit, wherein an output of a logic circuit in an m.sup.th driving unit is connected to a gate scan line of an m.sup.th row of pixels, and is connected to an input for a trigger signal of a shift register in an m+1.sup.th driving unit, wherein m is in a range of [1, M−1], and M is a total number of rows of pixels; an output of a logic circuit in a k.sup.th driving unit is connected to a reset of a k−(N−1).sup.th of a shift register, wherein k is in a range of [N, M]; and all logic circuits in the multiple groups of driving units use a common logic circuit clock signal; wherein the logic circuit clock signal has a pulse width equal to a first pulse width and a pulse period equal to a first pulse period; and wherein in each group of driving units, shift registers in various driving units multiplex N shift register clock signals with different timings, wherein each of the N shift register clock signals has a pulse width equal to a second pulse width and a pulse period equal to a second pulse period, wherein the second pulse width is larger than the first pulse width, and the second pulse period is larger than the first pulse period.

2. The gate driver according to claim 1, wherein logic circuits in various driving units output output signals with different timings which have multiple pulses respectively, each of the multiple pulses having a pulse width equal to that of the logic circuit clock signal.

3. The gate driver according to claim 1, wherein a logic circuit in the m.sup.th driving unit comprises a first thin film transistor, a second thin film transistor, and an inverter connected between a gate of the first thin film transistor and a gate of the second thin film transistor, wherein a drain of the first thin film transistor is connected to a drain of the second thin film transistor, and acts as an output of the logic circuit; a source of the first thin film transistor acts as an input for the logic circuit clock signal; the gate of the first thin film transistor acts as an input connected to an output of a shift register in an m.sup.th driving unit; and a source of the second thin film transistor acts as an input for a low level signal.

4. The gate driver according to claim 1, wherein the second pulse width is 2*(N−1) times the first pulse width, and the second pulse period is N times the first pulse period, and in each group of driving units, a timing of an n+1.sup.th shift register clock signal is the first pulse period later than an n.sup.th shift register clock signal; and a logic circuit in each driving unit outputs an output signal having N−1 pulses with a pulse width equal to the first pulse width, and a timing of an output signal of a logic circuit in an n+1.sup.th driving unit is the first pulse period later than that of an output signal of a logic circuit in an n.sup.th driving unit, wherein n is in a range of [1, N−1].

5. The gate driver according to claim 1, wherein each driving unit comprises the shift register and the logic circuit for each row of pixels.

6. The gate driver according to claim 4, wherein a shift register in an m.sup.th driving unit comprises a first thin film register, a second thin film register, a third thin film register, a fourth thin film register, a first capacitor, a second capacitor, and a resistor, wherein a gate of the first thin film transistor is shorted to a source of the first thin film transistor, and when m is equal to 1, the gate acts as an input for an initial trigger signal, and when m is larger than 1, the gate is connected to an output of a logic circuit in an m−1.sup.th driving unit as an input for a trigger signal of the shift register; and the first thin film transistor is connected to the second thin film transistor in series, a connection point between the first thin film transistor and the second thin film transistor is connected to one end of the first capacitor and a gate of the third thin film transistor, the third thin film transistor is connected to the fourth thin film transistor in series, a connection point between the third thin film transistor and the fourth thin film transistor is connected to the other end of the first capacitor and one end of the resistor, and acts as an output of the shift register, a source of the third thin film transistor acts as an input for a clock signal, both a gate of the second thin film transistor and a gate of the fourth thin film transistor act as a reset of the shift register, the other end of the resistor is connected to one end of the second capacitor, and the other end of the second capacitor, a drain of the second thin film transistor, and a drain of the fourth thin film transistor act as an input for a low level signal.

7. A display apparatus, comprising the gate driver according to claim 1.

8. A gate driving method using the gate driver according to claim 1, comprising: in each group of driving units: inputting shift register clock signals with different timings to shift registers in various driving units; and inputting a logic circuit clock signal to logic circuits in various driving units, so that after logic operations are implemented on an output signal of a shift register received by a logic circuit in each driving unit and the logic circuit clock signal, the logic circuits in various driving units output output signals with different timings which have multiple pulses respectively, each of the multiple pulses having a pulse width equal to that of the logic circuit clock signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagram of an active matrix in the related art;

(2) FIG. 2 is a structural diagram of an existing GOA circuit;

(3) FIG. 3 is a diagram of a simulation result of an output signal when dual pulses are input into an existing GOA circuit;

(4) FIG. 4 is a structural diagram of a gate driver circuit according to an embodiment of the present disclosure;

(5) FIG. 5 is diagram of a timing relationship among clock signals multiplexed by shift registers in every 8 driving units, a common clock signal used by all logic circuits, and an initial trigger signal STV input into a shift register in a 1.sup.st driving unit according to an embodiment of the present disclosure;

(6) FIG. 6 is a structural diagram of a shift register circuit according to an embodiment of the present disclosure;

(7) FIG. 7 is a structural diagram of a logic circuit according to an embodiment of the present disclosure;

(8) FIG. 8 is a structural diagram of an equivalent circuit of the logic circuit illustrated in FIG. 7 according to an embodiment of the present disclosure;

(9) FIG. 9 is a diagram of a simulation result of a gate driver according to an embodiment of the present disclosure; and

(10) FIG. 10 is a flowchart of a gate driving method using a gate driver according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

(11) The embodiments of the present disclosure provide a gate driver, a display apparatus, and a gate driving method, to achieve a function of outputting a multi-pulse waveform by the gate driver.

(12) In the gate driver according to the embodiments of the present disclosure, shift registers in every N (N is an integer larger than 1) driving units use a common group of clock signals. An output signal of each shift register is input into a corresponding logic circuit. The logic circuit processes the output signal of the shift register, and selects a part of a clock signal thereof to finally output a multi-pulse shift signal, and transmits the multi-pulse shift signal to a gate end of a gate scan line of a corresponding row of pixels, so as to implement multi-row scanning. In this way, a function of outputting a multi-pulse waveform by a gate driver is achieved, which prepares for a shift register having a function of threshold voltage compensation, to make a shift register capable of multi-row scanning become feasible on a display panel, which solves the technical problem of multi-row scanning on a glass panel.

(13) The embodiments of the present disclosure will be described below by taking N being equal to 8 as an example. Of course, N may be equal to another value, for example, 9. A specific value of N depends on the time required for scanning a row of pixels.

(14) As a drift of a threshold voltage (Vth) of a TFT may result in non-uniformity in the display of the OLED, in order to eliminate such non-uniformity, many OLED pixel circuit structures have a function of internal threshold voltage compensation, and the operation process of the OLED pixel circuits may generally include a pre-charging phase, a compensation phase, a data writing phase, and a light emitting phase. Compared to a scan waveform of the existing Liquid Crystal Display (LCD) gate driving, a scan waveform of the OLED gate driver may be more complex. The GOA according to the embodiment of the present disclosure has a function of outputting a multi-pulse waveform, which may prepare for the pixel circuit having a function of threshold voltage compensation in advance.

(15) As shown in FIG. 4, a gate driver according to an embodiment of the present disclosure comprises multiple groups of driving units, each group of driving units comprising N driving units, each of which comprises a shift register and a logic circuit. In the present embodiment, each driving unit comprises a shift register and a logic circuit, and corresponds to a row of pixels, and N is an integer larger than 1. In the present embodiment, N=8, and an output of a shift register is connected to a logic circuit in each driving unit. In FIG. 4, ON1 represents an output of a shift register in a 1.sup.st driving unit, ON2 represents an output of a shift register in a 2.sup.nd driving unit, ON3 represents an output of a shift register in a 3.sup.rd driving unit, and so on, until ON16 represents an output of a shift register in a 16.sup.th driving unit.

(16) An output of a logic circuit in an m.sup.th driving unit is connected to a gate scan line of an m.sup.th row of pixels, to provide a gate drive signal to the m.sup.th row of pixels. The output of the logic circuit in the m.sup.th driving unit is also connected to an input IN of a shift register in an m+1.sup.th driving unit, wherein m is in a range of [1, M−1], and M is a total number of rows of pixels. That is, as shown in FIG. 4, an output of a logic circuit in a 1.sup.st driving unit is connected to an input IN of a shift register in the 2.sup.nd driving unit, an output of a logic circuit in a 2.sup.nd driving unit is connected to an input IN of a shift register in the 3.sup.rd driving unit, an output of a logic circuit in a 3.sup.rd driving unit is connected to an input IN of a shift register in a 4.sup.th driving unit, and so on, until an output of a logic circuit in a 15.sup.th driving unit is connected to an input IN of a shift register in the 16.sup.th driving unit.

(17) In FIG. 4, Output 1 represents the output of a logic circuit in the 1.sup.st driving unit, Output 2 represents the output of a logic circuit in the 2.sup.nd driving unit, Output 3 represents the output of a logic circuit in the 3.sup.rd driving unit, and so on, until Output 16 represents an output of a logic circuit in a 16.sup.th driving unit; Shift register 1 represents a shift register in the 1.sup.st driving unit, Shift register 2 represents a shift register in the 2.sup.nd driving unit, Shift register 3 represents a shift register in the 3.sup.rd driving unit, and so on, until Shift register 16 represents a shift register in the 16.sup.th driving unit; and Logic circuit 1 represents a logic circuit in the 1.sup.st driving unit, Logic circuit 2 represents a logic circuit in the 2.sup.nd driving unit, Logic circuit 3 represents a logic circuit in the 3.sup.rd driving unit, and so on, until Logic circuit 16 represents a logic circuit in the 16.sup.th driving unit.

(18) An output of a logic circuit in a k.sup.th driving unit is connected to a reset of a shift register in a k−(N−1).sup.th driving unit, wherein k is in a range of [N, M]. In the present embodiment, k starts from 8. That is, an output of a logic circuit in a 8.sup.th driving unit is connected to a reset of a shift register in the 1.sup.st driving unit, an output of a logic circuit in a 9.sup.th driving unit is connected to a reset of a shift register in the 2.sup.nd driving unit, an output of a logic circuit in a 10.sup.th driving unit is connected to a reset of a shift register in the 3.sup.rd driving unit, and so on.

(19) All logic circuits use a common clock signal (which is represented by CLK below as in FIG. 4) with a pulse width equal to a first pulse width and a pulse period equal to a first pulse period.

(20) In each group of driving units (i.e., driving units in every 8 driving units), shift registers in various driving units multiplex N clock signals with different timings. Each of the clock signals has a pulse width equal to a second pulse width and a pulse period equal to a second pulse period. The second pulse width is 2(N−1) times the first pulse width, and the second pulse period is N times the first pulse period. An n.sup.th clock signal is input into a shift register in an n.sup.th driving unit, a timing of an n+1.sup.th clock signal is the first pulse period later than that of the n.sup.th clock signal. A logic circuit in each driving unit outputs a signal having N−1 pulses with a pulse width equal to the first pulse width. A timing of an output signal of a logic circuit in an n+1.sup.th driving unit is the first pulse period later than that of an output signal of a logic circuit in an n.sup.th driving unit, wherein n is in a range of [1, N−1].

(21) In the present embodiment, N=8. A shown in FIG. 4, 8 clock signals with different timings which are multiplexed by shift registers in every 8 driving units are CLK1, CLK2 . . . CLK8 respectively. In each group of driving units, the signal CLK1 is input into a shift register in the 1.sup.st driving unit, the signal CLK2 is input into a shift register in the 2.sup.nd driving unit, and so on, until the signal CLK8 is input into a shift register in a 8.sup.th driving unit.

(22) A timing relationship among the 8 clock signals CLK1, CLK2 . . . CLK8 with different timings which are multiplexed by shift registers in every 8 driving units, the common clock signal CLK used by all logic circuits, and an initial trigger signal STV input into a shift register in the 1.sup.st driving unit is shown in FIG. 5.

(23) With reference to FIG. 6, a shift register in an m.sup.th driving unit comprises a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a first capacitor C1, a second capacitor C2, and a resistor R1.

(24) A gate of the first thin film transistor M1 is shorted to a source of the first thin film transistor M1. When m is equal to 1, the gate acts as an input for an initial trigger signal STV, and when m is larger than 1, the gate is connected to an output Output(m−1) of a logic circuit in an m−1.sup.th driving unit as an input for a trigger signal of the shift register.

(25) The first thin film transistor M1 is connected to the second thin film transistor M2 in series, and a connection point between the first thin film transistor M1 and the second thin film transistor M2 is connected to one end of the first capacitor C1 and a gate of the third thin film transistor M3. The third thin film transistor M3 is connected to the fourth thin film transistor M4 in series, and a connection point between the third thin film transistor M3 and the fourth thin film transistor M4 is connected to the other end of the first capacitor C1 and one end of the resistor R1, and acts as an output ON(m) of the shift register. A source of the third thin film transistor M3 acts as an input for a clock signal CLK(n). Both a gate of the second thin film transistor M2 and a gate of the fourth thin film transistor M4 act as a reset of the shift register. The other end of the resistor R1 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2, a drain of the second thin film transistor M2, and a drain of the fourth thin film transistor M4 act as an input for a low level signal VSS. The specific GOA circuit is not limited in the present disclosure.

(26) With reference to FIG. 7, a logic circuit in an m.sup.th driving unit comprises a first thin film transistor T1, a second thin film transistor T2, and an inverter P1 connected between a gate of the first thin film transistor T1 and a gate of the second thin film transistor T2.

(27) A drain of the first thin film transistor T1 is connected to a drain of the second thin film transistor T2, and acts as an output Output(m) of the logic circuit. A source of the first thin film transistor T1 acts as an input for the common clock signal CLK used by the logic circuits. The gate of the first thin film transistor T1 acts as an input connected to an output ON(m) of a shift register in the m.sup.th driving unit. A source of the second thin film transistor T2 acts as an input for a low level signal VSS.

(28) FIG. 8 illustrates an equivalent circuit of the logic circuit illustrated in FIG. 7, wherein OP(m) represents an inverse signal of an output signal of ON(m). That is, the logic circuit according to the present embodiment is equivalent to being comprised of an inverter, two AND gates, and an OR gate.

(29) With reference to FIG. 9, in the present embodiment, there are 8 clock signals CLK1, CLK2 . . . CLK8 with different timings for shift registers. The shift registers multiplex the 8 clock signals to generate 8 clock signals respectively. Each of the generated clock signals has a wide pulse width which is 14 times a narrow pulse width of a clock signal CLK input into a source of a thin film transistor T1 of a logic circuit. That is, a pulse of the clock signal generated by the shift register corresponds to 7 pulses of the clock signal of the logic circuit. A multi-pulse output signal Outputn with 7 pulses is obtained by implementing logic AND, NOT and OR operations on the two clock signals for selection.

(30) It can be seen from a simulation result illustrated in FIG. 9 that after multiplexing the clock signals CLK1, CLK2 . . . CLK8, the shift registers generate waveforms of output signals ON1-ON8. In this simulation, a pulse width of an output signal ON is 14 times of a narrow pulse width of the clock signal CLK to be used for selection. After a logic NOT operation is implemented on the output signal ON to generate a first signal, the first signal is input into the thin film transistor T2 in FIG. 7 as a logic OR circuit for use. A logic AND operation is implemented on the output signal ON and the clock signal CLK for selection to generate a second signal. Then a logic OR operation is implemented on the first signal and the second signal to finally obtain an output signal Outputn with 7 pulses. That is, an output with 7 pulses is generated by processing the clock signal CLK. In this way, a function of outputting a multi-pulse waveform by a gate driver is achieved, which prepares for a shift register having a function of threshold voltage compensation, to make a shift register capable of multi-row scanning become feasible on a display panel, which solves the technical problem of multi-row scanning on a glass panel.

(31) A display apparatus according to the embodiment of the present disclosure comprises the above gate driver (GOA) according to the embodiment of the present disclosure. The display apparatus may be an OLED display for example.

(32) With reference to FIG. 10, a gate driving method using the gate driver according to the embodiment of the present disclosure comprises:

(33) in each group of driving units:

(34) in operation 1001, inputting shift register clock signals with different timings to shift registers in various driving units; and

(35) in operation 1002, inputting a logic circuit clock signal to logic circuits in various driving units, so that after logic operations are implemented on an output signal of a shift register received by a logic circuit in each driving unit and the logic circuit clock signal, the logic circuits in the various driving units output signals with different timings which have multiple pulses respectively, each of the multiple pulses having a pulse width equal to that of the logic circuit clock signal.

(36) Preferably, the logic circuit clock signal has a pulse width equal to a first pulse width and a pulse period equal to a first pulse period.

(37) In each group of driving units, each shift register clock signal has a pulse width equal to a second pulse width and a pulse period equal to a second pulse period, wherein the second pulse width is larger than the first pulse width, and the second pulse period is larger than the first pulse period.

(38) Preferably, the second pulse width is 2*(N−1) times the first pulse width, and the second pulse period is N times the first pulse period.

(39) In each group of driving units, a timing of an n+1.sup.th shift register clock signal is the first pulse period later than an n.sup.th shift register clock signal; and a logic circuit in each driving unit outputs an output signal having N−1 pulses with a pulse width equal to the first pulse width, and a timing of an output signal of a logic circuit in an n+1.sup.th driving unit is the first pulse period later than that of an output signal of a logic circuit in an n.sup.th driving unit, wherein n is in a range of [1, N−1].

(40) Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure belong to the scope of the claims of the present disclosure and the equivalent technologies thereof, the present disclosure is also intended to include these modifications and variations.