Multilayer circuit board and method for manufacturing the same

Abstract

A method for manufacturing a multilayer circuit board includes: forming a first patterned conductive layer on a ceramic substrate, the first patterned conductive layer having a first circuit pattern and a first submount pattern; forming a second patterned conductive layer on the first patterned conductive layer, the second patterned conductive layer having a second circuit pattern and a second submount pattern; forming an insulating layer on the ceramic substrate; and forming a third patterned conductive layer on the insulating layer. The third patterned conductive layer having a third circuit pattern and a third submount pattern. The first, second and third submount patterns are stacked one above another.

Claims

1. A multilayer circuit board adapted for mounting and heat dissipation of at least one semiconductor chip and comprising: a ceramic substrate; a first patterned conductive layer that is stacked on said ceramic substrate along a stacking direction, said first patterned conductive layer having a first circuit pattern and a first submount pattern, said first submount pattern including one or more first pads; a second patterned conductive layer that is stacked on said first patterned conductive layer, said second patterned conductive layer having a second circuit pattern which is connected to said first circuit pattern, and a second submount pattern which is connected to and at least partially overlaps said first submount pattern along the stacking direction, said second submount pattern including one or more second pads; an insulating layer stacked on said ceramic substrate and disposed among said first and second circuit patterns and said first and second submount patterns, such that a top surface of said second patterned conductive layer is exposed from said insulating layer; and a third patterned conductive layer that is stacked on said insulating layer and said top surface of said second patterned conductive layer, said third patterned conductive layer having a third circuit pattern which is connected to said second circuit pattern, and a third submount pattern which is connected to and at least partially overlaps said second submount pattern along the stacking direction and which is adapted for mounting of the semiconductor chip thereon, said third submount pattern including one or more third pads; wherein said second circuit pattern has a plurality of interconnections interconnecting said first circuit pattern and said third circuit pattern, and wherein at least said first, second and third submount patterns constitute a submount structure adapted for mounting and heat dissipation of the at least one semiconductor chip, said submount structure having at least one submount block which includes a corresponding one of said one or more first pads, a corresponding one of said one or more second pads, and a corresponding one of said one or more third pads, said first, second, and third pads of each of said at least one submount block being stacked one above another along the stacking direction such that said insulating layer steers clear of stacking of said first, second, and third pads along the stacking direction.

2. The multilayer circuit board as claimed in claim 1, further comprising a first seed layer sandwiched between said first patterned conductive layer and said ceramic substrate, and a second seed layer sandwiched between said third patterned conductive layer and said insulating layer.

3. The multilayer circuit board as claimed in claim 1, further comprising a surface finish layer formed on said third patterned conductive layer, wherein said surface finish layer includes at least two metal sub-layers, each of which is made from a different metallic material selected from the group consisting of Ni, Au, Ag, and Pd.

4. The multilayer circuit board as claimed in claim 1, wherein the submount structure is directly formed on and contacts the ceramic substrate.

5. The multilayer circuit board as claimed in claim 1, wherein the submount structure is made from metal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features and advantages of the present invention will become apparent in the following detailed description of the embodiment with reference to the accompanying drawings, of which:

(2) FIGS. 1 to 14 are schematic views illustrating consecutive steps of the embodiment of a method for manufacturing a multilayer circuit board;

(3) FIG. 15 is a flow chart of the embodiment; and

(4) FIG. 16 is a schematic view illustrating a state where a plurality of semiconductor chips are mounted on the multilayer circuit board of the embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENT

(5) The above-mentioned and other technical contents, features, and effects of this invention will be clearly presented from the following detailed description of the embodiment in coordination with the reference drawings.

(6) FIG. 15, together with FIGS. 1 to 14, illustrates consecutive steps (S01-S14) of the embodiment of a method for manufacturing a multilayer circuit board having a metallic submount structure 10 for mounting and heat dissipation of at least one semiconductor chip 9 (see FIG. 16), such as an LED chip, according to the present invention.

(7) Step S01: providing a ceramic substrate 1 (see FIG. 1). The ceramic substrate 1 is made from a material selected from the group consisting of aluminum oxide, aluminum nitride, silicon nitride, zirconia, and zirconia toughened alumina.

(8) Step S02: forming a first seed layer 21 on a surface of the ceramic substrate 1 (see FIG. 2) by sputtering. The first seed layer 21 is used for subsequent electroplating.

(9) Step S03: forming a first photoresist pattern 31 on the first seed layer 21 by photolithography, the first photoresist pattern 31 having holes 311 that expose a portion of the first seed layer 21.

(10) Step S04: forming a first patterned conductive layer 4 on the portion of the first seed layer 21 that is not covered by the first photoresist pattern 31 (see FIG. 4), such that the first patterned conductive layer 4 is stacked on the ceramic substrate 1 along a stacking direction (in this embodiment, the first patterned conductive layer 4 is directly formed on and contacts the ceramic substrate 1). The first patterned conductive layer 4 has a first circuit pattern 41 that includes a plurality of lower traces 411, and a first submount pattern 42 that includes a plurality of first pads 421. In this embodiment, the first patterned conductive layer 4 is made from copper, and is formed by electroplating.

(11) Step S05: forming a second photoresist pattern 32 on the first patterned conductive layer 4 and the first photoresist pattern 31 (see FIG. 5) by photolithography, the second photoresist pattern 32 having holes 321 that expose a portion of the first patterned conductive layer 4.

(12) Step S06: forming a second patterned conductive layer 5 on the portion of the first patterned conductive layer 4 that is not covered by the second photoresist pattern 32 (see FIG. 6). The second patterned conductive layer 5 has a second circuit pattern 51 which is connected to the first circuit pattern 41 (see FIG. 3) and which includes a plurality of interconnections 511, and a second submount pattern 52 which is connected to and at least partially overlaps the first submount pattern 42 (see FIG. 3) along the stacking direction. Specifically, the second submount pattern 52 includes a plurality of second pads 521, each of which is connected to and at least partially overlaps a corresponding one of the first pads 421 of the first submount pattern 42 along the stacking direction. In this embodiment, the second patterned conductive layer 5 is also made from copper, and is formed by electroplating.

(13) Step S07: removing the first and second photoresist patterns 31, 32 and the remaining portion of the first seed layer 21 that is not covered by the first patterned conductive layer 4 (see FIG. 7) after forming the second patterned conductive layer 5.

(14) Step S08: providing a softened thermoplastic film 60 to cover the ceramic substrate 1 and the first and second patterned conductive layers 4, 5 and to fill gaps among the first and second circuit patterns 41, 51 and the first and second submount patterns 42, 52, followed by curing the softened thermoplastic film 60 (see FIG. 8).

(15) Step S09: polishing the cured thermoplastic film 60 to expose a top surface of the second patterned conductive layer 5 (see FIG. 9), thereby forming an insulating layer 6 on the ceramic substrate 1, such that the insulating layer 6 is disposed among the first and second circuit patterns 41, 51 and the first and second submount patterns 42, 52 and that the top surface of the second patterned conductive layer 5 is exposed from the insulating layer 6.

(16) Step S10: forming a second seed layer 22 on the insulating layer 6 and the top surface of the second patterned conductive layer 5 (see FIG. 10) by sputtering for subsequent electroplating.

(17) Step S11: forming a third photoresist pattern 33 on the second seed layer 22 by photolithography (see FIG. 11), the third photoresist pattern 33 having holes 331 that expose a portion of the second seed layer 22.

(18) Step S12: forming a third patterned conductive layer 7 on the portion of the second seed layer 22 that is not covered by the third photoresist pattern 33 (see FIG. 12), such that the third patterned conductive layer 7 is stacked on the insulating layer 6 and the top surface of the second patterned conductive layer 5. The third patterned conductive layer 7 has a third circuit pattern 71 which is connected to the second circuit pattern 51, and a third submount pattern 72 which is connected to and at least partially overlaps the second submount pattern 52 along the stacking direction. Specifically, the third circuit pattern 71 includes a plurality of upper traces 711 that are electrically connected to the lower traces 411 of the first circuit pattern 41 through the interconnections 511 of the second circuit pattern 51. The third submount pattern 72 includes a plurality of third pads 721, each of which is connected to and at least partially overlaps a corresponding one of the second pads 521 of the second submount pattern 52 along the stacking direction. In this embodiment, the third patterned conductive layer 7 is also made from copper, and is formed by electroplating.

(19) Step S13: forming a surface finish layer 8 on the third patterned conductive layer 7 (see FIG. 13). In an embodiment, the surface finish layer 8 includes at least two metal sub-layers, each of which is made from a different metallic material selected from the group consisting of Ni, Au, Ag, and Pd. For example, the sub-layers may be made from Ni and Au, Ni and Pd, or Ni and Ag respectively. In another embodiment, the surface finish layer 8 may be made of a bi-metallic material. The bi-metallic material includes two of the following metals: Ni, Au, Ag, and Pd. Alternatively, the surface finish layer 8 is made from a different metallic material selected from the group consisting of Ni, Au, Ag, and Pd. The surface finish layer 8 is used for enhancing solderability and a bonding force for wire bonding.

(20) Step S14: removing the third photoresist pattern 33 and the remaining portion of the second seed layer 22 that is not covered by the third patterned conductive layer 7 (see FIG. 14), thereby forming the multilayer circuit board 100. The first, second and third circuit patterns 41, 51, 71 form multilayer circuits. The first, second and third submount patterns 42, 52, 72, the portions of the first and second seed layers 21, 22, and the surface finish layer 8 cooperatively form the metallic submount structure 10 that is made from metal and that is directly formed on and contacts the ceramic substrate 1. Specifically, the submount structure 10 has a plurality of spaced apart submount blocks 101, each of which includes a corresponding one of the first, second and third pads 421, 521, 721 stacking along the stacking direction.

(21) The multilayer circuit board thus formed may be used for mounting of a plurality of semiconductor chips 9 on the submount blocks 101 through wire bonding techniques (see FIG. 16). In this embodiment, the semiconductor chips 9 are horizontal type light emitting diode (LED) chips. Alternatively, the semiconductor chips 9 may be vertical type light emitting diode (LED) chips.

(22) Since the submount blocks 101 are formed through the formation of the first, second and third patterned conductive layers 4, 5, 7 that are stacked one above another according to the present invention, at least one of the aforesaid drawbacks associated with the prior art may be alleviated or overcome.

(23) While the present invention has been described in connection with what is considered the most practical embodiment, it is understood that this invention is not limited to the disclosed embodiment but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.