Integrated amplifier system

Abstract

Technologies are described to DC-couple an integrated amplifier system to a source that provides a signal with an unknown DC component, for example to DC-couple an integrated audio codec to an analog microphone. In one aspect, methods include receiving, by an amplifier, a signal having an unknown DC component, and issuing an amplified signal; low pass filtering, with respect to a cutoff frequency, by a feedback circuit coupled between an output of the amplifier and an input of the amplifier, the amplified signal issued at the output of the amplifier to generate a filtered signal having frequencies lower than the cutoff frequency; and injecting, by the feedback circuit, the filtered signal into the input of the amplifier to cancel the unknown DC component below the cutoff frequency.

Claims

1. An amplification system comprising: an amplifier configured and arranged to receive a signal comprising a DC component, and issue an amplified signal; and a feedback circuit coupled between an output of the amplifier and an input of the amplifier, wherein the feedback circuit comprises an operational amplifier and a secondary feedback circuit arranged to provide negative feedback to the operational amplifier, the secondary feedback circuit comprising a switched capacitor, and the feedback circuit is configured to filter, with respect to a cutoff frequency, the amplified signal issued at the output of the amplifier to generate a filtered signal having frequencies lower than the cutoff frequency, and inject the filtered signal into the input of the amplifier to cancel the DC component below the cutoff frequency.

2. The amplification system of claim 1, wherein the secondary feedback circuit further comprises an integrator capacitor, such that the operational amplifier and the secondary feedback circuit are arranged as an active integrator circuit.

3. The amplification system of claim 1, wherein the received signal is a differential voltage across first and second nodes of an electrical circuit, a voltage bias of the first node being higher than a voltage bias of the second node by the DC component of the received signal, and the amplifier comprises a non-inverting amplifier input connected to the first node of the electrical circuit, and an inverting amplifier input, and the feedback circuit comprises a first feedback input connected to the output of the amplifier, a second feedback input connected to the second node of the electrical circuit, and a feedback output connected to the inverting amplifier input where the filtered signal is injected by the feedback circuit.

4. A method comprising: receiving, by an amplifier, a signal that comprises a DC component, and issuing an amplified signal; filtering, with respect to a cutoff frequency, by a feedback circuit that (i) comprises an operational amplifier and a secondary feedback circuit arranged to provide negative feedback to the operational amplifier and (ii) is coupled between an output of the amplifier and an input of the amplifier, the amplified signal issued at the output of the amplifier to generate a filtered signal having frequencies lower than the cutoff frequency, wherein the filtering comprises switching a switched capacitor of the secondary feedback circuit at frequencies larger by a predetermined factor than an upper bound of a frequency spectrum of the received signal; and injecting, by the feedback circuit, the filtered signal into the input of the amplifier to cancel the DC component below the cutoff frequency.

5. The method of claim 4, comprising maintaining, by the feedback circuit at the input of the amplifier, a ratio of noise generated by the feedback circuit to a portion of the received signal having frequencies above the cutoff frequency below a predetermined ratio value.

6. The method of claim 4, wherein the cutoff frequency with respect to which the filtering is performed is less than a lower bound of a frequency spectrum of the received signal.

7. The method of claim 4, comprising: issuing, by the amplifier, two amplified signals at respective outputs of the amplifier; and converting, by an analog-to-digital convertor connected with the outputs of the amplifier, a difference of the amplified signals to a digital signal.

8. The method of claim 4, wherein the signal is received by the amplifier at a non-inverting input, the filtered signal is injected by the feedback circuit at an inverting input of the amplifier, and the method further comprises determining, by a detection circuit connected to the input of the amplifier, whether the DC component meets a target DC voltage; and in response to determining that the DC component meets a target DC voltage, causing that the amplifier, the feedback circuit or both be powered ON or be maintained in a power ON state, or else causing that the amplifier, the feedback circuit or both to be powered OFF or be maintained in a power OFF state.

9. An integrated circuit comprising: a first input port and a second input port, wherein the first input port is configured to receive a voltage that comprises a DC voltage; and an audio codec circuit, wherein the audio codec circuit comprises: an amplifier comprising an inverting amplifier input, a non-inverting amplifier input, one or more amplifier outputs, and a negative feedback loop, wherein the non-inverting amplifier input is coupled to the first input port and the negative feedback loop is connected to the second input port, and wherein the negative feedback loop comprises an active integrator circuit comprising (i) an operational amplifier, (ii) a switched capacitor connected to an inverting input of the operational amplifier, and (iii) an integrator capacitor connected between an output of the operational amplifier and the inverting input of the operational amplifier, the active integrator circuit being configured to generate at the inverting amplifier input a feedback DC voltage that counterbalances the DC voltage, such that one or more amplified voltages issued by the amplifier at the respective one or more amplifier outputs have only components with finite frequencies.

10. The integrated circuit of claim 9, wherein the integrator capacitor is a metal-oxide-semiconductor capacitor.

11. The integrated circuit of claim 9, wherein a capacitance of the integrator capacitor is between 10-45 pF, such that noise generated by the active integrator circuit at the inverting amplifier input is less than 5μ V.sub.RMS.

12. The integrated circuit of claim 9, wherein an upper bound of a frequency range of the received voltage is in a range of 8-20 kHz, and the switched capacitor is switched at a switching frequency in the range of 80 kHz to 200 kHz.

13. The integrated circuit of claim 12, wherein the active integrator is arranged and configured to provide a low pass filter associated with a cutoff frequency to the one or more amplified voltages, and a capacitance of the switched capacitor is in a range of 5-100 fF such that an effective resistance of the switched capacitor causes the cutoff frequency to be less than 200 Hz.

14. The integrated circuit of claim 9, wherein the received voltage is a differential voltage across first and second nodes of a microphone circuit, the first port is connected to the first node of the microphone circuit and the second port is connected to the second node of the microphone circuit, and the negative feedback loop comprises a first feedback input connected to one of the one or more amplifier outputs, a second feedback input connected to the second port, and a feedback output connected to the inverting amplifier input where the DC feedback voltage is generated by the negative feedback loop.

15. The integrated circuit of claim 9, wherein the audio codec circuit further comprises an analog-to-digital converter connected with the one or more amplifier outputs to convert the one or more amplified voltages to corresponding digital signals.

16. The integrated circuit of claim 9, wherein the audio codec circuit comprises a detection circuit connected to the first input port to compare the DC voltage to a target DC voltage, such that the amplifier is to be powered ON or OFF in accordance with a result of the comparison.

17. The integrated circuit of claim 9, wherein the amplifier comprises a programmable gain amplifier.

18. The integrated circuit of claim 9, wherein the amplifier comprises a fully-differential amplifier.

Description

DESCRIPTION OF DRAWINGS

(1) FIGS. 1A-1D show aspects of an example of an amplification system that can be DC-coupled to a source providing a signal with an unknown DC component.

(2) FIG. 2 shows an example of an audio processing system in which the amplification system from FIG. 1A that is DC-coupled to an audio source that provides a signal with an unknown DC component.

(3) FIG. 3 shows an example of a conventional integrated audio codec.

(4) FIGS. 4A-4C show aspects of an example of an integrated audio codec DC-coupled to an audio source that provides a signal with an unknown DC component.

(5) FIG. 5 is a flow chart showing an example of a process for amplifying a signal that includes an unknown DC component.

(6) FIG. 6 is a flow chart showing an example of a process for controlling power to, at least, a portion of an integrated audio codec that executes the process illustrated in FIG. 5.

(7) Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

(8) FIG. 1A shows an example of an amplification system 100 that can be DC-coupled to a source providing a signal with an unknown DC component. The amplification system includes an amplifier 110 with gain G and a feedback loop 120 (also referred to, interchangeably, as a feedback circuit 120.) The amplifier 110 is arranged and configured to receive a signal that includes an unknown DC component U, and to issue an amplified signal. The feedback circuit 120 is coupled between an output of the amplifier 110 and an input of the amplifier. The feedback circuit 120 is configured to low pass filter, with respect to a cutoff frequency f.sub.C, the amplified signal issued at the output of the amplifier 110 to generate a filtered signal having frequencies lower than the cutoff frequency f.sub.C. Additionally, the feedback circuit 120 is configured to inject the filtered signal into the input of the amplifier 110 to cancel the unknown DC component U below the cutoff frequency.

(9) In some implementations, the received signal can be a differential voltage across first and second nodes of an electrical circuit (not shown in FIG. 1A), where a voltage bias of the first node is higher than a voltage bias of the second node by the unknown DC component U of the received signal. In the example illustrated in FIG. 1A, a first input I.sub.1 of the amplification system 100 is connected to the first node of the electrical circuit and a second input I.sub.2 of the amplification system 100 is connected to the second node of the electrical circuit. In this manner, a first input voltage V.sub.in1(t) at the first input I.sub.1 of the amplification system 100 is V.sub.in1(t)=v.sub.i1(t)+U, and a second input voltage V.sub.in2(t) at the second input I.sub.2 of the amplification system 100 is V.sub.in2(t)=v.sub.i2(t). Here, the unknown DC component U represents a relative DC bias between V.sub.in1(t) and V.sub.in2(t). Additionally, v.sub.inj(t), where j=1 or 2, represents a portion of the j.sup.th input voltage V.sub.inj(t) that varies in time and, hence, includes only components with finite (non-zero) frequencies.

(10) Further in the example illustrated in FIG. 1A, the amplifier 110 has a non-inverting input connected to the first input I.sub.1 of the amplification system 100 and an inverting input N.sub.1. Also, the amplification system 100 has a first output O.sub.1 connected to a first output of the amplifier 110. As such, a first amplified signal V.sub.out1(t) is issued by the amplifier 110 at the first output O.sub.1. Optionally, the amplification system 100 has a second output O.sub.2 connected to a second output of the amplifier 110. In the latter case, a second amplified signal V.sub.out2(t) is issued by the amplifier 110 at the second output O.sub.2 concurrently with the first amplified signal V.sub.out1(t) issued at the first output O.sub.1.

(11) Furthermore in the example illustrated in FIG. 1A, the feedback circuit 120 has a first feedback input X connected to the first output O.sub.1 of the amplifier 110 and a second feedback input Y connected to the second input I.sub.2 of the amplification system 100. Also, the feedback circuit 120 has a feedback output Z connected to the non-inverting input N.sub.1 of the amplifier 110. Optionally, the feedback circuit 120 has a third input W connected to the optional second output O.sub.2 of the amplifier 110. As described above, the feedback circuit 120 is configured as a low pass filter that blocks components with frequencies larger than the cutoff frequency f.sub.C of the first amplified signal V.sub.out1(t) issued at the first output O.sub.1. In this manner, the first amplified signal V.sub.out1(t) issued at the first output O.sub.1 is V.sub.out1(t)=v.sub.out1(t) and contains only components with frequencies larger than the cutoff frequency f.sub.C. Similarly, when the second output O.sub.2 is available, the second amplified signal V.sub.out2(t) issued at the second output O.sub.2 is V.sub.out2(t)=v.sub.out2(t) and contains only components with frequencies larger than the cutoff frequency f.sub.C.

(12) Moreover, the filtered signal generated by the feedback circuit 120 at the feedback output Z includes only components with frequencies less than or equal to the cutoff frequency f.sub.C. In this manner, the filtered signal provided at the inverting input N.sub.1 of the amplifier 110 counterbalances the unknown DC component U of the first input voltage V.sub.in1(t).

(13) FIG. 1B shows an example of the amplifier 110 implemented as a standard differential amplifier 110′ and FIG. 1C shows an example of the amplifier 110 implemented as a fully-differential amplifier 110″. The standard differential amplifier 110′ has differential inputs I.sub.1 and N.sub.1 connected via resistors R.sub.1 with respective non-inverting and inverting inputs of an operational amplifier 112′ having open loop gain A′. Similarly, the fully-differential amplifier 110″ has differential inputs I.sub.1 and N.sub.1 connected via resistors R.sub.1 with respective non-inverting and inverting inputs of an operational amplifier 112″ having open loop gain A″. The standard differential amplifier 110′ has a single ended output O.sub.1, while the fully-differential amplifier 110″ has differential outputs O.sub.1 and O.sub.2. There is a single feedback path from the single ended output O.sub.1 via resistor R.sub.2 to the inverting input of the operational amplifier 112′ in the standard differential amplifier 110′. In contrast, the fully-differential amplifier 110″ has a first feedback path from the first output O.sub.1 via resistor R.sub.2 to the inverting input of the operational amplifier 112″ and a second feedback path from the second output O.sub.2 via resistor R.sub.2 to the non-inverting input of the operational amplifier 112″. The gain G of the standard differential amplifier 110′ is given by

(14) $\begin{array}{cc}G=\frac{V_{\mathrm{out}1}\left(t\right)}{V_{\mathrm{in}1}\left(t\right)-V_{\mathrm{in}2}\left(t\right)}=\frac{R_2}{R_1},& \left(1\right)\end{array}$
where an amplified voltage V.sub.out1(t) issued at the single ended output O.sub.1 is proportional to an input differential voltage V.sub.in1(t)-V.sub.in2(t) applied between the differential inputs I.sub.1 and N.sub.1. Similarly, the gain G of the fully-differential amplifier 110″ is given by

(15) $\begin{array}{cc}G=\frac{V_{\mathrm{out}1}\left(t\right)-V_{\mathrm{out}2}\left(t\right)}{V_{\mathrm{in}1}\left(t\right)-V_{\mathrm{in}2}\left(t\right)}=\frac{R_2}{R_1},& \left(2\right)\end{array}$
where an amplified differential voltage V.sub.out1(t)-V.sub.out2(t) issued between the differential outputs O.sub.1 and O.sub.2 is proportional to an input differential voltage V.sub.in1(t)-V.sub.in2(t) applied between the differential inputs I.sub.1 and N.sub.1. In case the standard differential amplifier 110′ or the fully-differential amplifier 110″ is implemented as a programmable gain amplifier, the gain G can be changed in a programmable manner by changing the ratio of the resistors R.sub.1 and R.sub.2.

(16) FIG. 1D shows an implementation of the feedback circuit 120 as an active integrator 120′. Here, the active integrator 120′ includes an operational amplifier 122 having an open-loop gain A.sub.I; a resistive element 124 having a resistance R.sub.1 and being connected between the first feedback input X of the active integrator 120′ and an inverting input of the operational amplifier 122; and a capacitive element 126 having a capacitance C.sub.1 and being connected between the inverting input of the operational amplifier 122 and the feedback output Z of the active integrator 120′. Note that in the example illustrated in FIG. 1D, the second feedback input Y of the active integrator 120′ is connected to the non-inverting input of the operational amplifier 122, which in turn is connected to ground.

(17) A transfer function of the amplification system 100 illustrated in FIG. 1A having the amplifier 110 with gain G and the feedback circuit 120 implemented as the active integrator 120′ illustrated in FIG. 1D can be expressed as:

(18) $\begin{array}{cc}\frac{V_{\mathrm{out},\mathrm{diff}}}{V_{\mathrm{in},\mathrm{se}}}=\frac{\mathrm{sG}}{s+\frac{{\mathrm{GR}}_I}{C_I}}.& \left(3\right)\end{array}$

(19) Equation (3) indicates that the transfer function of the amplification system 100 is zero at DC (for s=0) and has a pole at GR.sub.I/C.sub.I. As such, the amplification system 100 having a transfer function given by Equation (3) operates like a high pass filter with a cutoff frequency f.sub.C=GR.sub.I/C.sub.I. In case the amplifier 110 is implemented as a programmable gain amplifier, in which the gain G can be changed in a programmable manner, the product GR.sub.I must be maintained constant in order for the cutoff frequency f.sub.C of the amplification system 100 to remain constant. This can be accomplished by using a resistive element 124 with adjustable resistance R.sub.1. In some cases, the resistive element 124 can be implemented as a resistor having resistance R.sub.1. In other cases, the resistive element 124 can be implemented as a capacitor with capacitance C.sub.S that is switched with a switching frequency f.sub.S, such that the switched capacitor has an effective resistance R.sub.1=1/f.sub.SC.sub.S.

(20) Noise provided by the active integrator 120′ to the non-inverting input N.sub.1 of the amplifier 110 has a contribution from the operational amplifier 122 and a k.sub.BT/C.sub.1 contribution. Here, k.sub.B is Boltzmann's constant and T is absolute temperature. The k.sub.BT/C.sub.1 noise contribution can be mitigated by using a minimum capacitance C.sub.1 for which this noise contribution is less than a maximum acceptable noise value of 2μ V.sub.RMS, for instance. Similarly, as the operational amplifier 122 has a unitary transfer function, its noise contribution can be mitigated by using a low noise operational amplifier for which the total noise integrated between the cutoff frequency f.sub.C and a maximum frequency f.sub.MAX of a frequency range [f.sub.C, f.sub.MAX] of interest is less than a maximum acceptable noise value of 2μ V.sub.RMS, for instance. An example of the frequency range [f.sub.C, f.sub.MAX] of interest is an audio frequency range starting at about 200 Hz and extending up to about 20 kHz, for instance. As such, the amplification system 100 can be used to amplify audio signals received from an audio frequency source, when the audio signals include an unknown DC component.

(21) FIG. 2 shows an example of an audio processing system 201 in which an amplification system 200 is DC-coupled to an audio source 240 that provides an audio signal with an unknown DC component. Here, the audio signal with the unknown DC component is provided as an input differential voltage V.sub.in1(t)-V.sub.in2(t) over differential inputs I.sub.1 and I.sub.2 of the amplification system 200. In addition to the amplifier system 200, the audio processing system 201 includes an analog-to-digital convertor (ADC) 250 to convert an amplified differential voltage V.sub.out1(t)-V.sub.out2(t) issued by the amplification system 200 at differential outputs O.sub.1 and O.sub.2 to a digital signal.

(22) The amplification system 200 can be the amplification system 100 described above in connection with FIGS. 1A-1D. Here, the amplifier 210 with gain G is implemented as a fully-differential amplifier as described above in connection with FIG. 1C. The feedback circuit 220 can be the feedback circuit 120 implemented as an active integrator similar to the active integrator 120′ described above in connection with FIG. 1D. In the example illustrated in FIG. 2, a first feedback input X of the feedback circuit 220 is connected to the first output O.sub.1 of the amplification system 200; a second feedback input Y of the feedback circuit 220 is connected to the second input I.sub.2 of the amplification system 200; a third feedback input W of the feedback circuit 220 is connected to the second output O.sub.2 of the amplification system 200; and a feedback output of the feedback circuit 220 is connected to the inverting input N.sub.1 of the amplifier 210.

(23) Further in the example illustrated in FIG. 2, the audio source 240 is a microphone circuit including a field effect transistor (FET) 244 configured to convert sound signals captured by a microphone to audio signals. The FET 244 is biased by a voltage source V.sub.BIAS via a bias resistor R.sub.BIAS. The first input I.sub.1 of the amplification system 200 is connected to a first node of the microphone circuit 240 on the drain side of the FET 244, and the second input I.sub.2 of the amplification system 200 is connected to a second node of the microphone circuit 240 on the source side of the FET 244 (which, here, it is connected to ground.) In this manner, there is a finite (non-zero) DC voltage bias U between the first input voltage V.sub.in1(t) and the second input voltage V.sub.in2(t) which depends at least on combination of a value of the voltage source V.sub.BIAS and a value of the bias resistor R.sub.BIAS. Because this combination can vary between different types/brands of microphones, the DC voltage bias U between the first input voltage V.sub.in1(t) applied at the first input I.sub.1 of the amplification system 200 and the second input voltage V.sub.in2(t) applied at the second input I.sub.2 of the amplification system 200 is treated as an unknown DC component U of the first input voltage V.sub.in1(t).

(24) As described above in connection with FIG. 1A, the feedback circuit 220 low-pass filters the amplified differential voltage V.sub.out1(t)-V.sub.out2(t) issued by the amplification system 200 at the differential outputs O.sub.1 and O.sub.2 to generate a filtered signal that includes only components with frequencies less than a cutoff frequency f.sub.C. As the amplification system 200 is applied here to audio signals, the cutoff frequency is chosen to be between 20-200 Hz. The filtered signal is provided by the feedback circuit 220 through the feedback output Z at the inverting input N.sub.1 of the amplifier 200. As noted above, the feedback circuit 220 is implemented as an active integrator. As the active integrator continues to integrate the signals input at the feedback inputs X, Y and W of the feedback circuit 220, a DC component V.sub.N1 of the filtered signal provided, by the feedback circuit 220 through the feedback output Z, at the inverting input N.sub.1 of the amplifier 210 continues to increase until it reaches a value equal to the unknown DC component U of the first input voltage V.sub.in1(t) applied at the first input I.sub.1 of the amplification system 200. Once V.sub.N1 reached the value U, the unknown DC component U at the non-inverting input of the amplifier 210 is counterbalanced by the DC component V.sub.N1≈U at the inverting input of the amplifier 210. From there on, the DC component V.sub.N1 will remain constant at the value U, and the amplifier 210 will amplify only components of the input signal that have finite frequencies, f≠0.

(25) In some implementations, detection of the unknown DC component U at the non-inverting input of the amplifier 210 can be used to infer whether the audio source 240 is connected to the amplification system 200. A (partial or full) power state of the amplification system 200 may be controlled based on such inference. For example, if an unknown DC component U detected at the non-inverting input of the amplifier 210 meets a target bias value, then the amplifier 210, the feedback circuit 220 or both can be turned ON (or maintained in a powered-ON state). As another example, if the unknown DC component U detected at the non-inverting input of the amplifier 210 does not meet the target bias value, then the amplifier 210, the feedback circuit 220 or both can be turned OFF (or maintained in a powered-OFF state).

(26) The amplification system 200 and the ADC 250 of the audio processing system 201 (and optionally additional circuitry to determine whether an audio source is connected to the audio processing system 201) can be integrated into an integrated circuit, a system on a chip, or the like. Prior to describing an example of an integrated audio codec that includes an amplifier system in accordance with the disclosed technologies, a conventional integrated audio codec is described below.

(27) FIG. 3 shows a portion of a mobile device 301 including a conventional integrated audio codec 305 and a microphone circuit associated with an external analogue microphone. The conventional integrated audio codec 305 includes a programmable gain amplifier (represented as a dotted box) and an ADC. The microphone circuit provides a differential audio signal that is AC-coupled to the conventional integrated audio codec 305. Here, the AC-coupling is accomplished with external capacitors C.sub.E1 and C.sub.E2 connected between two nodes of the microphone circuit and respective pins (or ports) P.sub.1 and P.sub.2 of the conventional integrated audio codec 305. Capacitance values of the external capacitors C.sub.E1 and C.sub.E2 range from 100 nF and 2 μF. Such big capacitance values are needed to high pass filter the input differential signal with very low 3 dB cut-off frequency f.sub.C in the range of 20-200 Hz. As high capacitance values can be achieved by using large-size capacitors, the capacitors C.sub.E1 and C.sub.E2 are placed outside of the conventional integrated audio codec 305, e.g., on a circuit board 306. In addition, the conventional integrated audio codec 305 includes a microphone detection circuit which compares an unknown DC bias component of the input audio signal to a target bias voltage. As the input audio signal is AC-coupled to the conventional integrated audio codec 305, the audio signal that includes the unknown DC bias component must be provided inside the conventional integrated audio codec 305 through a dedicated pin P.sub.D with which the microphone detection circuit is coupled. Hence, a pad associated with the dedicated pin P.sub.D must be added to the circuit board 306, such that the pad can be reached by the input audio signal prior to reaching the external capacitor C.sub.E1.

(28) Bill of material costs along with strategies of separating and sizing components of the mobile device 301 are negatively impacted by the need to place external capacitors C.sub.E1 and C.sub.E2 on the circuit board 306—outside of the conventional integrated audio codec 305—to AC-couple the input audio signal to the conventional integrated audio codec 305. Further negative impact is created by the need to provide a combination of a pad located on the circuit board 306 and a dedicated pin P.sub.D of the conventional integrated audio codec 305 for detecting the unknown DC bias component of the input audio signal.

(29) The technologies described above in connection with FIGS. 1A, 1D and 2 can be used to modify the conventional integrated audio codec 305 to eliminate a portion of the circuit board 306 that supports the external capacitors C.sub.E1 and C.sub.E2 by integrating a high pass filter function within an improved integrated audio codec to allow for the input audio signal to be DC-coupled with the improved integrated audio codec. Moreover, the integrated audio codec improved in this manner manages to remove the dedicated pin P.sub.D of the conventional integrated audio codec 305 and to eliminate another portion of the circuit board 306 that supports the pad associated with the dedicated pin P.sub.D by connecting the microphone detection circuit to the first input pin P.sub.1.

(30) FIG. 4A shows a portion of a mobile device 401 including an integrated audio codec 405 configured in accordance with the disclosed technologies and a microphone circuit 240 associated with an external analogue microphone. The microphone circuit 240 provides an audio signal that is DC-coupled to the integrated audio codec 405. The integrated audio codec 405 includes first and second input pins (or ports) P.sub.1 and P.sub.2, an amplification system 110″ and an ADC 250. Here, the audio signal includes an unknown DC component and is provided as an input differential voltage V.sub.inP1(t)-V.sub.inP2(t) over the first and second input pins P.sub.1 and P.sub.2 of the integrated audio codec 405. In this example, the first and second input pins P.sub.1 and P.sub.2 represent the differential inputs of the amplification system 400. An amplified differential voltage V.sub.out1(t)-V.sub.out2(t) issued by the amplification system 400 at differential outputs O.sub.1 and O.sub.2 is converted by the ADC 250 to a digital signal.

(31) The amplification system 400 can be implemented as an integrated version of the amplification system 100 described above in connection with FIGS. 1A-1D. Here, the amplification system 400 includes an amplifier 110″ with gain G and a feedback loop 420. The amplifier 110″ is implemented as a programmable, fully-differential amplifier as described above in connection with FIG. 1C. For example, the gain G can be adjusted to be G=1 . . . 10. In the example illustrated in FIG. 4A, a first feedback input X of the feedback loop 420 is connected to the first output O.sub.1 of the amplification system 400; a second feedback input Y of the feedback loop 420 is connected to the second input pin P.sub.2 of the integrated audio codec 405; a third feedback input W of the feedback loop 420 is connected to the second output O.sub.2 of the amplification system 400; and a feedback output of the feedback loop 420 is connected to the inverting input N.sub.1 of the amplifier 110″.

(32) The feedback loop 420 is implemented as an active integrator similar to the active integrator 120′ described above in connection with FIG. 1D. The feedback loop 420 includes an operational amplifier 422 having an open-loop gain A.sub.1. Here, the operational amplifier 422 is implemented as a fully-differential operational amplifier operated in single ended mode. Further, the feedback loop 420 includes a capacitive element 428 having a capacitance C.sub.1 that is switched with a period T.sub.S with switches Φ.sub.1 and Φ.sub.2, such that the switched capacitor 428 has an effective resistance R.sub.S=T.sub.S/C.sub.1. FIG. 4B shows that when the switches Φ.sub.1 are OFF and the switches 112 are ON, the switched capacitor 428 is connected between the third feedback input W of the feedback loop 420 and a non-inverting input of the operational amplifier 422. FIG. 4C shows that when the switches Φ.sub.1 are ON and the switches Φ.sub.2 are OFF, the switched capacitor 428 is connected between the first feedback input X of the feedback loop 420 and an inverting input of the operational amplifier 422. The above operation of the switches Φ.sub.1 and Φ.sub.2 associated with the switched capacitor 428 beneficially allows for the fully-differential operational amplifier 422 to operate in single ended mode. In this manner, a dedicated stage of the fully-differential operational amplifier 422 can be omitted and, as a consequence, area and power consumption of the integrated audio codec 405 also is saved.

(33) Note that in the examples illustrated in FIGS. 4A-4C, the second feedback input Y of the feedback loop 420 also is connected to the inverting input of the operational amplifier 422. Moreover, the feedback loop 420 also includes a capacitive element 426 having a capacitance C.sub.2 and being connected between the non-inverting input of the operational amplifier 422 and the feedback output Z of the feedback loop 420.

(34) Referring again to FIG. 4A, the microphone circuit 240 includes a FET 244 configured to convert sound signals captured by a microphone to audio signals. The FET 244 is biased by a voltage source V.sub.BIAS via a bias resistor R.sub.BIAS. The first input pin P.sub.1 of the integrated audio codec 405 is connected to a first node of the microphone circuit 240 on the drain side of the FET 244, and the second input pin P.sub.2 of the integrated audio codec 405 is connected to a second node of the microphone circuit 240 on the source side of the FET 244 (which, here, it is connected to ground.) In this manner, there is a finite (non-zero) DC voltage bias U between the first input voltage V.sub.in1(t) and the second input voltage V.sub.in2(t) which depends at least on combination of a value of the voltage source V.sub.BIAS and a value of the bias resistor R.sub.BIAS. Because this combination can vary between different types/brands of microphones, the DC voltage bias U between the first input voltage V.sub.in1(t) applied at the first input pin P.sub.1 of the integrated audio codec 405 and the second input voltage V.sub.in2(t) applied at the second input pin P.sub.2 of the integrated audio codec 405 is treated as an unknown DC component U of the first input voltage V.sub.in1(t).

(35) A transfer function of the amplification system 400 having the amplifier 110″ with programmable gain G and the feedback loop 420 implemented as an active integrator—with the switched capacitor 428 and the capacitive element 426—can be expressed as:

(36) $\begin{array}{cc}\frac{V_{\mathrm{out},\mathrm{diff}}}{V_{\mathrm{in},\mathrm{se}}}=\frac{\mathrm{sG}}{s+\frac{{\mathrm{GC}}_I}{T_S{C}_2}}.& \left(4\right)\end{array}$

(37) Equation (4) indicates that the transfer function of the amplification system 400 is zero at DC (for s=0) and has a pole at GC.sub.1/T.sub.SC.sub.2. As such, the amplification system 400 having a transfer function given by Equation (4) operates like an active high pass filter with a cutoff frequency f.sub.C=GC.sub.1/T.sub.SC.sub.2. As the gain G of the programmable gain amplifier 110″ can be changed in a programmable manner, the product GC.sub.1 must be maintained constant in order for the cutoff frequency f.sub.C of the amplification system 400 to remain constant. This can be accomplished by using a switch capacitor 428 with adjustable capacitance C.sub.1.

(38) As described above in connection with FIG. 1A, the feedback loop 420 low-pass filters the amplified differential voltage V.sub.out1(t)-V.sub.out2(t) issued by the amplification system 400 at differential outputs O.sub.1 and O.sub.2 to generate a filtered signal that includes only components with frequencies less than the cutoff frequency f.sub.C. As the amplification system 400 is applied here to audio signals, the cutoff frequency is between 20-200 Hz. The filtered signal is provided by the feedback loop 420 through the feedback output Z at the inverting input N.sub.1 of the amplifier 110″. As noted above, the feedback loop 420 is implemented as an active integrator. As the active integrator continues to integrate the signals input at the feedback inputs X, Y and W of the feedback loop 420, a DC component V.sub.N1 of the filtered signal provided, by the feedback loop 420 through the feedback output Z, at the inverting input N.sub.1 of the amplifier 110″ continues to increase until it reaches a value equal to the unknown DC component U of the first input voltage V.sub.in1(t) applied at the first input pin P.sub.1 of the integrated audio codec 405. Once V.sub.N1 reached the value U, the unknown DC component U at the non-inverting input of the amplifier 110″ is counterbalanced by the DC component V.sub.N1≈U at the inverting input of the amplifier 110″. From there on, the DC component V.sub.N1 will remain constant at the value U, and the amplifier 110″ will amplify only components of the input signal that have finite frequencies, f≠0.

(39) In this manner, as the amplification system 400 operates as an active high pass filter, an offset of the feedback loop 420 is, advantageously, not critical and, hence, the only constraint of the amplification system 400 is a dynamic range of the amplifier 110″. Moreover, because a portion of the input signal V.sub.inP1(t)-V.sub.inP2(t) that includes components with frequencies larger than the cutoff frequency f.sub.C is blocked by (and, thus, does not go through) the feedback loop 420, the requirement that the feedback loop 420 operates in a linear regime can be removed. Beneficially, this allows use of smaller and less expensive components for the feedback loop 420. For example, the capacitive element 426 can be implemented as a metal-oxide-semiconductor (MOS) capacitor in the feedback loop 420. Although MOS capacitors have less linear characteristics than metal-oxide-metal (MOM) capacitors, MOS capacitors are smaller than MOM capacitors. In this manner, the extra silicon area of the feedback loop 420 and the extra cost added by the feedback loop 420 to the integrated audio codec 405 relative to the area and cost of the conventional integrated audio codec 305 can be kept below threshold values.

(40) Noise provided by the feedback loop 420 to the non-inverting input N.sub.1 of the amplifier 110″ has a contribution from the operational amplifier 422 and a k.sub.BT/C.sub.2 contribution.

(41) As the operational amplifier 422 has a unitary transfer function, its noise contribution can be mitigated by using a low noise operational amplifier for which the total noise integrated between the cutoff frequency f.sub.C and a maximum frequency f.sub.MAX of a frequency range [f.sub.C, f.sub.MAX] of interest is less than a maximum acceptable noise value of 2μ V.sub.RMS, for instance. As the amplification system 400 is used to amplify voice signals received from the microphone circuit 240, when the audio signals include an unknown DC, the frequency range [f.sub.C, f.sub.MAX] of interest is a voice frequency range starting at about 200 Hz and extending up to 8 kHz, for instance.

(42) The k.sub.BT/C noise contribution introduced by the feedback loop 420 is given by

(43) $\begin{array}{cc}{V}_{n,\mathrm{input}}^2=\frac{2k_{B}T}{\pi C_{2}G}{\int }_{\frac{2f_1\pi T_S{C}_2}{C_1}}^{\frac{2f_2\pi T_S{C}_2}{C_1}}\frac{\mathrm{dt}}{G\left(1+d-d\cos \left(\frac{C_{1}t}{C_2}\right)\right)},& \left(5\right)\end{array}$
where parameter d is given by

(44) $\begin{array}{cc}d=\frac{2C}{C_{1}G}+2{\left(\frac{C}{C_{1}G}\right)}^2.& \left(6\right)\end{array}$

(45) Note that if the integration in Equation (5) is performed from DC (f.sub.1=0) to very large frequencies (f.sub.2.fwdarw.∞), then the noise value is (1/G)(k.sub.BT/C.sub.2). As such, the k.sub.BT/C noise contribution can be mitigated by using a minimum capacitance C.sub.2 for which this noise contribution is less than a maximum acceptable noise value in a range of 2-5μ V.sub.RMS. Using the Equations (5) and (6) for the configuration of the feedback loop 420 illustrated in FIG. 4A, the capacitance C.sub.2 of the capacitive element 426 is found to be in a range of 10-45 pF.

(46) To avoid noise contributions to the output signal V.sub.out1(t)-V.sub.out2(t) due to switching the switched capacitor 428 at a switching frequency 1/T.sub.S, the latter can be set ten times larger than the maximum frequency f.sub.MAX of the audio range of interest. For example, because here f.sub.MAX for the voice frequency range is 8 kHz, the switching frequency 1/T.sub.S is chosen to be 80 kHz.

(47) The capacitance C.sub.1 of the switched capacitor 428 is determined based on the cutoff frequency f.sub.C of the amplification system 400 (e.g., 25 Hz), the capacitance C.sub.2 found above using the Equations (5) and (6) (e.g., 45 pF), the switching frequency 1/T.sub.S (e.g., 80 kHz), and the adjustable gain G (e.g., 1 . . . 10) of the amplifier 110″. In this manner, the capacitance C.sub.1=f.sub.CT.sub.SC.sub.2/G of the switched capacitor 428 is in the range of 8 . . . 80 fF. As the cutoff frequency f.sub.C has to remain constant, the product GC.sub.1 is kept constant. So, large values of the gain G (e.g., 10) correspond to small values of the capacitance C.sub.1 (e.g., 8 fF), and small values of the gain G (e.g., 1) correspond to larger values of the capacitance C.sub.1 (e.g., 80 fF).

(48) Note that an equivalent resistance R.sub.S of the active integrator implemented by the feedback loop 420 is larger than 500 MΩ. For instance, if the cutoff frequency f.sub.C=20 Hz, the capacitance which determines the noise contributed by the feedback loop 420 is C.sub.2=45 pF and the gain of the amplifier 110″ is G=10, then the equivalent resistance R.sub.S is 1.5 GΩ. A resistor having such a large resistance requires a very large area and would increase the overall silicon area of an active integrator. Hence, the feedback loop 420 is implemented with a switched capacitor 428 having a capacitance C.sub.1=8 fF. Such a small switched capacitor 428, even together with the two switches Φ.sub.1 and two switches Φ.sub.2, advantageously requires a much smaller area than a single resistor with resistance of 1.5 GΩ.

(49) A key advantage of the disclosed technologies is that the amplification system 400 of the integrated audio codec 405 can operate like an active high pass filter with a cutoff frequency f.sub.C 25 Hz while causing an overall reduction of an area of the portion of the mobile device 401—which includes the integrated audio codec 405 DC-coupled to an audio signal source—relative to the corresponding portion of the mobile device 301—which includes the conventional integrated audio codec 305 AC-coupled to the audio signal source via external capacitors C.sub.E1 and C.sub.E2. This overall area reduction is due to the fact that extra silicon area added by the feedback loop 420 to the integrated audio codec 405 is smaller than an area saved from the portion of the mobile device 401, where the saved area corresponds to a portion of the circuit board 306 occupied by the external capacitors C.sub.E1 and C.sub.E1 required by the conventional integrated audio codec 305.

(50) In the example illustrated in FIG. 4A, the integrated audio codec 405 further includes a microphone detection circuit 460. The microphone detection circuit 460 is configured to compare an unknown DC component U of the input voltage V.sub.inP1(t) applied at the first input pin P.sub.1 of the integrated audio codec 405 to a target bias voltage V.sub.T. Detection of the unknown DC component U by the microphone detection circuit 460 at the first input pin P.sub.1—which is connected to the non-inverting input of the amplifier system 400—is used by the integrated audio codec 405 to infer whether the microphone circuit 240 is connected to the integrated audio codec 405. A power state of the amplification system 400 can be controlled based on such inference. For example, when the amplifier 110″, the feedback circuit 420 or both are in a powered-OFF state, if the unknown DC component U detected by the microphone detection circuit 460 at the first input pin P.sub.1 meets the target bias voltage V.sub.T, then the amplifier 110″, the feedback circuit 420 or both are turned ON. As another example, when the amplifier 110″, the feedback circuit 420 or both are in a powered-ON state, if the unknown DC component U detected by the microphone detection circuit 460 at the first input pin P.sub.1 does not meet the target bias voltage V.sub.T, then the amplifier 110″, the feedback circuit 420 or both are turned OFF.

(51) As the microphone detection circuit 460 detects the unknown DC component U of the input voltage V.sub.inP1(t) at the first input pin P.sub.1, the integrated audio codec 405 can have one fewer pins than the conventional integrated audio codec 305 in which the microphone detection circuit requires its own dedicated pin P.sub.D. As the integrated audio codec 405 has one fewer pins than the conventional integrated audio codec 305, an area of the circuit board 306 occupied by a pad associated with the dedicated pin P.sub.D can be further saved from the overall area of the mobile device 401 which includes the integrated audio codec 405 DC-coupled to an audio signal source.

(52) FIG. 5 is a flow chart showing an example of a process 500 for amplifying a signal that includes an unknown DC component. The process 500 can be implemented, for example, using any of the amplification systems 100, 200 or 400 described above in connection with FIGS. 1A, 2 and 4A.

(53) At 510, a signal that includes an unknown DC component is received by an amplifier. In examples illustrated in FIGS. 2 and 4A, the signal is an audio signal having frequencies in the range of 200 Hz to 20 kHz.

(54) At 520, an amplified signal issued at an output of the amplifier is low pass filtered, with respect to a cutoff frequency f.sub.C, by a feedback circuit connected between the output of the amplifier and an input of the amplifier, to generate a filtered signal with frequencies less than the cutoff frequency f.sub.C. In some implementations, the cutoff frequency f.sub.C with respect to which the low pass filtering is performed is less than a lower bound of a frequency spectrum of the received signal. For instance, if the received signal is a voice audio signal with frequencies in a frequency range of [200 Hz, 20 kHz] like in the examples illustrated in FIGS. 2 and 4A, then the cutoff frequency is chosen to be f.sub.C=20 Hz.

(55) At 530, the filtered signal is injected, by the feedback circuit, into the input of the amplifier to cancel the unknown DC component below the cutoff frequency f.sub.C. Here, a ratio of noise generated by the feedback circuit to a portion of the received signal having frequencies above the cutoff frequency f.sub.C can be maintained by the feedback circuit below a predetermined ratio value. In the example illustrated in FIG. 4A, this is accomplished by sizing an integrator capacitance of the feedback circuit at a minimum value (e.g., C.sub.2=45 pF for the feedback loop 420 of the integrated audio codec 405.) Further, a switched capacitor of the feedback circuit can be switched at frequencies larger by a predetermined factor than an upper bound of a frequency spectrum of the received signal. In the example illustrated in FIG. 4A, if the received signal is a voice audio signal with frequencies in a frequency range of [200 Hz, 8 kHz], then the switched capacitor C.sub.1 is switched at a frequency f.sub.S=1/T.sub.S=80 kHz.

(56) In some implementations, a differential amplified signal can be issued at differential outputs of the amplifier. Here, the differential amplified signal can be converted to a digital signal by an analog-to-digital convertor.

(57) FIG. 6 is a flow chart showing an example of a process 600 for controlling power to, at least, a portion of an integrated audio codec that executes the process 500. The process 600 can be implemented using the integrated audio codec 405 described above in connection with FIG. 4A.

(58) At 610, when an amplifier and a feedback circuit of an integrated audio codec are in a powered-ON state, the amplifier and the feedback circuit are powered OFF. Alternatively, when the amplifier and the feedback circuit are in a powered-OFF state, the powered-OFF state of the amplifier and the feedback circuit is maintained.

(59) At 620, an unknown DC component U is determined by a bias detector of the integrated audio codec. In the example illustrated in FIG. 4A, the bias detector is implemented as a microphone detection circuit 460 of the integrated audio codec 405. Advantageously, the microphone detection circuit 460 detects the unknown DC component U at the same pin at which an input signal which contains the unknown DC component is applied. In this manner, a dedicated pin for detecting the unknown DC component is not required by the integrated audio codec 405.

(60) At 630, the detected unknown DC component is compared with a target DC voltage V.sub.T. In some implementations, the target DC voltage V.sub.T is a maximum allowed bias voltage. In other implementations, the target DC voltage V.sub.T is a minimum required bias voltage. In some other implementations, the target DC voltage V.sub.T is a desired range of bias voltages.

(61) If the detected unknown DC component meets the target DC voltage, then, at 640, when the amplifier, the feedback circuit or both are in a powered-ON state, the powered-ON state of the amplifier and the feedback circuit is maintained. Alternatively, at 640, when the amplifier, the feedback circuit or both are in a powered-OFF state, the amplifier and the feedback circuit are powered ON.

(62) At 650, the process 500 is being performed. Once the operations of the process 500 are completed, the process 600 is iterated starting at 630.

(63) Else, if the detected unknown DC component does not meet the target DC voltage, the process 600 is iterated starting at 610.

(64) A few embodiments have been described in detail above, and various modifications are possible. The disclosed subject matter, including the functional operations described in this specification, can be implemented in electronic circuitry, computer hardware, firmware, software, or in combinations of them, such as the structural means disclosed in this specification and structural equivalents thereof, including system on chip (SoC) implementations, which can include one or more controllers and embedded code.

(65) While this specification contains many specifics, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

(66) Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments.

(67) Other embodiments fall within the scope of the following claims.