Method for Detecting Depth of Vertical Gate of Transfer Transistor of CMOS Image Sensor

Abstract

The disclosure discloses a method for detecting the depth of a vertical gate of a transfer transistor of a CMOS image sensor. The effective electrical thickness of planar gate polysilicon of a transfer transistor of a reference CMOS image sensor is obtained through a planar test, the capacitance of a vertical gate structure of a transfer transistor of a to-be-tested CMOS image sensor is obtained through a vertical test, and then the equivalent depth of the vertical gate of the transfer transistor of the to-be-tested CMOS image sensor is calculated accordingly. The depth of the gates of the transfer transistors of all CMOS image sensors can be monitored on line without damaging a silicon wafer, it is conducive to finding the abnormality of the depth of the gates of the transfer transistors in time, and the product quality of the CMOS image sensor can be effectively monitored.

Claims

1. A method for detecting the depth of a vertical gate of a transfer transistor of a CMOS image sensor, vertical gate polysilicon of a transfer transistor of a to-be-tested CMOS image sensor comprising a flat portion and n vertical columns, n being a positive integer; the flat portion being formed on the surface of a first type doped epitaxial layer; the upper ends of the n vertical columns being connected with the flat portion and being formed in the first type doped epitaxial layer, wherein the method comprises the following steps: 1) detecting the effective electrical thickness EOT of planar gate polysilicon of a transfer transistor of a reference CMOS image sensor, the gate polysilicon of the transfer transistor of the reference CMOS image sensor being formed on the surface of the first type doped epitaxial layer and having the same cross-sectional shape as the flat portion of the vertical gate polysilicon of the transfer transistor of the to-be-tested CMOS image sensor; detecting the capacitance C.sub.ox(VTG) of a vertical gate structure of the transfer transistor of the to-be-tested CMOS image sensor; 2) calculating the depth H of the vertical gate of the transfer transistor of the to-be-tested CMOS image sensor, $H=\frac{\left[\frac{C_{\mathrm{ox}\left(VTG\right)}*\mathrm{EOT}}{{\mathrm{.Math.}}_0{\mathrm{.Math.}}_r}-W\right)]}{w*n};$ where ε.sub.0 is a vacuum dielectric constant; ε.sub.r is a relative dielectric constant; W is the cross-sectional area of the flat portion; w is the cross-sectional area of one vertical column of the vertical gate polysilicon.

2. The method for detecting depth of the vertical gate of the transfer transistor of the CMOS image sensor according to claim 1, wherein the cross section of the flat portion is rectangular.

3. The method for detecting depth of the vertical gate of the transfer transistor of the CMOS image sensor according to claim 1, wherein the cross section of the flat portion is square.

4. The method for detecting depth of the vertical gate of the transfer transistor of the CMOS image sensor according to claim 1, wherein w=2π*r, each vertical column of the vertical gate polysilicon is cylindrical, and r is the cross-sectional radius of each cylindrical vertical column of the vertical gate polysilicon.

5. The method for detecting depth of the vertical gate of the transfer transistor of the CMOS image sensor according to claim 1, wherein n is 7, 8, 9 or 10.

6. The method for detecting depth of the vertical gate of the transfer transistor of the CMOS image sensor according to claim 1, wherein the n vertical columns are uniformly formed in the first type doped epitaxial layer.

7. The method for detecting depth of the vertical gate of the transfer transistor of the CMOS image sensor according to claim 1, wherein the CMOS image sensor comprises a photodiode, a transfer transistor, a floating diffusion region and a reset transistor which are adjacent sequentially; the photodiode comprises a second conducting type photosensitive doped region formed at the top of the first type doped epitaxial layer; a first conducting type doped pinned layer is formed on the surface of the second conducting type photosensitive doped region; the floating diffusion region is formed in a first type doped well; a gate structure of the transfer transistor is formed at the top of the first type doped epitaxial layer between the floating diffusion region and the photodiode.

8. The method for detecting depth of the vertical gate of the transfer transistor of the CMOS image sensor according to claim 7, wherein the CMOS image sensor further comprises a resetting region; a gate structure of the reset transistor is formed between the floating diffusion region and the resetting region; the floating diffusion region and the resetting region are formed in the first type doped well; the resetting region is subjected to second conducting type doping; the resetting region is configured to connect with power supply voltage; a gate of an amplify transistor is connected with the floating diffusion region, a source outputs an amplified signal, and a drain is connected with the power supply voltage; a select transistor is configured to select and output the amplified signal output by the amplify transistor; a gate of the select transistor is connected with a select signal.

9. The method for detecting depth of the vertical gate of the transfer transistor of the CMOS image sensor according to claim 8, wherein the first conducting type is N-type, and the second conducting type is P-type; or the first conducting type is P-type, and the second conducting type is N-type.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly describe the technical solution of the disclosure, the drawings which need be used in the disclosure will be briefly introduced below. Apparently, the drawings described below are just some embodiments of the disclosure. Those skilled in the art may obtain other drawings according to these drawings without contributing any inventive labor.

[0035] FIG. 1 is a basic structure of a 4T CMOS image sensor.

[0036] FIG. 2 is a schematic view of electron transfer after a transfer transistor is turned on in a

[0037] CMOS image sensor with a planar gate transfer transistor.

[0038] FIG. 3 is a schematic view of electron transfer after a transfer transistor is turned on in a

[0039] CMOS image sensor with a small-size vertical gate transfer transistor.

[0040] FIG. 4 is a schematic view of a CMOS image sensor with a large-size vertical gate transfer transistor.

[0041] FIG. 5 is a cross-sectional schematic view of a planar gate transfer transistor.

[0042] FIG. 6 is a three-dimensional schematic view of a planar gate transfer transistor.

[0043] FIG. 7 is a cross-sectional schematic view of a vertical gate transfer transistor.

[0044] FIG. 8 is a three-dimensional schematic view of a vertical gate transfer transistor.

DETAILED DESCRIPTION OF THE DISCLOSURE

[0045] The technical solution of the disclosure will be described below clearly and completely with reference to the drawings. Apparently, the described embodiments are partial embodiments of the disclosure, instead of all embodiments. Based on the embodiments of the disclosure, all other embodiments obtained by those skilled in the art without contributing any inventive labor shall fall into the scope of protection of the disclosure.

EMBODIMENT 1

[0046] The present embodiment provides a method for detecting the depth of a vertical gate of a transfer transistor of a CMOS image sensor. Referring to FIG. 7 and FIG. 8, vertical gate polysilicon of a transfer transistor of a to-be-tested CMOS image sensor includes a flat portion and n vertical columns, wherein n is a positive integer; the flat portion is formed on the surface of a first type doped epitaxial layer; the upper ends of then vertical columns are connected with the flat portion and are formed in the first type doped epitaxial layer. The method includes the following steps:

[0047] 1) The effective electrical thickness EOT of planar gate polysilicon of a transfer transistor of a reference CMOS image sensor is detected. Referring to FIG. 5 and FIG. 6, the gate polysilicon of the transfer transistor of the reference CMOS image sensor is formed on the surface of the first type doped epitaxial layer and has the same cross-sectional shape as the flat portion of the vertical gate polysilicon of the transfer transistor of the to-be-tested CMOS image sensor.

[0048] The capacitance C.sub.ox(VTG) of a vertical gate structure of the transfer transistor of the to-be-tested CMOS image sensor is detected;

[0049] 2) The depth H of the vertical gate of the transfer transistor of the to-be-tested CMOS image sensor is calculated.

[00002]$\begin{array}{cc}H=\frac{\left[\frac{C_{\mathrm{ox}\left(VTG\right)}*\mathrm{EOT}}{{\mathrm{.Math.}}_0{\mathrm{.Math.}}_r}-W\right)]}{w*n}& \left(\mathrm{formula}1\right)\end{array}$

[0050] where ε.sub.0 is a vacuum dielectric constant; ε.sub.r is a relative dielectric constant; W is the cross-sectional area of the flat portion; w is the cross-sectional area of one vertical column of the vertical gate polysilicon.

[0051] The effective electrical thickness EOT of the planar gate polysilicon of the transfer transistor of the reference CMOS image sensor can be conveniently obtained through a test.

[0052] The capacitance C.sub.ox(VTG) of the vertical gate structure of the transfer transistor of the to-be-tested CMOS image sensor can be conveniently obtained through a test.

[00003]$\begin{array}{cc}{S}_{total}=W+w*H*n,& \left(\mathrm{formula}2\right);\\ \mathrm{EOT}=\frac{{\mathrm{.Math.}}_0{\mathrm{.Math.}}_{r}W}{C_{ox\left(bulk\right)}},& \left(\mathrm{formula}3\right);\\ C_{ox\left(VTG\right)}=\frac{{\mathrm{.Math.}}_0{\mathrm{.Math.}}_r{S}_{total}}{EOT},& \left(\mathrm{formula}4\right)\end{array}$

[0053] where S.sub.total is a sum of surface area of the flat portion and all vertical columns, which are in contact with the epitaxial layer, of the gate polysilicon of the transfer transistor of the to-be-tested CMOS image sensor;

[0054] C.sub.ox(bulk) is the capacitance of silicon oxide of the gate polysilicon with a rectangular cross section.

[0055] According to formula (2), formula (3) and formula (4), taking w=2π*r, formula 1 can be obtained.

[0056] In the method for detecting the depth of the vertical gate of the transfer transistor of the CMOS image sensor provided embodiment 1, through the combination of planar and vertical gates with the same layout area, the effective electrical thickness EOT of planar gate polysilicon of the transfer transistor of the reference CMOS image sensor is obtained through a planar test, the capacitance C.sub.ox(VTG) of the vertical gate structure of the transfer transistor of the to-be-tested CMOS image sensor is obtained through a vertical test, and then the equivalent depth of the vertical gate of the transfer transistor of the to-be-tested CMOS image sensor is calculated accordingly. The depth of the vertical gate can be effectively monitored, the depth of the gates of the transfer transistors of all CMOS image sensors can be monitored on line without damaging a silicon wafer, it is conducive to finding the abnormality of the depth of the gates of the transfer transistors in time, and the product quality of the CMOS image sensor can be effectively monitored.

EMBODIMENT 2

[0057] Based on the method for detecting the depth of the vertical gate of the transfer transistor of the CMOS image sensor provided embodiment 1, the cross section of the flat portion is rectangular.

[0058] Preferably, the cross section of the flat portion is square.

[0059] Preferably, w=2π*r , each vertical column of the vertical gate polysilicon is cylindrical, and r is the cross-sectional radius of each cylindrical vertical column of the vertical gate polysilicon.

[0060] Preferably, n is 7, 8, 9 or 10.

[0061] Preferably, the n vertical columns are uniformly formed in the first type doped epitaxial layer.

EMBODIMENT 3

[0062] Based on the method for detecting the depth of the vertical gate of the transfer transistor of the CMOS image sensor provided embodiment 1, referring to FIG. 1, the CMOS image sensor includes a photodiode (PD) 10, a transfer transistor (Tx) 11, a floating diffusion region (FD) 12 and a reset transistor (RST) 13 which are adjacent sequentially;

[0063] the photodiode 10 includes a second conducting type photosensitive doped region 101 formed at the top of the first type doped epitaxial layer 1;

[0064] a first conducting type doped pinned layer 102 is formed on the surface of the second conducting type photosensitive doped region 101;

[0065] the floating diffusion region 12 is formed in a first type doped well 17;

[0066] a gate structure of the transfer transistor 11 is formed at the top of the first type doped epitaxial layer 1 between the floating diffusion region 12 and the photodiode 10.

[0067] Preferably, the CMOS image sensor further includes a resetting region 16;

[0068] a gate structure of the reset transistor 13 is formed between the floating diffusion region 12 and the resetting region 16;

[0069] the floating diffusion region 12 and the resetting region 16 are formed in the first type doped well 17;

[0070] the resetting region 16 is subjected to second conducting type doping;

[0071] the resetting region 16 is configured to connect with power supply voltage VDD;

[0072] a gate of an amplify transistor 14 is connected with the floating diffusion region 12, a source outputs an amplified signal, and a drain is connected with the power supply voltage VDD;

[0073] a select transistor 15 is configured to select and output the amplified signal output by the amplify transistor 14;

[0074] a gate of the select transistor 15 is connected with a select signal Rs.

[0075] Preferably, the first conducting type is N-type, and the second conducting type is P-type;

[0076] or the first conducting type is P-type, and the second conducting type is N-type.

[0077] In the method for detecting the depth of the vertical gate of the transfer transistor of the CMOS image sensor provided by embodiment 3, when the transfer transistor (Tx) 11 is turned off for photosensitization, a P-N junction of the photodiode (PD) 10 captures sunlight to generate electrons and holes. Under the action of the built-in electric field of the P-N junction, the photo-generated electrons accumulate towards the top. When the gate of the transfer transistor (Tx) 11 is powered and turned on, the electrons are transmitted to the floating diffusion region 12 between the transfer transistor (Tx) 11 and the reset transistor (RST) 13 through a surface channel.

[0078] What are described above are just exemplary embodiments of the disclosure, which are not used to limit the disclosure. Any modification, equivalent replacement, improvement and the like made within the spirit and rule of the disclosure shall be included in the scope of protection of the disclosure.