OPTICAL SWITCHES AND METHODS OF REDUCING CROSS-TALK

Abstract

An optical switch with a plurality of actuators includes a controller configured to control the operation of a plurality of channels, where each channel has at least one electrical driver and at least one actuator, by interleaving periods of voltage switching output with periods of no voltage switching output for one or more drivers whilst the output voltage is switching from one level to another level. Alternatively, an optical switch with a plurality of actuators comprises a controller configured to control the operation of a plurality of channels, where each channel has at least one electrical driver and at least one actuator, by switching the output voltage from one level to another level for at least one driver of a first channel whilst at least one oilier driver of at least one other channel is in a relatively high impedance mode.

Claims

1. An optical switch with a plurality of actuators comprising a controller configured to control the operation of a plurality of channels, where each channel has at least one electrical driver and at least one actuator, by interleaving periods of voltage switching output with periods of no voltage switching output for at least one driver whilst the output voltage is switching from one level to another level.

2. An optical switch with a plurality of actuators comprising a controller configured to control the operation of a plurality of channels, where each channel has at least one electrical driver and at least one actuator, by switching the output voltage from one level to another level for at least one driver of a first channel whilst at least one other driver of at least one other channel is in a relatively high impedance mode.

3. The optical switch according to claim 2, wherein said switch comprises a plurality of other drivers which are in a relatively high impedance mode by sampling previous output values onto the channel capacitance.

4. The optical switch according to claim 1, wherein at least one non-switching driver is in a relatively high impedance mode during switching of a driver.

5. The optical switch according to claim 4, wherein at least one voltage of at least one non-switching driver is re-sampled during switching of a driver.

6. The optical switch according to claim 5, wherein the periods of switching are longer than the periods of re-sampling.

7. The optical switch according to claim 1, wherein several discrete driver circuits are integrated into a single chip.

8. The optical switch according to claim 1, wherein said actuators are piezo-electric actuators.

9. A method of reducing cross-talk in an optical switch with a plurality of channels, where each channel has at least one electrical driver and at least one actuator, the method comprising the steps of interleaving periods of voltage switching output with periods of no voltage switching output for one or more drivers whilst the output voltage is switching from one level to another level.

10. A method of reducing cross-talk in an optical switch with a plurality of channels, where each channel has at least one electrical driver and at least one actuator, the method comprising the steps of switching the output voltage from one level to another level for at least one driver of a first channel whilst at least one other driver of another channel is in a relatively high impedance mode.

11. The method according to claim 10, wherein said other drivers are in a relatively high impedance mode by sampling previous output values onto the channel capacitance.

12. The method according to claim 9, wherein at least one non-switching driver is in a relatively high impedance mode during switching of a driver.

13. The method according to claim 12, wherein at least one voltage of at least one non-switching driver is re-sampled during switching of a driver.

14. The method according to claim 13, wherein the periods of switching are longer than the periods of re-sampling.

15. The method according to claim 9, wherein several discrete driver circuits are integrated into a single chip.

16. The method according to claim 10, wherein several discrete driver circuits are integrated into a single chip.

17. The method according to claim 9, wherein each channel has at least one dedicated electrical driver.

18. The method according to claim 10, wherein each channel has at least one dedicated electrical driver.

19. The optical switch according to claim 2, wherein several discrete driver circuits are integrated into a single chip.

20. The optical switch according to claim 2, wherein said actuators are piezo-electric actuators.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0030] FIG. 1 shows a setup with several channels sharing the same supply Vs+ and ground together with typical voltages associated with a switching event occurring at channel 0.

[0031] FIG. 2 shows the measured cross-talk voltage at a single channel with 15 “nearby” channel voltages switching. The switching characteristic and the resulting cross-talk is shown for a normal switch, a staggered switch and a staggered switching with high-impedance (HI) mode during the non-switching time periods.

[0032] FIG. 3 shows the measured cross-talk voltage at a single channel while 15 “nearby” channel voltages switch using staggered switching with HI-mode. The result in case of equal switching and non-switching periods is shown together with the result of using a shorter non-switching (re-sampling) period.

DETAILED DESCRIPTION OF THE FIGURES

[0033] Certain embodiments of the invention relate to a technique of reducing the electrical cross-talk between drivers for capacitive loads (driver circuit together with capacitive load is referred to as a “channel”). More in particular the technique aims, in certain embodiments, at reducing the dynamic cross-talk on one/several driver(s) signal(s) generated by a voltage switching event on another driver(s). An embodiment of this technique comprises the following parts:

(a) A switch of the output voltage, from one voltage level to the next voltage level, of a certain driver(s) is split up into several short time periods in which the voltage output switches a part of the complete voltage interleaved with periods in which no voltage switching occurs. This type of switching is referred to as “staggered switching” and is able to lower the average dynamic electrical cross-talk.
(b) In the periods that the output voltage of a certain output driver(s) (the aggressor(s)) is switched, the output of the affected other drivers is put into high-impedance mode, effectively sampling the previous value of these other drivers onto the channel capacitance. Thus isolating the voltage of other channels from cross-talk caused by the aggressor(s).
(c) The cross-talk reduction methods mentioned in (a) and (b) can be combined into a staggered switching mode in which the non-switching drivers are put into high-impedance mode (the output is isolated from ground/supply by means of a high impedance) during switching of the voltage of a certain driver(s). In the interleaved period without switching, all drivers are put out of high-impedance mode which comes down to a re-sampling of the non-switching driver(s) voltage(s).
(d) The method described in (c) can be performed with either equally long periods of switching and re-sampling or with a difference between the time taken for the switching and re-sampling. By using a re-sampling time that is significantly shorter than the switching time, the overall switching time increases marginally in respect to a switch without any of the previously described cross-talk reduction techniques.

[0034] When multiple driver circuits, used to impose a certain voltage on a capacitive load, use the same electrical ground or supply line, dynamic cross-talk voltages can occur at a certain channel (combination of driver circuit and capacitive load) when other channels have their voltage being switched. This is caused by the non-zero impedance of the supply/ground lines which results in an error voltage when current is being sourced from the supply line or sunk into the ground line when a driver switches its output voltage. When integrating several drivers onto one chip the amount of cross-talk can become large in respect to the cross-talk of discrete driver circuits due to the typically large impedance of supply/ground lines on a chip compared to lines on a printed circuit board.

[0035] FIG. 1 shows a setup with several channels sharing the same supply Vs+ and ground. A switching event at one channel (in this case channel 0) will cause a cross-talk voltage at the channels sharing the same supply and ground lines. Typical switching and cross-talk voltage waveforms are shown to the right.

[0036] A system-level solution(s) is proposed to lower the cross-talk voltages induced by a switching driver onto a non-switching driver voltage. One solution consists of splitting the switching time into smaller time periods in which switching periods are interleaved with non-switching periods referred to as staggered switching. This allows the lowering of the average cross-talk voltage at the non-switching channels.

[0037] A second solution is to put the non-switching drivers into high-impedance mode during the time in which switching of another driver (the aggressor) occurs. This effectively samples the correct voltage onto the load capacitance of the channel which isolates the channel from cross-talk voltages. Due to leakage currents at both the driver and possibly the load (caused by a parasitic parallel resistor), the voltage at the channel will drop in time. This drop in channel voltage increases with the switching time of the aggressor and can become too large for certain cases. This is solved by using a third solution.

[0038] The third solution proposed, combines solution one and two which means that during the non-switching periods of the first solution the other non-switching channels are placed into high-impedance mode. By choosing an appropriate time for the switching periods, the drop in channel voltage can be limited. The result of using solution one and three compared to a regular switch is shown in FIG. 2.

[0039] FIG. 2 shows measured cross-talk (left y-axis) and switching voltages (right y-axis) in function of time (x-axis) for a chip with 16 integrated channel drivers of which the voltages of channels 0-7 and channels 9-15 are being switched from the supply voltage down to the ground rail while the voltage at channel 8 is being kept approximately halfway. Three different methods of switching are used, being: normal switching, staggered switching and staggered switching in which the non-switching driver (channel 8) is put into high-impedance (HI) mode during the switching of the other channels. Switching and non-switching time periods are equal in this measurement. The normal switching has the shortest switching time but also the highest average cross-talk while the average cross-talk in case of staggered switching with HI-mode is low in comparison.

[0040] In FIG. 2, a drop of the voltage at the non-switching channel can be observed for the staggered switch with HI-mode. This drop occurs during the switching of the other channels and is caused by the finite resistance at the output of the driver circuit of the non-switching channel. The drop in channel voltage Vd can then be expressed as:

[00001]$\mathrm{Vd}=\mathrm{Vs}.Math.\left(1-e^{\frac{-t}{\mathrm{RC}}}\right)$

[0041] With Vs the voltage sampled at the channel, t the time during which the non-switching channel is put into high-impedance mode, R the resistivity measured at the channel and C the capacitance of the load. By choosing a short switching time the drop in voltage can be limited however the switching time will double if the time taken for the switching and non-switching period is equal.

[0042] A fourth solution is to use the third solution with unequal switching and non-switching times which allows to limit the increase in switching time in comparison to normal switching. This reduction is achieved by making the non-switching (re-sampling) time significantly smaller than the switching time which is shown in FIG. 3.

[0043] FIG. 3 shows measured cross-talk (left y-axis) and switching voltages (right y-axis) in function of time (x-axis) for a chip with 16 integrated channel drivers of which the voltages of channels 0-7 and channels 9-15 are being switched from the supply voltage down to the ground rail while the voltage at channel 8 is being kept approximately halfway. Staggered switching with HI-mode is used for the two measurements with one measurement showing the result of using equal switching and non-switching time periods and the other depicting the result in case of a shorter non-switching (re-sampling) time period. Both cases show similar cross-talk voltages, however, the use of a shorter non-switching time period can lead to significant shorter switch times (roughly 8 ms instead of 12 ms).