PHASE DETECTION METHOD BASED ON A PLURALITY OF CONSECUTIVE VALUES OF A RECEIVING SIGNAL

Abstract

The invention relates to a phase detection method (200), comprising the following steps: receiving a plurality of consecutive values of a receiving signal (Y) with a known sampling frequency f.sub.s as a reaction to a transmitting signal having a known transmitting frequency f.sub.w; determining two differential values (ΔY1, ΔY2), each coming from two consecutive values out of three consecutive values (Y1, Y2, Y3) of the receiving signal (Y); and determining a phase real part (U) and a phase imaginary part (V) of the receiving signal (Y) based on a linear relation between the phase real part (U), the phase imaginary part (V) and the two differential values (ΔY1, ΔY2).

Claims

1. A phase detection method comprising the following steps: receiving a plurality of consecutive values of a receiving signal (Y) with a known sampling frequency f.sub.s as a reaction to a transmitting signal with a known transmitting frequency f.sub.w; determining two differential values (ΔY1, ΔY2), each coming from two consecutive values out of three consecutive values (Y1, Y2, Y3) of the receiving signal (Y); and determining a phase real part (U) and a phase imaginary part (V) of the receiving signal (Y) based on a linear relation between the phase real part (U), the phase imaginary part (V) and the two differential values (ΔY1, ΔY2).

2. The phase detection method according to claim 1, wherein the linear relation between the phase real part (U), the phase imaginary part (V) and the two differential values (ΔY1, ΔY2) can be represented by a two-dimensional linear system of equations based on the two differential values (ΔY1, ΔY2) as input variables and the phase real part (U) and the phase imaginary part (V) as output variables.

3. The phase detection method according to claim 2, wherein the linear system of equations is solved by weighting of the input variables with Fourier Coefficients based on a known circular frequency Ω, wherein said known circular frequency Ω depends on the transmitting frequency f.sub.w and the sampling frequency f.sub.s.

4. The phase detection method according to claim 3, wherein the known circular frequency Ω satisfies the following condition: Ω=2π(f.sub.w/f.sub.s).

5. The phase detection method according to claim 3, including determining the Fourier Coefficients in dependence of the known circular frequency Ω before determining, the phase real part (U) and the phase imaginary part (V) of the receiving signal (Y).

6. The phase detection method according to claim 1 including determining a bias (β) of the receiving signal (Y) based on a linear relation between the phase real part (U), the phase imaginary part (V), the bias (β), and the three consecutive values (Y1, Y2, Y3) of the receiving signal (Y).

7. A processor for determining a phase of a receiving signal (Y) received as a reaction to a transmitting signal with a known transmitting frequency f.sub.w, said receiving signal (Y) having a known sampling frequency f.sub.s, said processor comprising: a first input register, a second input register, and a third input register, each input register being configured for storing one of three consecutive values (Y1, Y2, Y3) from a plurality of consecutive values of the receiving signal (Y) one after the other; a first internal register and a second internal register, each of which being configured for storing either a first differential value (ΔY1) as a difference of the content (Y2) of the second input register and the content (Y1) of the first input register or a second differential value (ΔY2) as a difference of the content (Y3) of the third input register and the content (Y2) of the second input register; a first output register and a second output register, each of which being configured for providing either a phase real part (U) or a phase imaginary part (V) of the receiving signal (Y); and a computing unit configured for determining the phase real part (U) and the phase imaginary part (V) of the receiving signal (Y) based on a linear relation between the phase real part (U), the phase imaginary part (V), and the two differential values (ΔY1, ΔY2).

8. The processor according to claim 7 including a third output register configured for providing a bias (β) of the receiving signal (Y), wherein the computing unit is configured for determining the bias (β) of the receiving signal (Y) based on a linear relation between the phase real part (the phase imaginary part (V), the bias (β) and the three consecutive values (Y1, Y2, Y3) of the receiving signal (Y).

9. The processor according to claim 8 including a first coefficient register, a second coefficient register, a third coefficient register, and a fourth coefficient register, each of which being configured for storing Fourier Coefficients, wherein said Fourier Coefficients determine a linear relation between the phase real part (U), the phase imaginary part (V), and the two differential values (ΔY1, ΔY2).

10. The processor according to claim 9 including a first parameter memory, a second parameter memory, a third parameter memory, and a fourth parameter memory, said first parameter memory being configured for storing a cosine (hC) of a half of a known circular frequency Ω, which depends on the transmitting frequency f.sub.w and the sampling frequency f.sub.s, said second parameter memory being configured for storing a sine (hS) of the half of the known circular frequency Ω, said third parameter memory being configured for storing a cosine (wC) of the known circular frequency Ω, and said fourth parameter memory being configured for storing a sine (wS) of the known circular frequency Ω.

11. The processor according to claim 10, wherein the known circular frequency Ω satisfies the following condition: Ω=2π(f.sub.w/f.sub.s).

12. The processor according to claim 10, wherein the computing unit is configured for determining the phase real part (U) and the phase imaginary part (V) of the receiving signal (Y) based on the contents (C1, S1, C2, S2) of the four coefficient registers and the contents (hC, hS, wC, wS) of the four parameter memories.

13. The processor according to claim 12 including an instruction unit configured for initializing the first coefficient register with the content (hC) of the first parameter memory and for initializing the second coefficient register with the content (hS) of the second parameter memory in response to a reset signal, and for renewing the first coefficient register with the content (C2) of the third coefficient register and for renewing the second coefficient register with the content (S2) of the fourth coefficient register in response to a clock signal, wherein the instruction unit is configured for loading the fourth coefficient register with the value C.sub.1wS+S.sub.1wC and for loading the third coefficient register with the value C.sub.1wC−S.sub.1wS in response to the clock signal, wherein wS denotes the content of the fourth parameter memory, wC denotes the content of the third parameter memory, C.sub.1 denotes the content of the first coefficient register, S.sub.1 denotes the content of the second coefficient register, and Ω denotes the known circular frequency Ω=2π(f.sub.w/f.sub.s), wherein the computing unit is configured for determining the phase real part (U) as $\frac{\Delta .Math..Math.Y_1.Math.S_2-\Delta .Math..Math.Y_2.Math.S_1}{4.Math.\mathrm{hS}.Math.\mathrm{hS}.Math.\mathrm{hC}}$ and the phase imaginary part (V) as $\frac{\Delta .Math..Math.Y_1.Math.C_2-\Delta .Math..Math.Y_2.Math.C_1}{4.Math.\mathrm{hS}.Math.\mathrm{hS}.Math.\mathrm{hC}},$ wherein hS denotes the content of the second parameter memory, hC denotes the content of the first parameter memory, C.sub.2 denotes the content of the third coefficient register, S.sub.2 denotes the content of the fourth coefficient register, and Ω denotes the known circular frequency Q=2π(f.sub.w/f.sub.w).

14. The processor according to claim 13, wherein the computing unit is configured for determining the bias (β) as Y.sub.2−(S.sub.1hC+C.sub.1hS)+V.Math.(C.sub.1hC−S.sub.1hS)), wherein U denotes the phase real part, V denotes the phase imaginary part, and Y.sub.2 denotes the content of the second input register.

15. The processor according to claim 12 including a first auxiliary register, a second auxiliary register, and a counter incremented at every renewal of the three input registers depending on the clock signal, wherein the computing unit is configured for determining the phase real part (U) as ΔY.sub.1S.sub.2−ΔY.sub.2S.sub.1 and the phase imaginary part (V) as ΔY.sub.1C.sub.2−ΔY.sub.2C.sub.1, for adding the phase real part (U) to the first auxiliary register and for adding the phase imaginary part (V) to the second auxiliary register, wherein the instruction unit is configured for outputting the values (AU, AV) of the two auxiliary registers divided by the value 2.Math.wS.Math.hS=4hS.Math.hS.Math.hC and divided by a value (cnt) of the counter in response to an interruption signal, wherein ΔY.sub.1 denotes the content of the first internal register, ΔY.sub.2 denotes the content of the second internal register, C.sub.2 denotes the content of the third coefficient register, S.sub.2 denotes the content of the fourth coefficient register, hS denotes the content of the second parameter memory and hC denotes the content of the first parameter memory, and Ω denotes the known circular frequency Ω=2π(f.sub.w/f.sub.s).

Description

[0043] Further embodiments are described by way of reference to the attached drawings. In the figures,

[0044] FIG. 1 shows a schematic view of a system 100 for measuring phase relations of acoustic waves in a vessel 102;

[0045] FIG. 2 shows a schematic view of a phase detection method 200 according to an embodiment;

[0046] FIG. 3 shows a schematic view of a processor 300 for determining a phase of a receiving signal according to a first embodiment;

[0047] FIG. 4 shows a schematic view of a processor 400 for determining a phase of a receiving signal according to a second embodiment.

[0048] The following detailed description refers to the enclosed drawings, said drawings forming a part thereof and showing specific embodiments of implementing the invention for illustrative purposes. It is understood that other embodiments can also be used and structural or logical changes can be made without deviating from the concept of the present invention. The following detailed description is therefore not to be understood in a limiting sense. Moreover, it is understood that the features of the different exemplary embodiments described herein can be combined with each other, unless something else is specifically indicated.

[0049] The aspects and embodiments are described with reference to the drawings, with identical reference numbers generally referring to identical elements. In the following description, numerous specific details are described for the purpose of explaining the invention in order to enable thorough understanding of one or more aspects of the invention. However, it can be obvious to a skilled person that one or more aspects or embodiments can be implemented by a lesser degree of the specific details. In other cases, known structures and elements are shown in a schematic form in order to facilitate describing one or more aspects or embodiments. It is understood that other embodiments can be used and structural or logical changes can be implemented without deviating from the concept of the present invention.

[0050] Albeit a certain feature or a certain aspect of an embodiment regarding only one of several implementations may have been disclosed, such a feature or such an aspect can furthermore be combined with one or more other features or aspects of the other implementations, as may be desired or advantageous for any given or specific use. Furthermore, expressions such as “contain”, “have”, “with” or other variations thereof as used in the description or the claims are to be understood in an inclusive sense, like the meaning of “comprise”. The expressions “coupled” and “connected” may have been be used in conjunction with its derivatives. It is understood that such expressions are used for indicating that two elements cooperate or interact with each other independently of whether they are in direct physical or electric contact with each other or whether they are not in direct contact with each other. Moreover, the expressions “such as” and “for example” are to be understood merely as referring to an exemplary embodiment instead of a description of the best or the ideal embodiment. The following description is therefore not to be understood in a limiting sense.

[0051] FIG. 2 shows a schematic view of a phase detection method 200 according to an embodiment. The method 200 comprises receiving 201 a plurality of consecutive values of a receiving signal Y with a known sampling frequency f.sub.s as a reaction to a transmitting signal with a known transmitting frequency f.sub.w. The method 200 comprises determining 202 two differential values ΔY1, ΔY2 from two consecutive values out of three consecutive values Y1, Y2, Y3 of the receiving signal Y in each case. The method 200 comprises determining 203 a phase real part U and a phase imaginary part V of the receiving signal Y based on a linear relation between the phase real part U, the phase imaginary part V and the two differential values ΔY1, ΔY2.

[0052] The linear relation between the phase real part U, the phase imaginary part V and the two differential values ΔY1, ΔY2 can be represented by a two-dimensional linear system of equations based on the two differential values ΔY1, ΔY2 as input variables and the phase real part U and the phase imaginary part V as output variables.

[0053] The linear system of equations can be solved by weighting of the input variables with Fourier Coefficients based on a known circular frequency Ω, said known circular frequency Ω depending on the transmitting frequency and the sampling frequency.

[0054] The known circular frequency Ω can satisfy the condition Ω=2π(f.sub.w/f.sub.s).

[0055] The Fourier Coefficients can be identified before determining the phase real part U and the phase real part (V) of the receiving signal (Y) in dependence of the known circular frequency Ω.

[0056] A bias β of the receiving signal can be determined based on a linear relation between the phase real part U, the phase imaginary part V, the bias β and the three consecutive values Y1, Y2, Y3 of the receiving signal Y.

[0057] The following representation describes the theoretic principles of the method 200.

[0058] Three values Y.sub.0, Y.sub.1, Y.sub.2 of a function

Y(τ)=β+A sin(2π.Math.f.sub.wτ+φ)  (4)

are given, comprising the unknown parameters A, β and φ and the known transmitting frequency f.sub.w. The three values Y.sub.0, Y.sub.1, Y.sub.2 were measured at three equidistant points of time

τ.sub.1,τ.sub.2 and τ.sub.3  (5)

so that the following applies:

[00004]$\begin{array}{cc}\mathrm{\Delta \tau }={\tau }_2-{\tau }_1={\tau }_3-{\tau }_2<\frac{1}{2.Math.f_w}.& \left(6\right)\end{array}$

[0059] This condition (6) ensures (in the case of an absolute measuring accuracy) an exact reconstruction of the values

U=A cos(φ) and  (7a)

V=A sin(φ)  (7b)

and thus also of the values

A=√{square root over (U.sup.2+V.sup.2)} and  (8a)

φ=(arcsin(V/A)mod 2π).  (8b)

[0060] The values U and V solve the following linear system of equations:

Y.sub.1=U.Math.S.sub.1+V.Math.C.sub.1+β

Y.sub.2=U.Math.S.sub.2+V.Math.C.sub.2+β,

Y.sub.3=U.Math.S.sub.3+V.Math.C.sub.3+β  (9)

wherein the following applies:

S.sub.j=sin(2π.Math.f.sub.w.Math.τ.sub.j),jε{1,2,3}  (10a)

C.sub.j=cos(2π.Math.f.sub.w.Math.τ.sub.j),jε{1,2,3}.  (10b)

[0061] After a few simple modifications, the system of equations (9) can be represented as follows:

[00005]$\begin{array}{cc}\begin{array}{c}{Y}_2-Y_1=U.Math.\left(S_2-S_1\right)+V.Math.\left(C_2-C_1\right)=2.Math.\sin \left(\frac{\Omega }{2}\right).Math.\left(U.Math.{\hat{C}}_1-V.Math.{\hat{S}}_1\right)\\ Y_3-Y_2=U.Math.\left(S_3-S_2\right)+V.Math.\left(C_3-C_2\right)=2.Math.\sin \left(\frac{\Omega }{2}\right).Math.\left(U.Math.{\hat{C}}_2-V.Math.{\hat{S}}_2\right),\end{array}& \left(11\right)\end{array}$

wherein the following applies:

Ω=2π.Math.f.sub.wΔτ  (12)

and

[00006]$\begin{array}{cc}{\hat{S}}_j=\sin \left(\Omega .Math.\left(j+\frac{1}{2}\right)\right),j\in \left\{1,2\right\}& \left(13.Math.a\right)\\ {\hat{C}}_j=\cos \left(\Omega .Math.\left(j+\frac{1}{2}\right)\right),j\in \left\{1,2\right\}.& \left(13.Math.b\right)\end{array}$

[0062] Using the denotation

ΔY.sub.j=.sub.j+1Y.sub.j,jε{1,2}  (14)

the following is obtained as a solution for the system (11):

[00007]$\begin{array}{cc}U=\frac{\Delta .Math..Math.Y_1.Math.{\hat{S}}_2-\Delta .Math..Math.Y_2.Math.{\hat{S}}_1}{2.Math.\sin \left(\frac{\Omega }{2}\right).Math.\sin \left(\Omega \right)},& \left(15.Math.a\right)\\ V=\frac{\Delta .Math..Math.Y_1.Math.{\hat{C}}_2-\Delta .Math..Math.Y_2.Math.{\hat{C}}_1}{2.Math.\sin \left(\frac{\Omega }{2}\right).Math.\sin \left(\Omega \right)}.& \left(15.Math.b\right)\end{array}$

[0063] A further reduction of variables can be obtained by the following substitution:

Ŝ.sub.2=Ĉ.sub.1 sin Ω+Ŝ.sub.1 cos Ω,  (16a)

Ĉ.sub.2=Ĉ.sub.1 cos Ω−Ŝ.sub.1 sin Ω,  (16b)

and

[00008]$\begin{array}{cc}\sin .Math..Math.\Omega =2.Math.\sin \left(\frac{\Omega }{2}\right).Math.\cos \left(\frac{\Omega }{2}\right),& \left(17.Math.a\right)\\ \cos .Math..Math.\Omega =1-2.Math.{\sin }^2\left(\frac{\Omega }{2}\right).& \left(17.Math.b\right)\end{array}$

[0064] The constants

[00009]$\sin \left(\frac{\Omega }{2}\right).Math..Math.\mathrm{and}.Math..Math.\cos \left(\frac{\Omega }{2}\right)$

can thereby be treated as given parameters.

[0065] The value for β can thereby be determined from each of the following equations:

[00010]$\begin{array}{cc}\beta =Y_j-\left(U.Math.S_j+V.Math.C_j\right)=Y_j-[U.Math.\left({\hat{S}}_{j-1}.Math.\cos \left(\frac{\Omega }{2}\right)+{\hat{C}}_{j-1}.Math.\sin \left(\frac{\Omega }{2}\right)\right)+V.Math.\left({\hat{C}}_{j-1}.Math.\cos \left(\frac{\Omega }{2}\right)-{\hat{S}}_{j-1}.Math.\sin \left(\frac{\Omega }{2}\right)\right),.Math..Math.j\in \left\{2,3\right\}.& \left(18\right)\end{array}$

[0066] Receiving 201 a plurality of consecutive values of a receiving signal Y with a known sampling frequency f.sub.s as a reaction to a transmitting signal with a knowing transmitting frequency f.sub.w can be described using the equations (4) to (6).

[0067] Determining 202 two differential values ΔY1, ΔY2 each from two consecutive values out of three consecutive values Y1, Y2, Y3 of the receiving signal Y can be described by the system of equations (11).

[0068] Determining 203 a phase real part U and a phase imaginary part V of the receiving signal Y based on a linear relation between the phase real part U, the phase imaginary part V and the two differential values ΔY1, ΔY2 can be described by the equations (15a) and (15b).

[0069] FIG. 3 shows a schematic view of a processor 300 for determining a phase of a receiving signal according to a first embodiment.

[0070] The processor 300 comprises a first input register 301, a second input register 302, a third input register 303, a first internal register 341, a second internal register 342, a first output register 361, a second output register 362, a third output register 363, a first coefficient register 321, a second coefficient register 311, a third coefficient register 322, a fourth coefficient register 312, a first parameter memory 352 or rather a parameter register, a second parameter memory 351 or rather a parameter register, a third parameter memory 354 or rather a parameter register, a fourth parameter memory 353 or rather a parameter register, a computing unit 305 and an instruction unit 307. The processor further comprises an inlet for a clock signal CLK 370 and an inlet for a reset signal RST 371. The processor 300 is coupled to an input data bus 304 at its inlet side and to an output data bus 364 at its outlet side. Coupling of the inlets and outlets, however, can also be realized in a different manner. The three input registers 301, 302, 303 can be realized as a FIFO memory and can record a new value of the receiving signal Y in every clock and simultaneously delete the oldest recorded value.

[0071] The processor is suitable for determining a phase of a receiving signal Y being received as a reaction to a transmitting signal with a known transmitting frequency f.sub.w, said receiving signal Y having a known sampling frequency f.sub.s.

[0072] The first input register 301, the second input register 302 and the third input register 303 serve to store three consecutive values Y1, Y2, Y3 out of a plurality of consecutive values of the receiving signal Y one after the other, e.g. when the values Y1, Y2 and Y3 of a plurality of four consecutive values of the input signal Y1, Y2, Y3, Y4 are loaded in a first clock and the values Y2, Y3 and Y4 are loaded in a second clock, Y1 being substituted by Y2, Y2 being substituted by Y3 and Y3 being substituted by Y4 and so forth.

[0073] The first internal register 341 serves to store a first differential value ΔY1 as a difference of the content Y2 of the second input register 302 and of the content Y1 of the first input register 301. The second internal register 342 serves to store a second differential value ΔY2 as a difference of the content Y3 of the third input register 303 and the content Y2 of the second input register 302.

[0074] The first output register 361 serves to provide a phase real part U of the receiving signal Y. The second output register 362 serves to provide a phase imaginary part V of the receiving signal Y.

[0075] The computing unit 305 serves to determine the phase real part U and the phase imaginary part V of the receiving signal Y based on a linear relation between the phase real part U, the phase imaginary part V and the two differential values ΔY1, ΔY2, for example according to the method 200 described in FIG. 2 or according to the manner described below.

[0076] The computing unit 311, which is shown here only as a box using dashed lines, can comprise arithmetic-logic units for executing arithmetic operations. It can comprise adders, multipliers and other units for executing computing operations.

[0077] The third output register 363 serves to provide a bias β of the receiving signal Y.

[0078] The computing unit 305 is further configured for determining the bias β of the receiving signal Y based on a linear relation between the phase real part U, the phase imaginary part V, the bias β and the three consecutive values Y1, Y2, Y3 of the receiving signal Y.

[0079] The four coefficient registers 321, 311, 322, 312 serve to store Fourier Coefficients, said Fourier Coefficients determining the linear relation between the phase real part U, the phase imaginary part V and the two differential values ΔY1, ΔY2.

[0080] The first parameter memory 352 serves to store the cosine hC of the half of the known circular frequency Ω=2π(f.sub.w/f.sub.s). The second parameter memory 351 serves to store the sine hS of the half of the known circular frequency Ω. The third parameter memory 354 serves to store the cosine wC of the known circular frequency Ω. The fourth parameter memory 353 serves to store the sine wS of the known circular frequency Ω.

[0081] The computing unit 305 further serves to determine the phase real part U and the phase imaginary part V of the receiving signal Y based on the contents C1, S1, C2, S2 of the four coefficient registers 321, 311, 322, 312 and the contents hC, hS, wC, wS of the four parameter memories 352, 351, 354, 353.

[0082] The instruction unit 307 is configured for initializing the first coefficient register 321 with the content hC of the first parameter memory 352 and for initializing the second coefficient register 311 with the content hS of the second parameter memory 351 in response to a reset signal 371. The instruction unit 307 serves to renew the first coefficient register 321 with the content C2 of the third coefficient register 322 and to renew the second coefficient register 311 with the content S2 of the fourth coefficient register 312 in response to a clock signal 370.

[0083] The instruction unit 307 is further configured for loading the fourth coefficient register 312 with the value C.sub.1wS+S.sub.1wC in response to the clock signal 370 and for loading the third coefficient register 322 with the value C.sub.1wC−S.sub.1wS, wherein wS denotes the content of the fourth parameter memory 353, wC denotes the content of the third parameter memory 354, C.sub.1 denotes the content of the first coefficient register 321, S.sub.1 denotes the content of the second coefficient register 311 and Ω denotes the known circular frequency Ω=2π(f.sub.w/f.sub.s).

[0084] The computing unit 305 is configured for determining the phase real part U as

[00011]$\frac{\Delta .Math..Math.Y_1.Math.S_2-\Delta .Math..Math.Y_2.Math.S_1}{4.Math.\mathrm{hS}.Math.\mathrm{hS}.Math.\mathrm{hC}}$

and the phase imaginary part V as

[00012]$\frac{\Delta .Math..Math.Y_1.Math.C_2-\Delta .Math..Math.Y_2.Math.C_1}{4.Math.\mathrm{hS}.Math.\mathrm{hS}.Math.\mathrm{hC}},$

wherein hS denotes the content of the second parameter memory 351, hC denotes the content of the first parameter memory 352, C.sub.2 denotes the content of the third coefficient register 322, S.sub.2 denotes the content of the fourth coefficient register 312 and Ω denotes the known circular frequency Ω=2π((f.sub.w/f.sub.s).

[0085] The computing unit 305 is further configured for determining the bias β as Y.sub.2−(U.Math.(S.sub.1hC+C.sub.1hS)+V.Math.(C.sub.1hC−S.sub.1hS)), wherein U denotes the phase real part, V denotes the phase imaginary part and Y.sub.2 denotes the content of the second input register 302. However, the bias can also be determined according to a different formula according to the equation (18).

[0086] The processor 300 can be realized in hardware or in software. The processor 300 can form an operating unit on a chip or can be realized as a chip. The processor 300 can be a digital signal processor or a microcontroller. The processor 300 can be realized as an FPGA, as an integrated circuit, as an ASIC or as part of these components. The processor 300 can be realized in a receiver or as part of a receiver circuit, such as a receiver 103 as shown in FIG. 1.

[0087] The mode of operation of the processor 300 can be described as follows:

[0088] After starting the processor 300 or after receiving the reset signal RST 322, respectively, three consecutive values Y.sub.0, Y.sub.1, Y.sub.3 of the receiving signal Y are loaded into the three input registers 301, 302, 303 from the input data bus 304.

[0089] The third coefficient register 322 and the fourth coefficient register 312 are deleted. The first coefficient register 321 is initialized with the following value:

[00013]$\begin{array}{cc}\mathrm{hC}=\cos \left(\frac{\Omega }{2}\right)& \left(19.Math.a\right)\end{array}$

and the second coefficient register 311 is initialized with the following value:

[00014]$\begin{array}{cc}\mathrm{hS}=\sin \left(\frac{\Omega }{2}\right).& \left(19.Math.b\right)\end{array}$

[0090] In every clock of the clock signal 370, the third coefficient register 322 is loaded with the following value:

C.sub.1wC−S.sub.1wS  (20a)

and the fourth coefficient register 312 is loaded with the following value:

C.sub.1wS+S.sub.1wC,  (20b)

wherein the following applies:

wS=sin Q,  (21a)

wC=cos Q.  (21b)

[0091] The first output register 361 is loaded with the following value:

[00015]$\begin{array}{cc}U=\frac{\Delta .Math..Math.Y_1.Math.S_2-\Delta .Math..Math.Y_2.Math.S_1}{4.Math.\mathrm{hS}.Math.\mathrm{hS}.Math.\mathrm{hC}},& \left(22.Math.a\right)\end{array}$

and the second output register 362 is loaded with the following value:

[00016]$\begin{array}{cc}V=\frac{\Delta .Math..Math.Y_1.Math.C_2-\Delta .Math..Math.Y_2.Math.C_1}{4.Math.\mathrm{hS}.Math.\mathrm{hS}.Math.\mathrm{hC}},& \left(22.Math.b\right)\end{array}$

and the value

Y.sub.2−(U.Math.(S.sub.1hC+C.sub.1hS)+V(C.sub.1hC−S.sub.1hS))  (23)

is loaded into the third output register 363.

[0092] Then the first coefficient register 321 is overwritten with the content C.sub.2 of the third coefficient register 322 and the second coefficient register 311 is overwritten with the content S.sub.2 of the fourth coefficient register 312. The first input register 301 is overwritten with the content Y.sub.2 of the second input register 302, the second input register 302 is overwritten with the content Y.sub.3 of the third input register 303 and a new input value Y.sub.4 is loaded into the third input register 303 from the input data bus 304. The values U, V and β of the three output registers 361, 362, 363 are transferred to the output data bus 364.

[0093] FIG. 4 shows a schematic view of a processor 400 for determining a phase of a receiving to signal according to a second embodiment.

[0094] The processor 400 is constructed similar to the processor 300 described in FIG. 3. The processor 400 comprises, as does the processor 300, a first input register 301, a second input register 302, a third input register 303, a first internal register 341, a second internal register 342, a first output register 461, a second output register 462, a third output register 463, a first coefficient register 321, a second coefficient register 311, a third coefficient register 322, a fourth coefficient register 312, a first parameter memory 352, a second parameter memory 351, a third parameter memory 354, a fourth parameter memory 353, a computing unit 405 and an instruction unit 407. The processor 400 further comprises an inlet for a clock signal CLK 370 and an inlet for a reset signal RST 470. The processor is coupled to an input data bus 304 at its inlet side and to an output data bus 464 at its outlet side. Regarding the mode of operation of the units mentioned above, reference is made to the description of FIG. 3, although the computing unit has the reference number 405 due to the additional mode of operation and the instruction unit has the reference number 407 due to the additional mode of operation.

[0095] Unlike the processor 300, the processor 400 further comprises a fourth output register or first auxiliary register 481, respectively, a fifth output register or a second auxiliary register 482, respectively, a sixth output register or a third auxiliary register 483, respectively, three summation members 492, 493, 494, a counter 491 and an inlet for an interruption signal INT 472.

[0096] The counter 491 is incremented with each renewal of the three input registers 301, 302, 303 in dependence of the clock signal 370.

[0097] The computing unit 405 is further configured for determining the phase real part U as ΔY.sub.1S.sub.2−ΔY.sub.2S.sub.1 and the phase imaginary part V as ΔY.sub.1C.sub.2−ΔY.sub.2C.sub.1, for adding the phase real part U to the first auxiliary register 481 and for adding the phase imaginary part V to the second auxiliary register 482.

[0098] The instruction unit 407 is further configured for outputting the values AU, AV of the two auxiliary registers 481, 482 divided by the value 2.Math.wS.Math.hS=4hS.Math.hS.Math.hC and divided by a value cnt of the counter 491 in response to the interruption signal. Thereby, ΔY.sub.1 denotes the content of the first internal register 341, ΔY.sub.2 denotes the content of the second internal register 342, C.sub.2 denotes the content of the third coefficient register 322, S.sub.2 denotes the content of the fourth coefficient register 312, hS denotes the content of the second parameter memory 351 and hC denotes the content of the first parameter memory 352. Ω denotes the known circular frequency Ω=2π((f.sub.w/f.sub.s).

[0099] The processor 400 can be realized in hardware or in software. The processor 400 can form an operating unit on a chip or can be realized as a chip. The processor 400 can be a digital signal processor or a microcontroller. The processor 400 can be realized as an FPGA, as an integrated circuit, as an ASIC or as part of these components. The processor 400 can be realized in a receiver or as part of a receiver circuit, such as a receiver 103 as shown in FIG. 1.

[0100] The mode of operation of the processor 400 can be described as follows:

[0101] After starting the processor 400 or after receiving the reset signal RST 322, respectively, three consecutive values Y.sub.0, Y.sub.1, Y.sub.3 of the receiving value Y are loaded into the three input registers 301, 302, 303 from the input data bus 304.

[0102] The three coefficient register 322 and the forth coefficient register 312 are deleted. The first coefficient register 321 is initialized with the following value:

[00017]$\begin{array}{cc}\mathrm{hC}=\cos \left(\frac{\Omega }{2}\right)& \left(24.Math.a\right)\end{array}$

[0103] and the second coefficient register 311 is initialized with the following value:

[00018]$\begin{array}{cc}\mathrm{hS}=\sin \left(\frac{\Omega }{2}\right).& \left(24.Math.b\right)\end{array}$

[0104] In every clock of the clock signal 370, the third coefficient register 322 is loaded with the following value:

C.sub.1wC−S.sub.1wS  (25a)

and the fourth coefficient register 312 is loaded with the following value:

C.sub.1wS+S.sub.1wC,  (25b)

wherein the following applies:

wS=sin Q,  (26a)

wC=cos Q.  (26b)

[0105] The first output register 461 is loaded with the following value:

U=ΔY.sub.1.Math.S.sub.2−ΔY.sub.2.Math.S.sub.1,  (27a)

which is also added to the forth output register 481, for which the first summation member 492 is used.

[0106] The second output register 362 is loaded with the following value:

V=ΔY.sub.1.Math.C.sub.2−ΔY.sub.2.Math.C.sub.1,  (27b)

which is also added to the fifth output register 482, for which the second summation member 493 is used.

[0107] The value

[00019]$\begin{array}{cc}{Y}_2-\frac{\left(U.Math.\left(S_1.Math.\mathrm{wC}+C_1.Math.\mathrm{wS}\right)+V.Math.\left(C_1.Math.\mathrm{wC}-S_1.Math.\mathrm{wS}\right)\right)}{4.Math.\mathrm{hS}.Math.\mathrm{hS}.Math.\mathrm{hC}}& \left(28\right)\end{array}$

is loaded into the output register 463.

[0108] Then the first coefficient register 321 is overwritten with the content C.sub.2 of the third coefficient register 322 and the second coefficient register 311 is overwritten with the content S.sub.2 of the fourth coefficient register 312. The counter 491 is incremented. The first input register 301 is overwritten with the content Y.sub.2 of the second input register 302, the second input register 302 is overwritten with the content Y.sub.3 of the third input register 303 and a new input value Y.sub.4 is loaded into the third input register 303 from the input data bus 304.

[0109] As soon as there is an interruption, meaning as soon as the interruption signal 472 signals an interruption, the content AU of the fourth output register 481 and the content to AV of the fifth output register 482 are divided by the value 2wShS(=4hShShC) and their values as well as the value β of the third output register 463, each divided by the value cnt of the counter 491, are transferred to the output data bus 484.

[0110] After this, the reset signal 371 is transmitted.

[0111] The processor 300 according to the description of FIG. 3 as well as the processor 400 according to the description of FIG. 4 are suitable for implementing the method 200 described in FIG. 2.

[0112] An aspect of the invention also comprises a computer program product, which can be uploaded directly into the internal memory of a digital computer and comprises software code sections, by means of which the method 200 described in FIG. 2 can be carried out when the product is running on a computer. The computer program product can be stored on a medium suitable for computers and can comprise the following: machine-readable programming means, which cause a computer to receive 201 a plurality of consecutive values of a receiving signal Y with a known sampling frequency f.sub.s as a reaction to a transmitting signal with a known transmitting frequency f.sub.w; to determine 202 two differential values ΔY1, ΔY2 each from two consecutive values out of three consecutive values Y1, Y2, Y3 of the receiving signal Y; and to determine 203 a phase real part U and a phase imaginary part V of the receiving signal Y based on a linear relation between the phase real part U, the phase real part V and the two differential values ΔY1, ΔY2.

[0113] The computer can be a PC, for example a PC of a computer network. The computer can be realized as a chip, an ASIC, a microprocessor, a signal processor or as a processor in general and can be implemented as a processor as described in FIGS. 3 to 5, for example.

[0114] It is understood that the features of the different exemplary embodiments described herein can be combined with one another, except when explicitly indicated otherwise. As shown in the description and the drawings, individual elements, which are shown in connection with one another, do not have to be directly connected to one another; intermediate elements can be provided between the connected elements. Furthermore, it is understood that embodiments of the invention can be implemented in individual circuits, partially integrated circuits or entirely integrated circuits or programming means. The terms “such as” and “for example” solely refer to an exemplary embodiment and not to the best or the ideal embodiment. Certain embodiments were depicted and described herein, although it is obvious to the skilled person that a plurality of alternative and/or similar implementations can be realized in place of the embodiments shown and described, without deviating from the concept of the present invention.

LIST OF REFERENCES

[0115] 100: system 100 for measuring phase relations of acoustic waves in a vessel [0116] 101: transmitter [0117] 102: vessel [0118] 103: receiver [0119] 104: ultrasonic wave [0120] 105: inlet [0121] 107: outlet [0122] 200: phase detection method 200 [0123] 201: 1st method step: receiving [0124] 202: 2nd method step: determining [0125] 203: 3rd method step: determining [0126] 300: processor, suitable for determining a phase of a receiving signal [0127] 301: first input register [0128] 302: second input register [0129] 303: third input register [0130] 304: input data bus [0131] 305: computing unit [0132] 307: instruction unit [0133] 311: second coefficient register [0134] 312: fourth coefficient register [0135] 321: first coefficient register [0136] 322: third coefficient register [0137] 341: first internal register [0138] 342: second internal register [0139] 351: second parameter memory [0140] 352: first parameter memory [0141] 353: fourth parameter memory [0142] 354: third parameter memory [0143] 361: first output register [0144] 362: second output register [0145] 363: third output register [0146] 364: output data bus [0147] 370: clock signal [0148] 371: reset signal [0149] 400: processor, suitable for determining a phase of a receiving signal [0150] 405: computing unit [0151] 407: instruction unit [0152] 484: output data bus [0153] 472: interruption signal [0154] 481: fourth output register or first auxiliary register [0155] 482: fifth output register or second auxiliary register [0156] 483: sixth output register or third auxiliary register [0157] 491: counter [0158] 492: first summation member [0159] 493: second summation member [0160] 494: third summation member