FABRICATION METHOD OF PACKAGE STRUCTURE

Abstract

A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.

Claims

1-5. (canceled)

6. A method for fabricating a package structure, comprising the steps of: providing a carrier having a plurality of bonding pads and a dielectric layer having opposite first and second surfaces; laminating the dielectric layer on the carrier via the first surface thereof, wherein the bonding pads are covered by the dielectric layer; forming a plurality of conductive posts in the dielectric layer; and forming at least a cavity in the second surface of the dielectric layer so as to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity.

7. The method of claim 6, wherein the carrier is a packaging substrate, a semiconductor chip, a wafer, an interposer, or a packaged or unpackaged semiconductor element.

8. The method of claim 6, wherein the second surface of the dielectric layer has a conductive layer used for forming the conductive posts.

9. The method of claim 6, wherein forming the conductive posts comprises: forming a plurality of through holes penetrating the dielectric layer; and filling a conductive material in the through holes to form the conductive posts.

10. The method of claim 6, wherein the second surface of the dielectric layer has a circuit layer electrically connected to the conductive posts.

11. The method of claim 6, wherein the dielectric layer is made of a photo imageable dielectric material.

12. The method of claim 11, wherein the cavity is formed by exposure and development.

13. The method of claim 6, further comprising disposing an electronic element in the cavity, wherein the electronic element is electrically connected to the bonding pads.

14. The method of claim 6, further comprising stacking a stack member on the second surface of the dielectric layer, wherein the stack member is electrically connected to the conductive posts.

15. The method of claim 14, wherein the stack member is a packaging substrate, a semiconductor chip, an interposer or a package.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0020] FIGS. 1A and 1B are schematic cross-sectional views showing a method for fabricating a PoP structure according to the prior art; and

[0021] FIGS. 2A to 2G are schematic cross-sectional views showing a method for fabricating a PoP structure according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0022] The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.

[0023] It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as “first”, “second”, “on”, “a” etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention.

[0024] FIGS. 2A to 2G are schematic cross-sectional views showing a method for fabricating a package structure according to the present invention.

[0025] Referring to FIG. 2A, a carrier 21 having a plurality of first bonding pads 210 and a plurality of second bonding pads 211 is provided.

[0026] In the present embodiment, the carrier 21 is a packaging substrate, a semiconductor chip, a wafer, an interposer, or a packaged or unpackaged semiconductor element. For example, referring to FIG. 2A, the carrier 21 is a coreless packaging substrate, which has a plurality of dielectric layers 213 and a plurality of circuit layers 211′ alternately stacked on one another and a plurality of conductive vias 212 penetrating the dielectric layers 213 and electrically connected to the circuit layers 211′. Further, a metal layer 214 made of such as copper is formed on a lower side of the carrier 21.

[0027] A carrying area A is defined on the carrier 21. The first bonding pads 210 are positioned inside the carrying area A and the second bonding pads 211 are positioned outside the carrying area A.

[0028] Referring to FIG. 2B, a dielectric layer 22 having a conductive layer 23 thereon is laminated on the carrier 21 to cover the first and second bonding pads 210, 211. Then, by performing a laser drilling process, a plurality of through holes 260 are formed to penetrate the dielectric layer 22 and the conductive layer 23 corresponding in position to the second bonding pads 211.

[0029] In the present embodiment, the dielectric layer 22 has opposite first and second surfaces 22a, 22b. The conductive layer 23 is formed on the second surface 22b of the dielectric layer 22, and the dielectric layer 22 is laminated on the carrier 21 via the first surface 22a thereof.

[0030] Further, the dielectric layer 22 is made of a photo imageable dielectric (PID) material and the conductive layer 23 is a copper layer.

[0031] By laminating the dielectric layer 22 on the carrier 21, the present invention simplifies the fabrication process.

[0032] Referring to FIG. 2C, by using the conductive layer 23 as a conductive path, a circuit layer 25 is formed on the second surface 22b of the dielectric layer 22 and a conductive material is filled in the through holes 260 to form a plurality of conductive posts 26 electrically connecting the circuit layer 25 and the second bonding pads 211.

[0033] In the present embodiment, the circuit layer 25 is not formed on the second surface 22b of the dielectric layer 22 corresponding in position to the carrying area A.

[0034] Further, the metal layer 214 on the lower side of the carrier 21 is patterned to form a circuit layer 25′.

[0035] Referring to FIG. 2D, by performing an exposure and development process, a cavity 220 is formed in the second surface 22b of the dielectric layer 22 to expose the first bonding pads 210. The conductive posts 26 are positioned around a periphery of the cavity 220. As such, a package structure 2 is formed.

[0036] In the present embodiment, an upper side of the carrier 21 in the carrying area A is also exposed from the cavity 220.

[0037] Referring to FIG. 2E, an insulating layer 27 is formed on the second surface 22b of the dielectric layer 22 and the lower side of the carrier 21, and portions of the circuit layers 25, 25′ are exposed from the insulating layer 27 for mounting external elements in subsequent processes.

[0038] Referring to FIG. 2F, at least an electronic element 28 is disposed in the cavity 220 and electrically connected to the first bonding pads 210 through a plurality of conductive bumps 281.

[0039] Referring to FIG. 2G, a stack member 29 is stacked on the exposed portions of the circuit layer 25 and covers the cavity 220 and the electronic element 28. As such, a package structure 3 is formed.

[0040] In the present embodiment, the stack member 29 is a packaging substrate, a semiconductor chip, a wafer, a silicon interposer or a package. The stack member 29 is electrically connected to the circuit layer 25 and the conductive posts 26 through a plurality of conductive elements 291 made of such as a solder material or metal posts.

[0041] Further, an encapsulant 30 is formed between the stack member 29 and the carrier 21 for encapsulating the conductive bumps 281.

[0042] The present invention further provides a package structure 2, which has: a carrier 21 having a plurality of bonding pads 210; a dielectric layer 22 having opposite first and second surfaces 22a, 22b and disposed on the carrier 21 via the first surface 22a thereof, wherein at least a cavity 220 is formed in the second surface 22b of the dielectric layer 22 to expose the bonding pads 210; and a plurality of conductive posts 26 formed in the dielectric layer 22 and positioned around a periphery of the cavity 220.

[0043] The carrier 21 can be a packaging substrate, and the dielectric layer 22 can be made of a photo imageable dielectric material. A circuit layer 25 can be formed on the second surface 22b of the dielectric layer 22 and electrically connected to the conductive posts 26.

[0044] In an embodiment, the package structure 2 further has an electronic element 28 disposed in the cavity 220 and electrically connected the bonding pads 210.

[0045] According to the present invention, a dielectric layer 22 is formed on a carrier 21, a plurality of conductive posts 26 are embedded in the dielectric layer 22 and a stack member 29 is stacked on the dielectric layer 22 and electrically connected to the conductive posts 26. As such, the present invention achieves a preferred stand-off effect between the conductive posts 26 so as to prevent bridging from occurring between the conductive posts 26.

[0046] Further, the size of the conductive posts 26 can be controlled through the through holes 260 so as to cause the conductive posts 26 to have a uniform height. Therefore, the present invention overcomes the conventional drawback of joint deviation and ensures a reliable bonding between the conductive posts 26 and conductive elements 291, thus improving the product yield.

[0047] Furthermore, since the dielectric layer 22 has a photo imageable property, the cavity 220 can be formed in the dielectric layer 22 by exposure and development, thereby simplifying the fabrication process.

[0048] The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.