DISPLAY WITH CELL VOLTAGE COMPENSATION

Abstract

An active matrix display wherein each cell comprises: two thin-film transistors (TFTs) connected in series, the first TFT having its drain connected to a high supply line and the second TFT having its source connected to a low supply line. Gates of the first and second TFTs are selectively connected to respective first and second data driver signals under the control of a scan line signal. A storage capacitance is connected to a node joining the first and second TFT. A driving TFT has a gate connected to the joining node and is connected to drive a light emitting device with a bias current. In one embodiment, the first and second TFTs are sized relative to one another and the first and second data driver signal voltages are related proportionally, so that the data driver signals and the bias current are related to one another by a function substantially independent of a threshold voltage of the driving TFT.

Claims

1. A display, comprising: a matrix including a plurality of cells; a data driver connected to the matrix to provide data driver signals to the plurality of cells, wherein a cell of the plurality of cells includes: a light emitting device; a driving thin-film transistor (TFT) connected to the light emitting device to drive the light emitting device with a bias current, the driving TFT having a gate and a threshold voltage; and a circuit connected with the data driver and the gate of the driving TFT, the circuit configured to: generate a gate voltage based on a voltage of the data driver signals from the data driver and the threshold voltage of the driving TFT; and provide the gate voltage to the gate of the driving TFT such that the bias current that drives the light emitting device is independent of the threshold voltage of the driving TFT.

2. The display of claim 1, wherein: the display further includes a scan driver coupled to the matrix to provide scan line signals to the plurality of cells; and the circuit further includes a first TFT connected in series with a second TFT, wherein: the first TFT has a drain connected to a high supply line and the second TFT has a source connected to a low supply line; a gate of the first TFT is selectively connected to a first data driver signal from the data driver under control of a scan line signal from the scan driver; a gate of the second TFT is selectively connected to a second data driver signal from the data driver under control of the scan line signal; and the gate of the driving TFT is connected to a node joining the first and second TFTs.

3. The display of claim 2, wherein the circuit further includes: a third TFT connecting the gate of the first TFT to the first data driver signal, a gate of the third TFT connected the scan driver to receive the scan signal line; a fourth TFT connecting the gate of the second TFT to the second data driver signal, a gate of the fourth TFT connected to the scan driver to receive the scan line.

4. The display of claim 2, wherein: the first data driver signal has a first voltage; the second data driver signal has a second voltage different from the first voltage; the first TFT has a first size; and the second TFT has a second size different from the first size,

5. The display of claim 4, wherein data driver sets the first and second voltages such that the first TFT and the second TFT each have a threshold voltage that is substantially the same as the threshold voltage of the driver TFT.

6. The display of claim 2, wherein the cell further includes a storage capacitance coupled to the node joining the gate of the driving TFT and the first and second TFTs.

7. The display of claim 2, wherein the data driver provides a pair of variable first and second data driver signals to each of the plurality of cells.

8. The display of claim 1, wherein the circuit generates the gate voltage in a first portion of a scan pulse period and provides the gate voltage to the gate of the driving TFT in a second portion of the scan pulse period.

9. A display, comprising: a matrix including a plurality of cells; a data driver connected to the matrix to provide data driver signals to the plurality of cells, a cell of the plurality of cells including: a first light emitting device; a first driving thin-film transistor (TFT) connected to the first light emitting device to drive the first light emitting device, the first driving TFT having a first gate; and a second light emitting device; a second driving TFT connected to the second light emitting device to drive the second light emitting device, the second driving TFT having a second gate, the second driving TFT being oppositely doped from the first driving TFT; and a circuit connected with the data driver and a node joining the first gate of the first driving TFT and the second gate of the second driving TFT, the circuit configured to: generate a gate voltage based on a first voltage of a first data driver signal from the data driver and a second voltage of a second data driver signal from the data driver; and provide the gate voltage to the first gate of the first driving TFT and the second gate of the second driving TFT, the gate voltage causing the first driving TFT to drive the first light emitting device or causing the second TFT to drive the second light emitting device.

10. The display of claim of 9, wherein: the display further includes a scan driver coupled to the matrix to provide scan line signals to the plurality of cells; and the circuit further includes a first TFT connected in series with a second TFT, wherein: the first TFT has a drain connected to a high supply line and the second TFT has a source connected to a low supply line; a gate of the first TFT is selectively connected to the first data driver signal from the data driver under control of a scan line signal from the scan driver; a gate of the second TFT is selectively connected to the second data driver signal from the data driver under control of the scan line signal; and the first and second TFTs are connected to the node joining the first gate of the first driving TFT and the second gate of the second driving TFT.

11. The display of claim 10, wherein the circuit further includes: a third TFT connecting the first gate of the first TFT to the first data driver signal, a third gate of the third TFT connected the scan driver to receive the scan signal line; a fourth TFT connecting the second gate of the second TFT to the second data driver signal, a fourth gate of the fourth TFT connected to the scan driver to receive the scan line.

12. The display of claim 11, wherein the circuit further includes: a first storage capacitance connected to the first gate of the first TFT; and a second storage capacitance connected to the second gate of the second TFT.

13. The display of claim 10, wherein the gate voltage causes the first TFT to drive the first light emitting device independent of a first threshold voltage of the first driving TFT or the second TFT to drive the second light emitting device independent of a second threshold voltage of the second driving TFT.

14. The display of claim 13, wherein the first TFT and the second TFT have the same size.

15. The display of claim 14, wherein the data driver sets the first and second voltages such that the first TFT and the second TFT each have a threshold voltage that is substantially the same as the first threshold voltage of the first driver TFT and the second threshold voltage of the second driver TFT.

16. The display of claim 9, wherein the data driver controls the voltage of the first data driver signals relative to the voltage of the second data driver signals to selectively drive the first light emitting device or the second light emitting device of the cell.

17. The display of claim 9, wherein the circuit generates the gate voltage in a first portion of a scan pulse period and provides the gate voltage to the first gate of the first driving TFT and the second gate of the second driving TFT in a second portion of the scan pulse period.

18. A method of populating a display, comprising: placing first light emitting devices at first light emitting device locations within a matrix of the display, the matrix including a plurality of cells each being arranged to receive at least two light emitting devices; testing the display to determine one or more cells containing a defective first light emitting device; and placing second discrete light emitting devices at second light emitting device locations within the one or more cells determined to contain a defective first light emitting device, each of the one or more cells including circuitry that selectively activates a first light emitting device at a first light emitting device location or a second light emitting device at a second light emitting device location.

19. The method of claim 18, further comprising: subsequent to placing the second discrete light emitting devices at the second light emitting device locations of the one or more cells, testing the display to determine one or more second cells containing two defective light emitting devices; and storing locations of the one or more cells and the one or more second cells in a memory.

20. The method of claim 18, further comprising: programming the circuitry of one or more second cells containing non-defective first light emitting devices at the first light emitting device locations to activate the non-defective first light emitting devices; and programming the circuitry of the one or more cells to activate the second light emitting devices at the second light emitting device locations.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:

[0031] FIG. 1 shows a conventional type active matrix display;

[0032] FIG. 2 shows a conventional 2-TFT-1-capacitance pixel design;

[0033] FIG. 3 shows a pixel design with threshold voltage compensation;

[0034] FIG. 4 is a timing diagram showing scan pulses with a threshold voltage compensation phase;

[0035] FIG. 5 shows a single LED cell design according to an embodiment of the present invention;

[0036] FIG. 6 shows a dual LED cell design according to an embodiment of the present invention; and

[0037] FIG. 7 shows a placement method for a display incorporating a cell such as shown in FIG. 6.

DESCRIPTION OF THE EMBODIMENTS

[0038] In embodiments of the present invention, compensation for threshold voltage variation is provided locally on a cell by cell basis. If the threshold voltage of the driving TFT, T2, is extracted and added to Vdata, then the effective gate voltage of the driving TFT would be:

V.sub.gs,eff=V.sub.data+V.sub.th   (3)

[0039] In this case, the produced drain current would be:

[00003]$\begin{array}{cc}{I}_{\mathrm{drain}}=I_{\mathrm{bias}}=\frac{W}{L}.Math.\mu .Math..Math.{C_{\mathrm{ox}}\left(V_{\mathrm{gs},\mathrm{eff},T.Math..Math.2}-V_{\mathrm{th}}\right)}^2.fwdarw..Math.I_{\mathrm{bias}}=\frac{W}{L}.Math.\mu .Math..Math.{C_{\mathrm{ox}}\left(V_{\mathrm{data}}\right)}^2& \left(4\right)\end{array}$

[0040] As it can be seen from Equation (4), the produced drain current that would bias the light emitting device would then be independent of the driving TFT threshold voltage and the light brightness would exhibit immunity to the threshold voltage variations.

[0041] Referring now to FIG. 3 which shows a notional circuit implementation of the above method. According to FIG. 3, an additional Vth compensation circuit is added to the 2T1C cell. During the frame programming phase and before the data loading period, the circuit samples the threshold voltage of the driving TFT, T2 and then it sums the extracted threshold voltage and the Vdata in order to generate the required effective gate-to-source voltage for compensation. Therefore, a specific time duration of the scan pulse per frame refresh period is dedicated to threshold voltage compensation. An example of such scan pulses is shown in FIG. 4.

[0042] The total scan pulse duration (τ.sub.scan) depends on the frame rate (FR) of the display as well as from the total number of rows (Nrow), and can follow the equation:

[00004]${\tau }_{\mathrm{scan}}=\frac{1}{\mathrm{FR}*N_{\mathrm{row}}}$

[0043] FIG. 4 implies that the total scan time is divided into the threshold voltage compensation phase and the Vdata loading phase. (In the case of a PWM matrix, the period after threshold voltage compensation would comprise both a Vdata loading phase and a PWM phase for each sub-frame.) As the performance, i.e. frame refresh rate, and the size or resolution of displays keeps increasing, the available scan time is reduced significantly. This means that the time for threshold voltage compensation also shrinks, making threshold voltage compensation impractical for high performance displays.

[0044] FIG. 5 illustrates a cell design according to an embodiment of the present invention.

[0045] The cell comprises 5 TFTs T1 . . . T5 and 1 storage capacitance Cst. The objective is to produce a voltage at the storage capacitance (node A) equal to the effective voltage shown in equation (3). In an embodiment, T4 is four times larger than T3 (k4 =4k3) and the bias voltage (Vbias) is 3 times larger than data voltage (Vbias =3*Vdata) and is provided by the data driver at the same time as Vdata. Thus for a matrix as shown in FIG. 1, each data driver signal D1 . . . . Dn would comprise a data line and bias line, one being a fraction of the other. T3 and T4 share the same current and both of them operate within their saturation region. Therefore:

I.sub.drain,T3=I.sub.drain,T4.fwdarw.k.sub.3(V.sub.gs,T3−V.sub.th3).sup.2=k.sub.4(V.sub.gs,T4−V.sub.th4).sup.2

k.sub.3(3*V.sub.data−V.sub.A−V.sub.th3).sup.2=4k.sub.3(V.sub.data−V.sub.th4).sup.2

3*V.sub.data−V.sub.A−V.sub.th3=2*V.sub.data−V.sub.th4

[0046] If it is assumed that the two TFTs (T3 and T4) share the same threshold voltage (Vth4=Vth3=Vth) which is true, at least for LTPS, the voltage at node A, will be:

V.sub.A=V.sub.gs,T5=V.sub.data+V.sub.th

[0047] Therefore, the bias current produced from T5, is threshold voltage independent and well controlled, since it will be calculated by the equation:

[00005]$I_{\mathrm{ILED}}=\frac{W_5}{L_5}.Math.\mu .Math..Math.{C_{\mathrm{ox}}\left(V_{\mathrm{data}}\right)}^2$

[0048] As it can be seen from FIG. 3, the frame programming and the threshold voltage compensation can now be implemented during the same phase, resulting in additional available time for the programming phase or for improved performance. Furthermore, in the cell design of FIG. 5, the storage capacitor isn't charged directly from data line, but from T3. This means that power as well as propagation delay can be reduced. The advantages of the described cell design thus make it suitable for high performance displays, with high frame refresh rate and a short scan period.

[0049] The only requirement to ensure the proper operation of the cell is that all TFTs operate within their saturation region. The most critical TFT is T3 because its gate node is biased with the highest voltage. The condition which will ensure that T3 operates in its saturation region is:

V.sub.DS,T3>V.sub.gs,T3−V.sub.th

V.sub.dd>3*V.sub.data−.sub.th

[0050] Therefore, by choosing the supply voltage (Vdd) properly, the operation of the cell is ensured.

[0051] It will be appreciated that while the above embodiment has been described with k.sub.4×X*k.sub.3 and Vbias=Y*Vdata; where X=4 and Y=3, any combination of X and Y values which meant that the current through the light emitting device was substantially independent of the driving transistor threshold voltage could be employed.

[0052] It will also be appreciated that while a ground reference is shown in FIG. 5, any low supply line voltage could be employed with the above equations changing accordingly.

[0053] In operation, during the frame programming phase, the Scan signal for a row containing the cell goes high “1” causing T1 and T2 to turn ON. Vbias and Vdata (provided from the data driver) are biased to the circuit simultaneously, so based on their value, node A voltage and so the ILED current are adjusted. The storage capacitance Cst is added in order to keep the voltage at node A constant during emission phase resulting in stable iLED current. The cell design allows both analog Vdata and PWM driving or mixed mode schemes to be employed. In the case of a PWM driving scheme, rather than providing a constant Vdd to the ilED, a pulsed PWM signal can be applied. Alternatively, as described in UK Patent Application No. 1604699.7 (Ref: I35-1702-01GB), the iLED can be connected to the drain of T5 and the PWM signal can be applied directly to the cathode of the iLED. The mixed mode scheme described in UK Patent Application No. 1604699.7 (Ref: I35-1702-01GB) can also be employed.

[0054] FIG. 6 illustrates a cell design according to a second embodiment of the present invention including two iLEDs and the front-end part (T1, T2, T3 and T4) of the cell of FIG. 5. The cell design can be used to provide redundancy and so to increase the yield of an iLED based display; or for other applications where it could be useful to swap between driving ILED1 or ILED2 where both are placed in a cell.

[0055] The cell of FIG. 6 comprises 6 TFTs T1 . . . T6 and two capacitances. In this case, switching transistors T3 and T4 extend in series between a high supply line Vdd and a low supply line Vss while the capacitors are connected between respective gates of transistors T3 and T4 and ground. ILED1 has its anode connected to the ground line and its cathode connected to the drain node of T6. ILED2 has its cathode connected to ground and its anode connected to the drain node of T5. T5 is a p-type TFT while T6 is an n-type TFT. Again, the operation of the circuit is based on controlling the voltage at node A with T1, T2, T3, T4, Vbias and Vdata so that: if VA>0, T6 operates in order for ILED1 to emit light; or if VA<0, T5 operates in order for ILED2 to emit light. Unlike in FIGS. 5, T3 and T4 have the same gate dimensions (k.sub.3=k.sub.4) and again, as they are connected in series, the same current flows through them. If both operate in their saturation region, the current will be equal to:

I.sub.drain,T3=I.sub.drain,T4.fwdarw.k.sub.3(V.sub.gs,T3−V.sub.th3).sup.2=k.sub.4(V.sub.gs,T4−V.sub.th4).sup.2

k.sub.3(V.sub.data−V.sub.A−V.sub.th3).sup.2=k.sub.3(V.sub.bias−V.sub.th4).sup.2

V.sub.data−V.sub.A−V.sub.th3=V.sub.bias−V.sub.th4

[0056] If it is assumed that the two TFTs (T3 and T4) share the same threshold voltage (V.sub.th4=V.sub.th3=V.sub.th) which stands true for LTPS TFT process, the voltage at node A, will be:

V.sub.A=V.sub.data−V.sub.bias

[0057] Therefore, by setting Vbias at a pre-determined value, the sign of the node A voltage is determined by Vdata independent of the threshold voltage of the driving transistors. If Vdata>Vbias, then VA>0 and ILED1 emits light or if Vdata<Vbias, then VA<0 and ILED2 will emit light. There is also the special case in which Vdata=Vbias resulting in the voltage at node A being equal to zero. In this case none of T5 or T6 will be turned ON so neither ILED1 nor ILED2 will emit light. This can be used for “electrical repair” where no light is emitted from the cell and it is turned into a “black” cell.

[0058] Note that in the cell designs of FIGS. 5 and 6, the largest transistor within the cell is T5 and T6, the driving transistor(s). Once such a transistor is being fabricated then there is very little additional cost in producing the switching transistors T1, T2 and indeed the additional switching transistors T3, T4 required for the cell designs of FIGS. 5 and 6.

[0059] In the matrix of FIG. 1, the data driver is shown as a singular unit, however, it will be appreciated that the functionality of the data driver (and indeed the other peripheral components) can be divided among more than one unit, for example, with one unit providing Vdata and another providing Vbias.

[0060] In one application, a matrix based on the cell design of FIG. 6 can be employed to improve yield. Referring to FIG. 7, initially, the whole panel is assembled with light emitting devices, for example, iLEDs, placed in sockets or locations corresponding to ILED1. As each iLED is discrete, this is typically performed using a first pick-and-place procedure. Once placement of these devices is completed, the panel is tested visually. With visual detection, all defective ILEDs are recognized and their location on the panel recorded. In this way, a panel map indicating defective ILEDs is generated and stored in a memory available to the matrix controller (not shown). This map will be used for the programming of the display when in operation.

[0061] A second pick-and-place places ILEDS in sockets or locations corresponding to ILED2 in cells where ILED1 has been identified as defective. (Note that the defective ILED does not need to be removed.) Also note that ILEDs chosen for placement in the second pick-and-place phase can be known good devices. For light emitting devices where say 95% of devices work, this means that only 5% need to be replaced and so this reduces the need to test devices before they are placed and yet still obtain higher manufacturing yield than the natural reliability of the devices would provide.

[0062] When the second pick-and-place procedure is completed, the panel is visually tested again. If any of the ILED2 locations still don't work, then these cells (along with other cells forming a pixel) can be converted into black pixels meaning that they will not emit light. Again, a panel map indicating cells containing two defective ILEDs can be generated and stored in a memory available to the matrix controller (not shown) and this map will be used for the programming of the display when in operation.

[0063] The selection of the appropriate Vdata value can be made using the above mentioned panel map(s), produced during the fabrication process and after the visual inspection. Each cell can be programmed individually so that, if the cell has a second iLED placed because the first was defective, in the programming phase, the Vdata value will be set less than Vbias (or at least the opposite to cells where the first iLED works). Similarly for “black” pixels, Vdata=Vbias value can be set during the programming phase for pixels indicated by the panel map to contain two defective ILEDs.

[0064] In another application, two different types of light emitting devices are placed in sockets or locations corresponding to iLED1 and iLED2 to enable the display to selectively operate in one of two modes. For example, iLED1 devices might have more focussed light emission characteristics whereas iLED2 devices might have more diffuse light emission. The panel controller can therefore swap between driving either the first set of devices or the second set of devices to swap between a display providing a narrow (private) viewing angle and a wider more accessible viewing angle.

[0065] In a still further application, again two different sets of light emitting devices can be placed in sockets corresponding to iLED1 and ilED2 and these can be selectively driven to provide a display which can selectively operate in one of a 2D display mode and a 3D display mode.

[0066] In each of these multi-mode embodiments, Vbias (or Vdata) can be a global signal and swapping this between one of two levels can change the panel from driving iLED1 to iLED2 within each cell.

[0067] In still further variants of the above described embodiments, the above principals can be extended to cell designs comprising more than two light emitting devices and appropriate switching circuitry to provide both threshold compensation and redundancy; redundancy and multi-mode operation; threshold compensation and multi-mode operation; or indeed threshold compensation, redundancy and multi-mode operation.