GaN-based VCSEL chip based on porous DBR and manufacturing method of the same

Abstract

A GaN-based VCSEL chip based on porous DBR and a manufacturing method of the same, wherein the chip includes: a substrate; a buffer layer formed on the substrate; a bottom porous DBR layer formed on the buffer layer; an n-type doped GaN layer formed on the bottom porous DBR layer, which is etched downward on its periphery to form a mesa; an active layer formed on the n-type doped GaN layer; an electron blocking layer formed on the active layer; a p-type doped GaN layer formed on the electron blocking layer; a current limiting layer formed on the p-type doped GaN layer with a current window formed at a center thereof, wherein the current limiting layer covers sidewalls of the active layer, the electron blocking layer and the convex portion of the n-type doped GaN layer; a transparent electrode formed on the p-type doped GaN layer; an n-electrode formed on the mesa of the n-type doped GaN layer; a p-electrode formed on the transparent electrode with a recess formed therein; and a dielectric DBR layer formed on the transparent electrode in the recess of the p-electrode.

Claims

1. A method for manufacturing a GaN-based VCSEL chip based on porous DBR, comprising: step 1: growing a buffer layer, alternately stacked lightly doped layers and heavily doped layers, an n-type doped GaN layer, an active layer, an electron blocking layer, and a p-type doped GaN layer on a substrate sequentially, wherein the substrate is made of sapphire, Si or SiC; step 2: performing lateral etching on the alternately stacked lightly doped layers and heavily doped layers by using an electrochemical etching method, so as to transform them to a bottom porous DBR layer in which porous layers and non-porous layers are alternately stacked; step 3: etching down on a periphery of the p-type doped GaN layer by a depth so that a portion of the n-type doped GaN layer is etched, so as to form a mesa on the periphery of the n-type doped GaN layer; step 4: forming a current limiting layer on sidewalls of the p-type doped GaN layer, the mesa, the active layer, and the electron blocking layer; step 5: forming a current window on the current limiting layer, and removing a portion of the current limiting layer on the mesa, using a photolithography and etching technique; step 6: forming a transparent electrode at the current window on the p-type doped GaN layer; step 7: forming an n-electrode and a p-electrode on the mesa on which a portion of the current limiting layer is removed and a periphery of the transparent electrode respectively, wherein a recess is formed in a middle of the p-electrode; and step 8: forming a dielectric DBR layer on an upper surface of the transparent electrode in the recess of the p-electrode, so as to complete the manufacturing.

2. The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 1, wherein the dielectric DBR layer and the bottom porous DBR layer constitute upper and lower mirrors of the VCSEL chip respectively, and the bottom porous DBR layer has a reflectivity of above 95% at a peak wavelength of the active layer, which is higher than the reflectivity of the dielectric DBR layer.

3. The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 1, wherein the bottom porous DBR layer has a material of a multi-periodic DBR formed by stacking porous nitride layers and non-porous nitride layers alternately.

4. The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 1, wherein the current limiting layer is made of SiO.sub.2, SiNX, HfO.sub.2 or Al.sub.2O.sub.3.

5. The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 1, wherein an n-type GaN layer is further grown between the bottom porous DBR layer and the buffer layer, and is used as a current spreading layer applied for electrochemical etching to form the bottom porous DBR layer.

6. The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 1, wherein the lightly doped layers have a doping concentration of 5×10.sup.16 cm.sup.−3 and the heavily doped layers have a doping concentration of 1×10.sup.19 cm.sup.−3.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) To make the objectives, technical solutions, and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in conjunction with the specific embodiments and with reference to the accompanying drawings. Here, a green porous DBR and its VCSEL will be described as a preferred embodiment. Wherein:

(2) FIG. 1 is a schematic structural view according to an embodiment of the present disclosure;

(3) FIG. 2 is a flow chart of the manufacturing according to an embodiment of the present disclosure;

(4) FIG. 3 is a picture of a scanning electron microscope of the bottom porous DBR of FIG. 1; and

(5) FIG. 4 is the reflection spectrum corresponding to FIG. 3.

DETAILED DESCRIPTION

(6) In the present disclosure, the terms “include” and “comprise” and their derivatives are intended to be inclusive and not limiting.

(7) It should be noted that the directional terms mentioned in the present disclosure, such as “upper”, “lower”, “front”, “back”, “left”, “right”, and the like, are only referring to the directions of the drawings, and not used to limit the scope of protection of the present disclosure. The same elements are denoted by the same or similar reference numerals throughout the drawings. Conventional structures or configurations will be omitted when they may cause confusion to the understanding of the present disclosure. The shapes and sizes of the various components in the drawings do not reflect the true size and proportions, but merely illustrate the contents of the embodiments of the present disclosure.

(8) Referring to FIG. 1, the present disclosure provides a GaN-based VCSEL chip based on porous DBR, including:

(9) A substrate 10, which may be a planar or patterned substrate and may be made of sapphire, Si or SiC;

(10) A buffer layer 11, formed on the upper surface of the substrate 10 and composed of a low-temperature GaN nucleation layer and an unintentionally doped GaN layer. High-purity pure ammonia gas may be used as a nitrogen source, and trimethylgallium or triethylgallium may be used as a Ga source. The GaN nucleation layer is first grown at a low temperature, and then the unintentionally doped GaN layer is grown at a high temperature. The material which may be used as the nucleation layer also includes AlN, ZnO or graphene;

(11) A bottom porous DBR layer 12 formed on the upper surface of the buffer layer 11. The material of the bottom porous DBR layer 12 is GaN, AlGaN, InGaN or AlInGaN, or a combination of the above materials, and the bottom porous DBR layer 12 is a multi-periodic DBR formed by stacking porous layers and non-porous layers alternately;

(12) Wherein, the bottom porous DBR layer 12 is obtained by electrochemical etching of the lightly doped layer and the heavily doped layer which are alternately stacked, wherein the typical doping concentration of the heavily doped layer is 1×10.sup.19 cm.sup.−3, the typical doping concentration of the lightly doped layer is 5×10.sup.16 cm.sup.−3, and the number of periods of the bottom porous DBR layer 12 may be 12;

(13) An n-type GaN layer is further grown between the bottom porous DBR layer 12 and the buffer layer 11, and is used as a current spreading layer applied for electrochemical etching to form the bottom porous DBR layer 12;

(14) An n-type doped GaN layer 13, with the dopant of silane and the typical doping concentration of 1×10.sup.18 cm.sup.−3, formed on an upper surface of the bottom porous DBR layer 12, wherein the n-type doped GaN layer 13 is etched downward on its periphery to form a mesa 13′ having a depth smaller than the thickness of the n-type doped GaN layer 13, and the middle of the n-type doped GaN layer 13 is a convex portion 13″;

(15) An active layer 14 formed on the convex portion 13″ of the n-type doped GaN layer 13. The active layer 14 is an InGaN/GaN multiple quantum well structure, the peak wavelength of which is near 520 nm and corresponds to the high reverse band of the bottom porous DBR layer 12, so as to realize the matching of the light emission wavelength and the resonance wavelength;

(16) An electron blocking layer 15 formed on the upper surface of the active layer 14. The electron blocking layer 15 is made of AlGaN, which may be p-type doped with the dopant of ferrocene;

(17) A p-type doped GaN layer 16 formed on the upper surface of the electron blocking layer 15;

(18) A current limiting layer 17, which may be an insulating medium and formed on the upper surface and side surfaces of the p-type doped GaN layer 16. A current window 17′ is formed at the center of the current limiting layer 17 to achieve carrier narrowing, and a typical current window is a circular hole pattern having a diameter of 10-30 μm. The current limiting layer 17 covers the sidewalls of the active layer 14, the electron blocking layer 15, and the convex portion 13″ of the n-type doped GaN layer 13, and covers a portion of the mesa 13′, so as to achieve sidewall passivation, reducing leakage paths of the device;

(19) The material of the current limiting layer 17 is SiO.sub.2, SiN.sub.x, HfO.sub.2 or Al.sub.2O.sub.3;

(20) A transparent electrode 18 formed at the current limiting layer 17 over the p-type doped GaN layer 16 and the current window 17′. The material that may be used as the transparent electrode includes indium-doped tin oxide ITO, graphene, ZnO thin film, transparent metal or nano silver wire, or a composite film material of the above materials;

(21) An n-electrode 20 formed on the mesa 13′ of the n-type doped GaN layer 13;

(22) A p-electrode 21 formed on the periphery of the transparent electrode 18 with a recess formed therein;

(23) The metal material used for the n-electrode 20 and the p-electrode 21 is Cr/Al/Ti/Au, Cr/Pt/Au, Ni/Au, Ni/Ag/Pt/Au, Ti/Au or Ti/Pt/Au;

(24) A dielectric DBR layer 19 formed, as a top mirror, on the upper surface of the transparent electrode 18 in the recess of the p-electrode 21. The dielectric DBR layer 19 may have a multi-periodic SiO.sub.2/TiO.sub.2, SiO.sub.2/Ta.sub.2O.sub.5, TiO.sub.2/Al.sub.2O.sub.3 or ZrO.sub.2/SiO.sub.2 structure. A phase adjustment layer is also included in the dielectric layer near the transparent electrode 18 to adjust the electric field distribution in the VCSEL and reduce the absorption loss of the transparent electrode 18 as much as possible.

(25) The dielectric DBR layer 19 and the bottom porous DBR layer 12 constitute upper and lower mirrors of the VCSEL chip respectively, and the bottom porous DBR layer 12 has a reflectivity of above 95% at a peak wavelength of the active layer 14, which is higher than the reflectivity of the dielectric DBR layer 19 to allow the VCSEL device to emit light from the side of the top dielectric DBR layer.

(26) Referring to FIG. 2, and in conjunction with FIG. 1, the present disclosure provides a method for manufacturing a GaN-based VCSEL chip based on porous DBR, comprising the following steps:

(27) Step 1: growing the buffer layer 11, alternately stacked lightly doped layers and heavily doped layers, the n-type doped GaN layer 13, the active layer 14, the electron blocking layer 15, and the p-type doped GaN layer 16 on the substrate 10 sequentially;

(28) The material of the substrate 10 is sapphire, Si or SiC. The material of the bottom porous DBR layer 12 is a multi-periodic DBR formed by stacking porous nitride layers and non-porous nitride layers alternately, and the constituent material is GaN, AlGaN, InGaN or AlInGaN, or a combination of the above materials. An n-type GaN layer is further grown between the bottom porous DBR layer 12 and the buffer layer 11, and is used as a current spreading layer applied for electrochemical etching to form the porous DBR;

(29) Step 2: performing lateral etching on the alternately stacked lightly doped layers and heavily doped layers by using an electrochemical etching method, so as to transform them to a bottom porous DBR layer 12 in which porous layers and non-porous layers are alternately stacked;

(30) Step 3: etching down on the periphery of the p-type doped GaN layer 16 by a depth so that a portion of the n-type doped GaN layer 13 is etched, so as to form a mesa 13′ on the periphery of the n-type doped GaN layer 13;

(31) Step 4: forming the current limiting layer 17 on the sidewalls of the p-type doped GaN layer 16, the mesa 13′, the active layer 14, and the electron blocking layer 15 to achieve carrier narrowing and sidewall passivation, and to reduce the leakage paths of the device; wherein the material of the current limiting layer 17 is SiO.sub.2, SiN.sub.x, HfO.sub.2 or Al.sub.2O.sub.3;

(32) Step 5: forming the current window 17′ on the current limiting layer 17, and removing a portion of the current limiting layer 17 on the mesa 13′, using a photolithography or etching technique;

(33) Step 6: forming the transparent electrode 18 at the current window 17′ on the p-type doped GaN layer 16;

(34) Step 7: forming the n-electrode 20 and the p-electrode 21 on the mesa 13′ on which a portion of the current limiting layer 17 is removed and the periphery of the transparent electrode 18 respectively, wherein a recess is formed in a middle of the p-electrode 21;

(35) The metal material used for the n-electrode 20 and the p-electrode 21 is Cr/Al/Ti/Au, Cr/Pt/Au, Ni/Au, Ni/Ag/Pt/Au, Ti/Au or Ti/Pt/Au;

(36) Step 8: forming the dielectric DBR layer 19 on the upper surface of the transparent electrode 18 in the recess of the p-electrode 21 to complete the manufacturing of the device. The dielectric DBR layer 19 is a multi-periodic SiO.sub.2/TiO.sub.2, SiO.sub.2/Ta.sub.2O.sub.5, TiO.sub.2/Al.sub.2O.sub.3 or ZrO.sub.2/SiO.sub.2 structure.

(37) Referring to FIG. 3, and in conjunction with FIG. 4, the present disclosure provides a picture of a scanning electron microscope of the GaN-based bottom porous DBR layer 12 and its corresponding reflection spectrum. The porous layers in FIG. 3 are the heavily doped GaN layers after electrochemical etching, and the uncorroded GaN layers are the lightly doped layers. The two layers of material have a refractive index difference due to the introduction of the air gaps and are alternately stacked to form the bottom porous DBR layer. In the reflection spectrum of FIG. 4, the abscissa is the wavelength and the ordinate is the reflectivity. As can be seen from the reflection spectrum, the bottom porous DBR layer 12 has a very high reflectivity and a wide high reflection band near 520 nm, which may meet the requirements of GaN-based green VCSELs for high reflectivity bottom mirrors.

(38) With the lateral porous DBR of the embodiments of the present disclosure, the technical barrier of the high-reflectivity bottom mirror of the resonant cavity can be fundamentally broken. By electrochemical etching of the periodic GaN epitaxial structure in which non-doped layers (or lightly doped layers) and heavily doped layers are alternately stacked, lateral air channels can be selectively formed in the heavily doped layers, thus changing the effective refractive indexes of the layers, while the non-doped layers (or lightly doped layers) are not affected by the etching. The introduction of the air gaps will cause a certain refractive index difference between the porous GaN layers and the non-porous GaN layers, thereby forming a DBR composite structure in which the porous GaN layers and the non-porous GaN layers are alternately stacked. On this basis, the GaN-based VCSEL is manufactured using the dielectric DBR layer as the top mirror.

(39) The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only specific embodiments of the present disclosure and is not used to limit the present disclosure. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure shall fall within the protection scope of the present disclosure.