INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION

Abstract

Integrated circuits (ICs) include electrostatic discharge protection including a transistor having a drain operably coupled to a first rail of the integrated circuit and a source operatively coupled to a second rail of the integrated circuit. A voltage regulating trigger circuit is operatively coupled to the first rail and to a gate of the transistor to turn on of the transistor responsive to an ESD event affecting the integrated circuit, wherein the voltage regulating trigger circuit limits a potential of the first rail to a first potential and a gate potential of the transistor to a second potential, less than the first potential but sufficient to turn the transistor on to conduct current arising from the ESD event from the first rail to the second rail.

Claims

1. An integrated circuit electrostatic discharge (ESD) protection circuit comprising: a transistor having a drain operably coupled to a first rail of the integrated circuit and a source operatively coupled to a second rail of the integrated circuit; and a voltage regulating trigger circuit operatively coupled to the first rail and to a gate of the transistor to drive the transistor responsive to an ESD event affecting the integrated circuit, wherein the voltage regulating trigger circuit limits a potential of the first rail to a first potential and a gate potential of the transistor to a second potential, less than the first potential but sufficient to turn the transistor on to conduct current arising from the ESD event from the first rail to the second rail.

2. The ESD protection circuit of claim 1, wherein the voltage regulating trigger circuit is configured to limit the second potential to a potential of a third rail of the integrated circuit that is less than the first potential.

3. The ESD protection circuit of claim 1, wherein the voltage regulating trigger circuit is configured to limit the second potential to be at or below 6V (volts).

4. The ESD protection circuit of claim 1, the transistor comprising a nMOSFET.

5. The ESD protection circuit of claim 1, wherein the voltage regulating trigger circuit comprises a voltage clamp.

6. The ESD protection circuit of claim 5, wherein the voltage clamp comprises a diode stack operatively coupled between the first rail and the gate.

7. The ESD protection circuit of claim 1, comprising a disable/enable device coupled to the voltage regulating trigger circuit.

8. The ESD protection circuit of claim 7, the disable/enable device comprising a low potential addressable transistor.

9. An integrated circuit comprising: a first rail at a first voltage potential, a second rail at a second voltage potential and a third rail at a third voltage potential, wherein the first potential, the second potential and the third potential are all different from each other, an electrostatic discharge (ESD) protection circuit disposed within the integrated circuit and operatively coupled to the first rail, the second rail and the third rail, the ESD protection circuit including a transistor operably disposed between the first rail and the second rail, and a voltage regulating trigger circuit coupled to the first rail and to the transistor to turn on of the transistor responsive to an ESD event, wherein the voltage regulating trigger circuit limits a potential of the first rail to a first potential and a gate potential of the transistor to a second potential, less than the first potential, such that the transistor is enabled to conduct current from the first rail to the second rail responsive to an ESD event.

10. The integrated circuit of claim 9, wherein the voltage regulating trigger circuit is configured to limit the second potential to a potential of the third rail that is less than the first potential.

11. The integrated circuit of claim 9, wherein the voltage regulating trigger circuit is configured to limit the second potential to be at or below 6V (volts).

12. The integrated circuit of claim 9, the transistor comprising a nMOSFET having a drain coupled to the first rail, a source coupled to the second rail, and a gate coupled to the voltage regulating trigger circuit.

13. The integrated circuit of claim 9, wherein the voltage regulating trigger circuit comprises a voltage clamp.

14. The integrated circuit of claim 13, wherein the voltage clamp comprises a diode stack operatively coupled between the first rail and a gate of the transistor.

15. The ESD protection circuit of claim 1, comprising a disable/enable device coupled to the voltage regulating trigger circuit, the disable/enable device operable to selectively disable/enable the ESD protection circuit.

16. The ESD protection circuit of claim 15, the disable/enable device comprising a low potential addressable transistor.

17. A method of providing electrostatic discharge protection within an integrated circuit, the integrated circuit having a first rail, a second rail and a third rail, and a transistor having a drain couple to the first rail and a source coupled to the second rail, the method comprising: clamping a potential of the first rail to a hold potential; and providing a second potential, less than the first potential, to a gate of the transistor enabling the transistor to conduct current from the first rail to the second rail in response to an ESD event affecting the integrated circuit.

18. The method of claim 17, wherein providing the second potential, less than the first potential, to the gate of the transistor comprises providing the second potential being equal to or less than a potential of the third rail.

19. The method of claim 17, wherein providing the second potential, less than the first potential, to the gate of the transistor comprises limiting a voltage of the first rail to the second potential to provide a limited voltage, and providing the limited voltage to the gate.

20. The method of claim 17, comprising selectively disabling the electrostatic discharge protection with normal operation of the integrated circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:

[0021] FIG. 1 is a schematic circuit diagram of an integrated circuit with at least one electrostatic discharge protection circuit in accordance with the herein described embodiments;

[0022] FIG. 2 is a schematic circuit diagram of an embodiment of an electrostatic discharge protection circuit that may be used in the IC configuration depicted in FIG. 1;

[0023] FIG. 3 is a schematic circuit diagram of an alternative embodiment of an electrostatic discharge protection circuit that may be used in the IC configuration depicted in FIG. 1; and

[0024] FIG. 4 is a schematic circuit diagram of an alternative embodiment of an electrostatic discharge protection circuit that may be used in the IC configuration depicted in FIG. 1.

DETAILED DESCRIPTION

[0025] The following detailed description is merely exemplary in nature and is not intended to limit the various embodiments or the application and uses thereof. Furthermore, there is no intention to be bound by any theory presented in the preceding background or the following detailed description. Embodiments of the present disclosure are generally directed to integrated circuits, and methods for configuring and operating the same. The various structures, elements, tasks and steps described herein may be incorporated into a more comprehensive structure, procedure or process having additional elements, steps or functionality not described in detail herein. In particular, many structures, designs and methods of producing integrated circuits are well-known and so, in the interest of brevity, many conventional aspects of integrated circuits will only be mentioned briefly herein or will be omitted entirely without providing the well-known details.

[0026] Referring to the exemplary embodiment depicted in FIG. 1, an integrated circuit (IC) 10 includes internal circuitry 12 and an ESD event triggered protection circuit 20. The protection circuit 20 protects a high potential (30V-100V or more) VHdd power supply rail 22, and hence the internal circuitry 12, from an ESD event, graphically depicted in FIG. 1 as ESD event 14, referenced to grounded Vss power supply rail 24.

[0027] The IC 10 further includes a double diode (pulling up and pulling down, respectively) network 16 that includes diodes 46 and 48. In a typical configuration, the diode 46 is a P+/N-well or P+/NW diode, while the diode 48 may be a N+/Substrate or N+/SX diode. The diode network 16 may be replaced with other ESD protection structures configured to direct current resulting from an ESD event to the protection circuit 20. Suitable structures may include N-FET-based or silicon controlled rectifier (SCR)-based ESD structures. One of skill in the art will appreciate that still other alternative arrangements may be utilized to appropriately direct or discharge ESD current within the IC responsive to an ESD event.

[0028] As noted, the diode network directs ESD event related current along desired paths for positive and negative ESD pulses, respectively. For example, FIG. 1 further illustrates possible current paths 28 resulting from a positive or negative ESD event at either the VHdd rail 22 or the VLdd rail 18. Forming the current path 28, the diodes 46 and 48 direct the ESD event related current away from the internal circuitry 12 allowing the protection circuit 20 to effectively clamp the ESD event related voltage and shunt the ESD event related current.

[0029] Protection circuit 20 as illustrated in FIG. 2 may include a voltage limiting trigger circuit 30. Together protection circuit 20 and trigger circuit 30 form an effective ESD protection arrangement to clamp ESD voltage below damaging levels and to shunt ESD current responsive to an ESD event affecting the IC 10. In an exemplary embodiment, the trigger circuit 30 clamps the potential of the VHdd rail 22 to a first potential while also turning on the transistor 36 by providing a gate 38 turn on voltage at a second potential less than the first potential such that the transistor 36 is operable to conduct current from the first rail VHdd 22 to the second rail Vss 24.

[0030] The trigger circuit 30 operatively couples a sampling circuit 32 and a pre-amp 34 to provide a gate voltage, Vg, to the gate 38 of the transistor 36, which is usually a nMOSFET, of the protection circuit 20. The drain 40 of the transistor 36 is operatively coupled to VHdd rail 22 and its source 42 to Vss rail 24. The sampling circuit 32 is operatively coupled to receive a reference voltage 44 and is further operatively coupled to VHdd rail 22. If the gain of the pre-amp 34 is A, and the transistor 36 has a transconductance gm, the holding voltage will be clamped as Vhold˜=Vref as long as A*gm>>1.

[0031] FIG. 3 presents a protection circuit 100 in accordance with an alternative embodiment, and wherein like elements are identified with like reference numerals to the embodiment illustrated in FIG. 2. The protection circuit 100 includes transistor 36, such as an nMOSFET, that is operatively coupled between the VHdd rail 22 and the Vss rail 24. The gate 38 of the transistor 36 is coupled to a trigger circuit 102 at the source 104 of a trigger transistor 106 of the trigger circuit 102.

[0032] The trigger circuit 102 has as an operable element diode stack 108 that includes at least one, and in most implementations, several diodes 110. Depicted in FIG. 3 are two (2) diodes 110 in the diode stack 108. Each of the diodes 110 may be of the same type, and in the illustrated embodiment the diodes 110 are Zener diodes. As Zener diodes are known to act as ideal diodes in a forward direction, but to also allow current flow in the reverse direction responsive to the bias voltage exceeding the Zener breakdown voltage, e.g., a threshold voltage, the skilled person will appreciate that other suitable structures providing a low resistance forward path and a reverse current path responsive to a threshold voltage may be used in addition to or in place of the diode stack. Suitable structures may be N-FET or SCR-based.

[0033] The diodes 110 are reverse biased from VHdd rail 22 to the drain 112 of the trigger transistor 106 which may be a pMOSFET. The gate 114 of the trigger transistor 106 is operatively coupled via a resistor 116 to Vss rail 24 and the gate 114 is further coupled via a reverse biased diode 118 to Vss rail 24. The diode 118 may also be a Zener type diode. The source 104 of the trigger transistor 106 is operatively coupled to Vss rail 24 via a resistor 122.

[0034] In an embodiment, to ensure the trigger circuit 102, and in particular the trigger transistor 106, is off during normal operation, the voltage drop of the diode stack 108 in the trigger circuit 102 is made to be greater than the voltage of VHdd rail 22. The voltage of the diode stack 108 should satisfy N*Vz>VHdd; where N is the number of diodes 110 and Vz is the individual Zener diodes' reverse breakdown voltage.

[0035] During an ESD event, such as ESD event 12 as depicted in FIG. 1 affecting integrated circuit 10, the VHdd rail 22 is limited to a hold voltage Vhold, while the gate 114 of trigger transistor 106 is held at a voltage less than Vhold and/or VHdd, and to approximately VLdd. During the ESD event, the VHdd rail 22 holding voltage will be clamped to: Vhold˜=N*Vz+Vgs1, where Vgs1 is the G/S voltage of the trigger transistor 106 and is typically from 1 to 2V.

[0036] Advantageously, the turn on resistance of the transistor 36 is low, providing associated benefit toward the dissipation of the ESD event 12. The turn on resistance, Ron, is determined as: Ron=1/(gm*gm1*R1), where gm is the transconductance of transistor 36, gm1 is the transconductance of the trigger transistor 106 and R1 is the resistance of the resistor 122 coupling the trigger transistor source 106 to Vss rail 24.

[0037] Thus it will be appreciated, in accordance with the herein described embodiments, responsive to an ESD event, electronic circuitry such as protection circuit 20 and trigger circuit 30, may be provided to clamp a potential of a VHdd rail 22 to a first or hold potential. The transistor 36 of the protection circuit 20 is turned on, e.g., enabled, to shunt current from the VHdd rail 22 to Vss rail 24. The gate voltage, Vg, of the transistor 36 is limited also by the trigger circuit 30 to a value that is less than Vhold and/or to the normal potential of VHdd rail 22.

[0038] FIG. 4 presents a protection circuit 200 in accordance with an alternative embodiment similar to the protection circuit 100, and wherein like elements are identified with like reference numerals as illustrated in FIG. 3. The protection circuit 200 includes transistor 36 that couples the VHdd rail 22 and the Vss rail 24. The gate 38 of the transistor 36 is coupled to the trigger circuit 102.

[0039] Within the trigger circuit 102, a disable/enable device 202 is provided. The disable/enable device 202 may be internally or externally addressed to disable/enable the trigger circuit 102. With the trigger circuit 106 disabled, the ESD protection circuit 20 is disabled. This ensures the ESD clamp circuit 20 does not interfere with normal operation of the IC 10.

[0040] In the embodiment illustrated in FIG. 4 that includes the disable/enable device 202, a transistor 204 of the disable/enable device 202, e.g., a n-field effect transistor (nFET) is coupled at the gate 38 of the transistor 36. The gate 206 of the transistor 204 may be coupled to VLdd rail 18. In the illustrated configuration, the disable/enable device 202 is high-effective. As a result, upon normal chip-on operation, with VLdd rail 18 at its operative potential, the disable/enable device disables the protection circuit 200. During manufacturing processes or other handling of the IC, without power application to the IC 10, the disable/enable device 202 enables the protection circuit 200.

[0041] It will be appreciated from the foregoing discussion, that a method of dissipating an ESD event within an IC circuit with a tri-rail configuration may include providing a clamp circuit and a trigger circuit. The clamp circuit and the trigger circuit are operative such that upon an ESD event, the trigger circuit engages the clamp circuit to act as a power clamp to limit damaging effects of the ESD event. The clamp circuit limits a voltage on the VHdd rail of the IC to a hold voltage, while the trigger circuit operates and limits a gate voltage of the transistor to much less than the VHdd rail voltage, and to VLdd, for example, or approximately 6V in some embodiments to turn on a transistor.

[0042] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the application in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing one or more embodiments, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope, as set forth in the appended claims.