Apparatus and Method for Remote Power and Control of Electric Loads

Abstract

A system and method for controlling an electrical load are provided. A power supply converts an AC power signal to a DC power signal having a ripple voltage whose valley voltage approaches zero volts when the AC power signal crosses zero volts. A buss conducts the DC power signal. A transmitter is electrically coupled to the buss and receives electrical power from the DC power signal. The transmitter sends a command by selectively biasing one or more valley voltages of the DC power signal to a predetermined non-zero voltage. A load control system is electrically coupled to the buss and configured to receive electrical power from the DC power signal. The load control system determines a length of one or more sequences of dial pulses, which include DC power signal cycles where the valley voltage is not biased to the predetermined non-zero voltage. The load control system also generates a control signal based on the determined lengths of dial pulse sequences, where the control signal is configured to control an electric load.

Claims

1. A system for controlling an electric load, comprising: a power supply, configured to convert an AC power signal to a DC power signal having a ripple voltage whose valley voltage approaches zero volts when the AC power signal crosses zero volts; a buss, configured to conduct the DC power signal; a transmitter, electrically coupled to the buss and configured to: receive electrical power from the DC power signal, and send a command by selectively biasing one or more valley voltages of the DC power signal to a predetermined non-zero voltage; and a load control system, electrically coupled to the buss and configured to: receive electrical power from the DC power signal, determine a length of one or more sequences of dial pulses comprising DC power signal cycles where the valley voltage is not biased to the predetermined non-zero voltage, and generate a control signal based on the determined lengths, wherein the control signal is configured to control an electric load.

2. The system of claim 1, wherein the power supply comprises a full wave bridge rectifier.

3. The system of claim 2, wherein the transmitter comprises: a threshold detector configured to generate 12 volt drive pulses synchronized to the DC power signal to bias one or more valley voltages of the DC power signal to 12 volt; and a shift register configured to generate dial pulses in response to a keypad, where the dial pulses inhibit the 12 volt bias buffered to the buss.

4. The system of claim 2, wherein the transmitter is configured to be bridged across the buss at any point by a two wire loop.

5. The system of claim 3, wherein the load control system comprises: a dial pulse detector circuit configured to detect dial pulses in the DC power signal; and a logic decoder circuit configured to generate a control signal based on detected dial pulses.

6. The system of claim 5, wherein the logic decoder circuit generates the control signal based on a first sequence of drive pulses representing an address, a second sequence of drive pulses validating the address, and a third sequence of drive pulses representing the command.

7. The system of claim 5, comprising a master module and a one or more slave modules, wherein: the master module comprises the power supply and a first load control system; and each slave module comprises an additional load control system without a power supply.

8. The system of claim 1, wherein the control signal is one of an analog signal and a digital signal.

9. The system of claim 1, wherein the electric load is powered from the buss.

10. A method of controlling an electric load, the method comprising: converting an AC power signal to a DC power signal having a ripple voltage whose valley voltage approaches zero volts when the AC power signal crosses zero volts; conducting the DC power signal on a buss; sending a command by selectively biasing one or more valley voltages of the DC power signal to a predetermined non-zero voltage; and controlling an electric load by generating a control signal based on determined lengths of one or more sequences of dial pulses comprising DC power signal cycles where the valley voltage is not biased to the predetermined non-zero voltage, where the control signal is operable to control an electric load.

11. The method of claim 10, wherein the AC power signal is converted to a DC power signal using a full wave bridge rectifier.

12. The method of claim 11, wherein transmitting a control signal comprises: generating 12 volt drive pulses synchronized to the DC power signal to bias one or more valley voltages of the DC power signal to 12 volt; and generating dial pulses in response to a keypad, where the dial pulses inhibit the 12 volt bias buffered to the buss.

13. The method of claim 12, wherein controlling an electric load comprises: detecting dial pulses in the DC power signal; and generating a control signal based on detected dial pulses.

14. The method of claim 13, wherein generating a control signal based on detected dial pulses comprises detecting on a first sequence of drive pulses representing an address, a second sequence of drive pulses validating the address, and a third sequence of drive pulses representing the command.

15. The method of claim 13, wherein: converting an AC power signal to a DC power signal, and controlling a first electric load are performed in a master module; and controlling additional electric loads is performed in one or more associated slave modules.

16. The method of claim 10, wherein the control signal is one of an analog signal and a digital signal.

17. A load control system configured to: electrically couple to a buss and receive electrical power from a DC power signal conducted by the buss; determine a length of one or more sequences of dial pulses comprising DC power signal cycles where the valley voltage is not biased to a predetermined non-zero voltage; and generate a control signal based on the determined lengths, wherein the control signal is configured to control an electric load.

18. The load control system of claim 17, comprising: a dial pulse detector circuit configured to detect dial pulses in the DC power signal; and a logic decoder circuit configured to generate a control signal based on detected dial pulses.

19. The load control system of claim 18, wherein the logic decoder circuit generates the control signal based on a first sequence of drive pulses representing an address, a second sequence of drive pulses validating the address, and a third sequence of drive pulses representing a command.

20. The load control system of claim 17, wherein the control signal is one of an analog signal and a digital signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts:

[0008] FIG. 1 illustrates a lighting system according to one embodiment of the disclosure.

[0009] FIG. 2 illustrates a full wave bridge rectifier according to one embodiment of the disclosure.

[0010] FIG. 3 illustrates a DC waveform produced by the circuit of FIG. 2.

[0011] FIG. 4 shows a keypad transmitter according to one embodiment of the disclosure.

[0012] FIG. 5 illustrates a buss composite waveform produced by the circuit of FIG. 4 according to one embodiment of the disclosure.

[0013] FIG. 6 illustrates a dial pulse detector circuit and buck regulator according to one embodiment of the disclosure.

[0014] FIG. 7 illustrates a clock generation circuit according to one embodiment of the disclosure.

[0015] FIG. 8 illustrates a logic decoder circuit according to one embodiment of the disclosure.

[0016] FIG. 9 shows a timing diagram for the logic decoder circuit of FIG. 8 according to one embodiment of the disclosure.

[0017] FIG. 10 illustrates an embodiment of the disclosure configured for contactor control of an electric motor.

DETAILED DESCRIPTION

[0018] FIGS. 1 through 10, discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged system and method for remote power and control of electric loads.

[0019] A system and method of the present disclosure provide a control system that can be applied to dimming ballasts as well as other remote control systems for parallel loads. There are many commercial dimming ballasts available with no basic control systems available.

[0020] FIG. 1 illustrates a lighting system 100 according to one embodiment of the disclosure. The block diagram of FIG. 1 illustrates how the control system can be applied to dimming ballast installations, new or retrofit of systems. The system 100 includes an AC power source 106, a master lighting fixture 102, one or more slave lighting fixtures 104, a buss 112 coupling the master lighting fixture 102 to the slave lighting fixture(s) 104, and a keypad transmitter 110 coupled to the buss 112. The master lighting fixture 102 includes a master module and fluorescent lamps powered by a dimming ballast circuit. The slave lighting fixture 104 includes a slave module and fluorescent lamps powered by a dimming ballast circuit. The keypad transmitter 110 encodes onto the buss 112 control signals that control the master lighting fixture 102 and the slave lighting fixture(s) 104. The master lighting fixture 102 decodes the control signals on the buss 112 to generate a control signal 114 to control its associated dimming ballast and lamps. The slave module of the slave lighting fixture 104 operates similarly.

[0021] FIG. 2 illustrates a power supply 200 according to one embodiment of the disclosure. The power supply 200 is a full wave bridge rectifier that converts an AC power signal to a DC power signal to provide power to a buss that conducts the DC power signal. FIG. 3 illustrates a DC waveform 300 produced by the circuit of FIG. 2. The waveform 300 has a peak voltage of 170 volts and a 120 Hz ripple that goes to zero volts. FIG. 4 shows a keypad transmitter 400 according to one embodiment of the disclosure that selectively biases the valley voltage of the buss to 12 volts. While the disclosure teaches biasing the valley voltage of the buss to 12 volts, it will be understood that in other embodiments the valley voltage may be biased to another predetermined non-zero voltage. FIG. 5 illustrates a buss composite waveform produced by the circuit of FIG. 4 according to one embodiment of the disclosure, when the keypad sends dial pulses over the buss.

[0022] FIG. 2 is a schematic of a full wave bridge rectifier formed by diodes D.sub.1 to D.sub.4 that convert AC power to DC power. The DC waveform shown in FIG. 3 and produced by the circuit of FIG. 2 has a 120 Hz ripple voltage that approaches zero when the AC crosses zero. Since the valley voltage falls below 12 volts, dial pulses can be inserted in the valley as a means to send dial pulses to buss interface circuits bridged across the buss. FIG. 4 shows a keypad transmitter according to one embodiment of the disclosure that can be bridged across the buss at any point by a two wire loop that replaces a wall switch. A buck regulator is formed by Q.sub.1, L.sub.1, C.sub.1, pulse width modulator, and other associated components shown in the schematic. The buck regulator converts the buss voltage to 12 v to operate the keypad transmitter and buffer amp Q.sub.2 and Q.sub.3.

[0023] In FIG. 4 resistors R.sub.4 and R.sub.5 scale the buss voltage so the CMOS gate Z1-1 functions as a threshold detector to generate 12 v drive pulses synchronized to the AC line. Resistor R.sub.6 and diode D.sub.3 limit the buss voltage so the gate output goes high to generate a 120 pulse-per-second (PPS) clock pulse when the buss voltage falls to 6 volts. The threshold detector generates 120 PPS clock pulses to synchronize the dial pulses to the buss voltage nulls.

[0024] The 120 PPS clock drives the shift register to generate dial pulses that inhibit the 12V bias buffered to the buss, for keypad control of the bus.

[0025] Transistor Q.sub.1 and the discrete components (including a voltage controlled pulse width modulator) implement a buck regulator to convert the 170 v buss voltage to 12 volts for the keypad transmitter module. FIG. 5 shows the buss 170 volts goes to zero during nulls when the 12 v dial pulses inhibit the minimum voltage to 12 volts when no dial pulses are transmitted. Missing pulses are generated to the logic detector (shown in FIG. 6) when the buss voltage goes to zero.

[0026] The keypad programs a shift register to generate dial pulses that inhibit the buss being biased to 12 volts during dial pulses.

[0027] FIG. 5 shows the buss composite waveform generated when the keypad dial pulses inhibit the 12 volt bias to the buss. The first four half cycles show the ripple voltage going to zero when the logic detector of FIG. 6 generates data pulses. Dial trains of five dial pulses (502) and four dial pulses (504) may be seen in the drawing.

[0028] FIG. 1 shows how the buss is distributed to fixtures to provide power and control. The master and slave modules respond to keypad transmitters to control the ballasts. A master fixture is the same as a slave fixture except the master fixture has the diode bridge that provides power to the buss. The key pad transmitter is bridged across the buss. Lights having two or three way switching can have keypad transmitters replace any switch that has access to the buss. Any fixture that has an AC source can be converted to a master by changing a slave module to a master module.

[0029] The buss load is limited by the diode bridge and the circuit breaker. The dimming ballast is powered from the buss and is controlled by a key pad transmitter module bridged across the buss. AC provides power to the master fixture, and the master fixture buss provides power to all slave fixtures.

Logic Decoder

[0030] FIG. 6 illustrates a circuit 600 comprising a dial pulse detector circuit and buck regulator according to one embodiment of the disclosure. The upper portion of the circuit of FIG. 6 detects dial pulses for the logic decoders. The CMOS gate Z1-1 threshold voltage is 45% of V.sub.CC so 0.45×12=5.4 volts. Zener diode D1 clamps the gate to 12 volts. When the buss voltage drops below 5.4 volts, Z1-1 output goes high to generate data pulses to the logic decoder shown in FIG. 8.

[0031] Q.sub.1 and associated components implement a buck regulator to convert the buss voltage to 12 volts. R.sub.2 biases Q.sub.1 on, so current through L.sub.1 charges C.sub.1. The voltage is scaled by R.sub.3 and R.sub.4 to close the control loop. Z.sub.2 is a voltage controlled pulse width modulator that controls Q.sub.1 to regulate the 12 volt output for the buss interface circuit.

[0032] When the keypad transmitter is not sending dial pulses, the buss voltage is biased to 12 volts during the buss nulls. When the keypad transmitter sends dial pulses, the 12 volt bias is inhibited in the nulls so the dial pulse detector shown in FIG. 6 puts out 12 voltage data pulses when data is being sent.

[0033] FIG. 7 illustrates a clock generation circuit 700 according to one embodiment of the disclosure. The clock generation circuit 700 generates 120 cycle Ø1 and Ø2 clocks when the buss is 60 volts and 130 volts. When R.sub.1 drops the buss voltage to 10.8 volts, R.sub.2 and R.sub.3 divide the 10.8 v to 5.4 v. Z1-4 output goes high and inverted to generate Ø1 clock low. When the V.sub.CC drops to 60 volts, the voltage drop to R.sub.3 goes to 5.4 v, the gate Z1-2 output goes high and inverted to generate Ø2 clock low. When the buss voltage rises to 60 volts, Ø1 goes high and when the buss goes to 130 volts, Ø2 goes high for Ø1 and Ø2.

[0034] FIG. 8 illustrates a logic decoder circuit 800 according to one embodiment of the disclosure. FIG. 9 shows waveforms of various signals within the logic decoder of FIG. 8. When dial pulses are being sent by the keypad transmitter, data pulses set Z.sub.1 S.sub.1 so Z.sub.1 Q.sub.1 can clock Z2 and Z3. Z1 stretches dial pulses (4) to data pulses (5). The clock Ø2 transfers the low on Z.sub.1 D.sub.1 to Z.sub.1 D.sub.2. If a data pulse (4) comes in, it sets Z.sub.1 Q.sub.1 high to clock Z2 and Z3, so the next clock Ø1 transfers another high (5) into Z.sub.1Q.sub.2 and Q.sub.2 remains high as long as data pulses are received.

[0035] When no data pulse is received, the clock Ø2 (3) transfers the low on Z.sub.1 D.sub.1 to Z.sub.1 Q.sub.1 and this is clocked through to Z.sub.1 Q.sub.2. When Z.sub.1 Q.sub.2 goes low, Z.sub.1 Q.sub.2 (7) goes high to enable Z4-1 so clock Ø2 (3) generates a RESET (8) to Z2 and Z3. When Z.sub.1 Q.sub.2 (7) goes high, Z.sub.4 Cl.sub.1 is incremented to read Z.sub.4 D.sub.1.

[0036] An invalid address will set Z.sub.4 Q.sub.1 low, so clocking the program counter Z.sub.4 will transfer the Z.sub.3 D.sub.1 low to Z.sub.3 Q.sub.1. Z.sub.4 Q.sub.1 is inverted high to the OR gate to Z.sub.8-1 D.sub.1. The next clock will transfer the high on Z.sub.8-1 D.sub.1 to Z.sub.8-1 Q.sub.1 (15) and reset the program counter Z.sub.4. Clock Ø1 (2) is inverted to reset Z.sub.8. At turn on, the power up reset Z.sub.10-3 sets Z.sub.5 and Z.sub.6, and sets Z.sub.8-1, which resets Z.sub.4-1. The power up reset also resets Z.sub.8-2.

Logic Decoder Portion of Dial Pulse Counter

[0037] The dial pulse counters Z2 and Z3 must not be reset before Z4. When Z.sub.1 Q.sub.2 goes high to Z.sub.9, the clock (3) will delay the reset (8) to Z.sub.2 and Z.sub.3 until after they are read by Z.sub.4. Z.sub.3 is a counter that strobes the switch SW.sub.1 so the switch is set to address the receiver when it is read by Z.sub.4 D.sub.1.

[0038] When the address counter Z.sub.3 and the dial pulse counter Z.sub.2 Q have been reset, the system is ready for a new cycle since an invalid address will reset the program counter Z.sub.4.

[0039] When a valid address is received, Z.sub.4 D.sub.1 is set high and a high is transferred into Z.sub.4 Q.sub.1. The high is inverted so Z.sub.4 D.sub.2 is low so the next clock will not transfer a high to Z.sub.4 Q.sub.2 to reset the program counter Z.sub.4. The next dial train will be a second valid address (sent to validate the address), so Z.sub.4 D.sub.1 is set high again. When the program counter Z.sub.4 is clocked, the high on Z.sub.4 D.sub.1 will shift D.sub.1 into Z.sub.4 Q.sub.1 and Q.sub.1 will shift into Q.sub.2. The high on Z.sub.4 Q.sub.1 will be inverted by the inverter so Z.sub.8 D.sub.1 will be low and the low transferred to Z.sub.4 Q.sub.1 by the clock so the program counter Z.sub.4 will not be reset. A valid address does not recycle the system.

[0040] The third dial train is a command and when the program counter Z.sub.4 is clocked, Z.sub.4 Q.sub.1 and Z.sub.4 Q.sub.2 are shifted to Z.sub.4 Q.sub.2 and Z.sub.4 Q.sub.3. When Q.sub.3 goes high it clocks Z.sub.5 and Z.sub.6 to read the dial pulse counter Z.sub.2. Z.sub.5/Z.sub.6 form a latch for the command that can be interfaced to digital or analog control systems. When Z.sub.4 Q.sub.3 goes high it drives the OR gate high so the next Ø2 (3) clock will transfer Z.sub.8 Q.sub.1 high to reset Z.sub.4. Clock Ø1 is inverted to reset Z.sub.8-1 so the cycle ends.

[0041] The latch Z.sub.5/Z.sub.6 output is a binary code. A resistor network implements a digital to analog converter. The digital to analog converter generates a 0-10 v analog voltage to control a dimming ballast output. In other embodiments, the binary output can be decoded to control digital systems.

[0042] Z.sub.8-2 is coupled to output 9 of Z.sub.3. When the keypad transmitter transmits a “9”, output 9 of Z.sub.3 toggles the flip-flop Z.sub.8-2 to turn the dimming ballast off by causing Q.sub.1 to pull the 0-10 volt source to ground.

[0043] FIG. 9 shows waveforms of various signals within the logic decoder of FIG. 8.

[0044] The master module and slave module of FIG. 1 both include the dial pulse detector circuit and buck regulator circuit 600, the clock generation circuit 700, and the logic decoder circuit 800. A slave module may also be referred to as a buss interface. The master module further includes the power supply circuit 200. One or more keypad transmitters 400 may be incorporated into the master module, the slave module(s), or may be separate from both the master module and the slave module(s).

[0045] While the embodiment shown in FIG. 1 is adapted to control a dimming ballast for lamps, it will be understood that, in other embodiments (such as that shown in FIG. 10), analog or digital output from the Logic Decoder may be used to control contactors, actuators, motors, and other controllable loads. Further, while the load in FIG. 1 (dimming ballast) is powered from the buss, it will be understood that in other embodiments loads under remote control of a system according to the disclosure may be locally powered, instead, to provide remote control of power levels greater than can be served solely by the buss.

[0046] In other embodiments, a keypad transmitter or optional control can be added for two-way communication when needed for terminal equipment to send data to other stations.

[0047] Although the present disclosure has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.