Three-Dimensional Vertical One-Time-Programmable Memory

Abstract

The present invention discloses a three-dimensional vertical read-only memory (3D-OTP.sub.V). It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string is vertical to the substrate and comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. The antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming.

Claims

1. A three-dimensional vertical read-only memory (3D-OTP.sub.V), comprising: a semiconductor substrate comprising a substrate circuit; at least a vertical OTP string formed on said semiconductor circuit, said OTP string comprising a plurality of vertically stacked OTP cells coupled to a vertical address line; each of said OTP cells comprises an antifuse layer, wherein said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming.

2. The 3D-OTP.sub.V according to claim 1, further comprising a plurality of vertically stacked horizontal address lines above said semiconductor circuit, wherein said OTP cells are formed at the intersection of said horizontal address lines and said vertical address line.

3. The 3D-OTP.sub.V according to claim 2, wherein said horizontal address lines comprises a first conductive material, and said vertical address line comprises a second conductive material.

4. The 3D-OTP.sub.V according to claim 2, wherein said horizontal address lines comprises a metallic material, and said vertical address line comprises a doped semiconductor material.

5. The 3D-OTP.sub.V according to claim 2, wherein said horizontal address lines comprises a doped semiconductor material, and said vertical address line comprises an oppositely-doped semiconductor material.

6. The 3D-OTP.sub.V according to claim 1, wherein each of said OTP cells further comprises a quasi-conductive layer.

7. The 3D-OTP.sub.V according to claim 2, wherein all OTP cells coupled to selected one of said horizontal address lines are read out in a single read cycle.

8. The 3D-OTP.sub.V according to claim 2, further comprising: at least a memory hole through said horizontal address lines; a vertical transistor formed in a first portion of said memory hole; wherein said OTP string is formed in a second portion said memory hole.

9. The 3D-OTP.sub.V according to claim 8, wherein said hole is filled with a doped semiconductor material.

10. The 3D-OTP.sub.V according to claim 1, wherein said OTP cells have more than two states, the OTP cells in different states having different resistance value.

11. A three-dimensional vertical read-only memory (3D-OTP.sub.V), comprising: a semiconductor substrate comprising a substrate circuit; a plurality of vertically stacked horizontal address lines above said semiconductor circuit; at least a memory hole through said plurality of horizontal address lines; an antifuse layer formed on the sidewall of said memory hole, wherein said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming; a vertical address line formed by filling at least a conductive material in said memory hole; a plurality of OTP cells formed at the intersections of said horizontal address lines and said vertical address line.

12. The 3D-OTP.sub.V according to claim 11, wherein said plurality of OTP cells form a vertical OTP string.

13. The 3D-OTP.sub.V according to claim 11, wherein said horizontal address lines comprises a first conductive material, and said vertical address line comprises a second conductive material.

14. The 3D-OTP.sub.V according to claim 11, wherein said horizontal address lines comprises a metallic material, and said vertical address line comprises a doped semiconductor material.

15. The 3D-OTP.sub.V according to claim 11, wherein said horizontal address lines comprises a doped semiconductor material, and said vertical address line comprises an oppositely-doped semiconductor material.

16. The 3D-OTP.sub.V according to claim 11, wherein each of said OTP cells further comprises a quasi-conductive layer.

17. The 3D-OTP.sub.V according to claim 11, wherein all OTP cells coupled to selected one of said horizontal address line are read out in a single read cycle.

18. The 3D-OTP.sub.V according to claim 12, further comprising a vertical transistor coupled to said OTP string.

19. The 3D-OTP.sub.V according to claim 18, wherein said vertical transistor is formed in a first portion of said memory hole, and said OTP string is formed in a second portion of said memory hole.

20. The 3D-OTP.sub.V according to claim 11, wherein said OTP cells have more than two states, the OTP cells in different states having different resistance value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1A is a z-x cross-sectional view of a first preferred 3D-OTP.sub.V; FIG. 1B is its x-y cross-sectional view along the cutline AA′;

[0018] FIGS. 2A-2C are cross-sectional views of the first preferred 3D-OTP.sub.V at three manufacturing steps;

[0019] FIG. 3A is a z-x cross-sectional view of a second preferred 3D-OTP.sub.V; FIG. 1B is its x-y cross-sectional view along the cutline BB′;

[0020] FIG. 4A is a symbol of the OTP cell; FIG. 4B is a circuit block diagram of a first preferred read-out circuit for an OTP array; FIG. 4C is its signal timing diagram; FIG. 4D shows the current-voltage (l-V) characteristic of a preferred quasi-conductive layer;

[0021] FIG. 5A is a z-x cross-sectional view of a third preferred 3D-OTP.sub.V; FIG. 5B is its x-y cross-sectional view along the cutline CC′; FIG. 5C is a circuit block diagram of a second preferred read-out circuit for an OTP array;

[0022] FIG. 6 is a cross-sectional view of a multi-bit-per-cell 3D-OTP.sub.V.

[0023] It should be noted that all the drawings are schematic and not drawn to scale. Relative dimensions and proportions of parts of the device structures in the figures have been shown exaggerated or reduced in size for the sake of clarity and convenience in the drawings. The same reference symbols are generally used to refer to corresponding or similar features in the different embodiments. The symbol “/” means a relationship of “and” or “or”.

[0024] Throughout the present invention, the phrase “on the substrate” means the active elements of a circuit are formed on the surface of the substrate, although the interconnects between these active elements are formed above the substrate and do not touch the substrate; the phrase “above the substrate” means the active elements are formed above the substrate and do not touch the substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Those of ordinary skills in the art will realize that the following description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons from an examination of the within disclosure.

[0026] Referring now to FIG. 1A-1B, a first preferred three-dimensional vertical one-time-programmable memory (3D-OTP.sub.V) is disclosed. FIG. 1A is its z-x cross-sectional view. It comprises a plurality of vertical OTP strings 1A, 1B . . . (shorthanded to OTP strings) formed side-by-side on the substrate circuit 0K. Each OTP string (e.g. 1A) is vertical to the substrate 0 and comprises a plurality of vertically stacked OTP cells 1aa-1ha.

[0027] The preferred embodiment shown in this figure is an OTP array 10, which is a collection of all OT cells sharing at least an address line. It comprises a plurality of vertically stacked horizontal address lines (word lines) 8a-8h. After the memory holes 2a-2d penetrating these horizontal address lines 8a-8h are formed, the sidewalls of the memory holes 2a-2d are covered with an antifuse layer 6a-6d before the memory holes 2a-2d are filled with at least a conductive material, which could be a metallic material or a doped semiconductor material. The conductive material in t the memory holes 2a-2d form vertical address lines (bit lines) 4a-4d.

[0028] The OTP cells 1aa-1ha on the OTP string 1A are formed at the intersections of the word lines 8a-8h and the bit line 4a. In the OTP cell 1aa, the antifuse layer 6a is a thin layer of insulating dielectric (e.g. silicon oxide, or silicon nitride). During programming, a conductive filament 11, which has a low resistance, is irreversibly formed therein. Except for the OTP cell 1aa, the conductive filaments in other OTP cells are not drawn.

[0029] FIG. 1B is its x-y cross-sectional view along the cutline AA′. Each of the horizontal address lines (word lines) 8a, 8a′ is a conductive plate. The horizontal address line 8a is coupled with eight vertical address lines (bit lines) 4a-4h. Eight OTP cells 1aa-1ah are formed at the intersections of the horizontal address 8a and the vertical address lines 4a-4h. All OTP cells 1aa-1ah coupled with a single horizontal address line 8a form an OTP-cell set 1a. Because the horizontal address line 8a is wide, it can be formed by a low-resolution photolithography (e.g. with feature size >60 nm).

[0030] Referring now to FIGS. 2A-2C, three manufacturing steps for the preferred 3D-OTP.sub.V are shown. First of all, vertically stacked horizontal address-line layers 12a-12h are formed in continuously forming steps (FIG. 2A). To be more specific, after the substrate circuit 0K (including transistors and the associated interconnects) are planarized, a first horizontal address-line layer 12a is formed. The first horizontal address-line layer 12a is just a plain layer of conductive materials and contains no patterns. Then a first insulating layer 5a is formed on the first horizontal address-line layer 12a. Similarly, the first insulating layer 5a contains no patterns. Repeating the above process until alternate layers of the horizontal address-line layers and the insulating layers (a total of M layers) are formed. “Continuously forming steps” means that these forming steps (for the horizontal address-line layer and the insulating layer) are carried out continuously without any in-between pattern-transfer steps (including photolithography). Without any in-between pattern-transfer steps, excellent planarization can be achieve. As a result, the 3D-OTP.sub.V comprising tens to hundreds of horizontal address-line layers can be formed. This is significantly more than the 3D-OPT.sub.H.

[0031] A first etching step is performed through all horizontal address-line layers 12a-12h to form a stack of horizontal address lines 8a-8h in (FIG. 2B). This is followed by a second etching step to form memory holes 2a-2d through all horizontal address lines 8a-8h (FIG. 2C). The sidewall of the memory holes 2a-2d is covered by an antifuse layers 6a-6d before the memory holes 2a-2d are filled with at least a conductive material to form the vertical address lines 4a-4d (FIG. 1A).

[0032] Referring now to FIG. 3A-3B, a second preferred 3D-OTP.sub.V 10 is disclosed. FIG. 3A is its z-x cross-sectional view; FIG. 3B is its x-y cross-sectional view along the cutline BB′. It is similar to FIG. 1A-1B, except that each memory hole (e.g. 2a) further comprises a quasi-conductive layer (e.g. 16a). The quasi-conductive layer 16a is the major component of a diode. It has the following properties: its resistance at the read voltage (read resistance) is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage. The quasi-conductive layers 16a-16d could be a ceramic layer (e.g. a metal-oxide layer). In this preferred embodiment, the quasi-conductive layers 16a-16d are formed between the sidewalls of the memory holes 2a-2d and the antifuse layers 6a-6d. Alternatively, the antifuse layers 6a-6d can be formed between the sidewalls of the memory holes 2a-2d and the quasi-conductive layer 16a-16d.

[0033] FIG. 4A is a symbol of the OTP cell 1. It means that the OTP cell 1 comprises an antifuse 12 and a diode 14. The antifuse 12 comprises the antifuse layer 6a-6d whose resistance is irreversibly switched from high to low during programming. The diode 14 comprises the quasi-conductive layer 16a-16d and can be broadly interpreted as any two-terminal device whose resistance at the read voltage is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage.

[0034] Exemplary diodes 14 include semiconductor diodes, Schottky diodes and ceramic diodes. For the semiconductor diodes 14, the horizontal address lines 8a-8h comprise a P+ semiconductor material, while the vertical address lines 4a-4d comprise an N+ semiconductor material. For the Schottky diodes 14, the horizontal address lines 8a-8h comprise a metallic material, while the vertical address lines 4a-4d comprise an N+ semiconductor material. For the ceramic diodes 14, ceramic layers (e.g. metal-oxide layers) separate the horizontal address lines 8a-8h from the b vertical address it lines 4a-4d.

[0035] In an OTP cell (e.g. 1aa), the dimension of the diode's cathode is equal to the radius of the memory hole (e.g. 2a). Because this cathode is too small to suppress the leakage current of the diode, the OTP cell could be leaky. To address this issue, the present invention discloses a full-read mode. For the full-read mode, all OTP cells on a selected word line are read out during a read cycle.

[0036] FIG. 4B discloses a first preferred read-out circuit for an OTP array 10. It runs in the full-read mode. In the language of electronic circuitry, the horizontal address lines 8a-8h are word lines, while the vertical address lines 4a-4h are bit lines. An OTP array 10 comprises the word lines 8a-8h, the bit lines 4a-4h, and the OTP cells 1aa-1ad . . . located at their intersections. Its peripheral circuits (located on the substrate 0 and is not part of the OTP array 10) comprise a multiplexor 40 and an amplifier 30. In this preferred embodiment, the multiplexor 40 is a 4-to-1 multiplexor.

[0037] FIG. 4C is its signal timing diagram. A read cycle T includes two read phases: a pre-charge phase t.sub.pre and a read-out phase t.sub.R. During the pre-charge phase t.sub.pre, all address lines 8a-8h, 4a-4h in the OTP array 10 are charged to a pre-determined voltage (e.g. an input bias voltage V.sub.i of the amplifier 30). During the read-out phase t.sub.R, all bit lines 4a-4h are floating. The voltage on a selected word line (e.g. 8a) is raised to the read voltage V.sub.R, while voltage on other word lines 8b-8h remains at the input bias voltage V.sub.i. After this, the selected word line 8a starts to charge all bit lines 4a-4h through the OTP cells 1aa . . . and the voltages on the bit lines 4a-4h begin to rise. The multiplexor 40 sends the voltage on each bit line (e.g. 4a) to the amplifier 30. When this voltage exceeds the threshold voltage V.sub.T of the amplifier 30, the output V.sub.O is toggled. At the end of the read cycle T, the states of all OTP cells 1aa-1ah in the OTP-cell set 1a are determined.

[0038] FIG. 4D shows the current-voltage (I-V) characteristic of a preferred quasi-conductive layer. Because the V.sub.T of the amplifier 30 is relatively small (˜0.1V or smaller), the voltage changes delta(V) on the bit lines 4a-4h during the above measurement are small, i.e. delta(V)˜V.sub.T. The reverse voltage on the unselected OTP cells (e.g. 1ca) is ˜V.sub.T. As long as the I-V characteristic of the quasi-conductive layer satisfies I(V.sub.R)>>|(−V.sub.T), the 3D-OTP.sub.V would work properly even with leaky OTP cells.

[0039] To facilitate address decoding, vertical transistors are formed on the sidewalls of the memory holes. FIGS. 5A-5C disclose a third preferred 3D-OTP.sub.V 10 comprising vertical transistors 3aa-3ad. The vertical transistor 3aa is a pass transistor comprising a gate 7a, a gate dielectric 6a and a channel 9a (FIG. 5A). The channel 9a is formed in the semiconductor material filled in the memory hole 2a. Its doping could be same as, lighter than, or opposite to that of the vertical address line 4a. The gate 7a surrounds the memory holes 2a, 2e and controls the pass transistors 3aa, 3ae (FIG. 5B); the gate 7b surrounds the memory holes 2b, 2f and controls the pass transistors 3ab, 3af; the gate 7c surrounds the memory holes 2c, 2g and controls the pass transistors 3ac, 3ag; the gate 7d surrounds the memory holes 2e, 2h and controls the pass transistors 3ae, 3ah. The pass transistors 3aa-3ah form at least a decoding stage (FIG. 5C). In one preferred embodiment, when the voltage on the gate 7a is high while the voltages on the gates 7b-7d are low, only the pass transistors 3aa, 3ae are turn on, with other pass transistors off. The substrate multiplexor 40′ is a 2-to-1 multiplexor which selects a signal from the bit lines 4a, 4e. By forming vertical transistors 3aa-3d in the memory holes 2a-2d, the decoder design could be simplified.

[0040] FIG. 6 discloses a multi-bit-per-cell 3D-OTP.sub.V. It comprises a plurality of OTP cells 1aa-1ah. In this preferred embodiment, the OTP cells 1aa-1ah have four states: ‘0’, ‘1’, ‘2’, ‘3’. The OTP cells 1aa-1ah in different states are programmed by different programming currents and therefore, have different resistance. The OTP cells 1ac, 1ae, 1ah are in the state ‘0’. Being un-programmed, their antifuse layers 6c, 6e, 6h are intact. Other OTP cells are programmed. Among them, the OTP cells lab, lag are in the state ‘1’, which have the largest resistance as the conductive filaments 11b are the thinnest; the OTP cell 1aa is in the state ‘3’, which has the smallest resistance as the conductive filament 11d is the thickest; the OTP cells 1ad, 1af are in the state ‘2, which have an intermediate resistance as the size of its conductive filament 11c is between those of 11b and 11d.

[0041] While illustrative embodiments have been shown and described, it would be apparent to those skilled in the art that many more modifications than that have been mentioned above are possible without departing from the inventive concepts set forth therein. The invention, therefore, is not to be limited except in the spirit of the appended claims.