METHOD FOR MANUFACTURING IMPLANTABLE ELECTRODES AND ELECTRODES MADE BY SUCH METHODS

Abstract

A method of manufacturing a plurality of neural probes from a silicon wafer in which after neural probes are formed on one side of a silicon wafer, the other side of the silicon wafter is subject to a dicing process that separates and adjusts the thickness of the neural probes.

Claims

1. A method for manufacturing neural probes from a silicon wafer which comprises: providing a silicon wafer having a top side and a back side; determining a desired shape of neural probes to be made from the silicon wafer, said desired shape including a backend and at least one shank extending outward from the backend; providing at least one microelectrode on the shank of the desired shape and an equal amount of bonding pads on the backend of the desired shape and interconnects between pairs of the at least one microelectrode and bonding pads, the bonding pads and interconnects being provided on a first electrical insulating layer provided on the top side of the silicon wafer and the microelectrodes being provided on the first electrical insulating layer or in or on a second electrical insulating layer that is provided on the first electrical insulating layer; etching through said first and second insulating layers and a top portion of the top side of the silicon wafer in a pattern that corresponds to the desired shape of the neural probe; and dicing the back side of the silicon wafer to form a neural probe having the desired shape with the shank having a predetermined thickness.

2. A method for manufacturing neural probes from a silicon wafer according to claim 1, wherein the neural probe comprises one shank.

3. A method for manufacturing neural probes from a silicon wafer according to claim 2, wherein the one shank extends outward from a middle area of the backend.

4. A method for manufacturing neural probes from a silicon wafer according to claim 2, wherein the one shank extends outward in line with a side of the backend.

5. A method for manufacturing neural probes from a silicon wafer according to claim 2, wherein the at least one shank comprises two or more shanks.

6. A method for manufacturing neural probes from a silicon wafer according to claim 1, wherein the backend has a uniform thickness.

7. A method for manufacturing neural probes from a silicon wafer according to claim 1, wherein the backend has a non-uniform thickness.

8. A method for manufacturing neural probes from a silicon wafer according to claim 1, wherein the dicing of the back side of the silicon wafer comprises using multiple dicing lanes.

9. A method for manufacturing neural probes from a silicon wafer according to claim 1, wherein the at least one shank has a thickness of from about 10 .Math.m to about 100 .Math.m.

10. In a method of manufacturing neural probes from a silicon wafer in which a plurality of neural probes having backends and shanks are pattered on one side of a silicon wafer, the improvement wherein the shanks of the individual patterned neural probes are thinned by a dicing an opposite side of the silicon wafer.

11. The method of manufacturing neural probes from a silicon wafer according to claim 10, wherein a desired thickness of the shanks is achieved by the dicing of the opposite side of the silicon wafer.

12. The method of manufacturing neural probes from a silicon wafer according to claim 10, wherein the neural probes have one shank.

13. The method of manufacturing neural probes from a silicon wafer according to claim 12, wherein the one shank extends outward from a middle area of each backend.

14. The method of manufacturing neural probes from a silicon wafer according to claim 12, wherein the one shank extends outward in line with a side of each backend.

15. The method of manufacturing neural probes from a silicon wafer according to claim 10, wherein the neural probes include two or more shanks.

16. The method of manufacturing neural probes from a silicon wafer according to claim 10, wherein the individual neural probes are separated by dicing the opposite side of the silicon wafer.

17. The method of manufacturing neural probes from a silicon wafer according to claim 10, wherein the backends have non-uniform thicknesses.

18. The method of manufacturing neural probes from a silicon wafer according to claim 10, wherein the dicing of the back side of the silicon wafer comprises using multiple dicing lanes.

19. The method of manufacturing neural probes from a silicon wafer according to claim 10, wherein the shanks have a thickness of from about 10 .Math.m to about 100 .Math.m.

20. The method of manufacturing neural probes from a silicon wafer according to claim 10, wherein the shanks have a length of from about 1 mm to about 20 mm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be described with reference to the attached drawings which are given as non-limiting examples only, in which:

[0018] FIG. 1 is a top view of a neural probe according to one embodiment of the present invention.

[0019] FIG. 2 is a cross-sectional view taken along section line A-A in FIG. 1 that illustrates an initial step in a neural probe manufacturing process according to the present invention.

[0020] FIG. 3 is a cross-sectional view taken along section line A-A in FIG. 1 that illustrates the second step in a neural probe manufacturing process according to the present invention.

[0021] FIG. 4 is a cross-sectional view taken along section line A-A in FIG. 1 that illustrates the third step in a neural probe manufacturing process according to the present invention.

[0022] FIG. 5 is a cross-sectional view taken along section line A-A in FIG. 1 that illustrates the fourth step in a neural probe manufacturing process according to the present invention.

[0023] FIGS. 6a and 6b are a cross-sectional view of the neural probe taken along section lines B-B and C-C in FIG. 1 respectively that show how the insulating layers shown in FIG. 5 are etched to define the shape of the final neural probe.

[0024] FIGS. 7a and 7b are a cross-sectional view of the neural probe taken along section lines B-B and C-C in FIG. 1 respectively that show how the etched out portion of the insulating layers is extended into the upper portion of the silicon base layer.

[0025] FIG. 8 is a top view that shows diced areas or dicing lanes that are used to form the final neural probes.

[0026] FIGS. 9a and 9b are a cross-sectional views of the neural probe taken along section lines B-B and C-C in FIG. 8 respectively that show how dicing areas or dicing lanes are aligned to form the final neural probes.

DETAILED DESCRIPTION OF THE DRAWINGS AND THE PRESENTLY PREFERRED EMBODIMENTS

[0027] The neural probes of the present invention are manufactured from silicon wafers and include backends and one of more shanks that extend from a lower side edge of the backends. The shank(s) can extend outward from the lower edge of the backends near the sides of the backends or from any position between the sides of the backends.

[0028] The shanks are provided with one or more spaced apart microelectrodes and the backends are provided with a similar number of bonding pads. Electrically conductive interconnects connect between the microelectrodes and the bonding pads. The interconnects and bonding pads are made from a conductive material, which may include one or more metals including but not limited to gold, iridium, or platinum. During use output leads and be connected to the bonding pads for processing signals detected by the microelectrodes and/or sending stimulating current to the microelectrodes.

[0029] The lengths of the shanks can from about 5 mm to about 10 mm or longer. The widths of the shanks can be from about 30 .Math.m to about 300 .Math.m. The thickness of the shanks can be from about 30 .Math.m to about 50 .Math.m. The number of microelectrodes can range from up to 512 or more. The backends can have a generally rectangular shape or any desired shape and can have uniform or nonuniform thickness with a minimum thickness being the same as the thinnest shank which extends outward therefrom.

[0030] FIG. 1 is a top view of a neural probe according to one embodiment of the present invention.

[0031] The neural probe 1 shown in FIG. 1 includes a backend 2 with a shank 3 extending outward from the middle of the backend 2. A plurality of spaced apart microelectrodes 4 are provided on the shank 3. The backend 2 includes plurality of bonding pads 5 to which output leads can be connected for processing signals detected by the microelectrodes and/or sending stimulation current to the microelectrodes. Electrically conductive interconnects 6 connect between the microelectrodes 4 and the bonding pads 5.

[0032] The backend 2 in FIG. 1 has a generally rectangular shape with the shank 3 extending outward form the middle. In other embodiments of the neural probes, one or more shanks can be provided which extend outward from any from any location from the lower portion of the backend 2. In addition, the backend 2 can have any desired shape other that the rectangular shape shown.

[0033] The distal end of the shank 3 in FIG. 1 has a pointed shape. In other embodiments the distal end of the shank 3 can be flat or have an angular shape.

[0034] While the neural probe 1 in FIG. 1 has four microelectrodes 4 and four bonding pads 5, the number of microelectrodes 4 and bonding pads 5 that can be used is only limited to how small the microelectrodes 4 and bonding pads 5 can be made and the surface area of the shank 3. The number of microelectrodes 4 and bonding pads 5 can range up to about 512 or more.

[0035] FIG. 2 is a cross-sectional view taken along section line A-A in FIG. 1 that illustrates an initial step in a neural probe manufacturing process according to the present invention.

[0036] The neural probes of the present invention are manufactured from a silicon wafer in a manner that manufactures many neural probes at a time - up to as many that can be made from a standard silicon wafer that can have a diameter of 450 mm or 300 mm or less and have a thickness of from about 775 .Math.m to about 925 .Math.m. Accordingly, in FIG. 2 the silicon base layer 7 is small portion of a silicon wafer.

[0037] In the initial manufacturing step, an electrical insulating layer 8 is formed on the top surface of the silicon base layer 7. The insulating layer 8 can be made from silicon dioxide (SiO.sub.2) that can be formed by thermal oxidation or by chemical vapor deposition (CVD). The insulating layer 8 generally has a thickness of from about 0.1 .Math.m to about 2 .Math.m or more.

[0038] FIG. 3 is a cross-sectional view taken along section line A-A in FIG. 1 that illustrates the second step in a neural probe manufacturing process according to the present invention.

[0039] In FIG. 3 the bonding pads 5 and portions of the interconnects 6 that will connect and/or underlie the microelectrodes 4 are formed on the insolating layer 8 by a metal sputtering process using a mask. As noted above, the bonding pads 5 and interconnects 6 can be made from a conductive material, which may include one or more metals including but not limited to gold, iridium, or platinum.

[0040] FIG. 4 is a cross-sectional view taken along section line A-A in FIG. 1 that illustrates the third step in a neural probe manufacturing process according to the present invention.

[0041] In FIG. 4 a second patterned electrical insulating layer 9 is formed over the interconnects 6 which is formed with openings 10 above the bonding pads 5 and openings 11 above the ends of the portions of the interconnects 6 that will connect and/or underlie the microelectrodes 4. This second insulating layer 9 can be formed by from silicon dioxide (SiO.sub.2) and applied by a chemical vapor deposition (CVD) process using a mask.

[0042] FIG. 5 is a cross-sectional view taken along section line A-A in FIG. 1 that illustrates the fourth step in a neural probe manufacturing process according to the present invention.

[0043] In FIG. 5 microelectrodes 4 are formed which extend through the openings 11 to the ends of the interconnects 6. As shown, the microelectrodes 4 can also extend over the surface of the second insulating layer 9 at the periphery of the openings 11 if desired. The microelectrodes 4 can be formed using a chemical vapor deposition (CVD) process and can be formed from one or more metals including but not limited to gold, iridium, or platinum. In an alternative embodiments, the microelectrodes 4 could be formed on the first insulating layer 8, in electrical contact with the interconnects 6 and provided at the bottoms of openings 11, or in openings 11 with or without extending above the top surface of the second insulating layer.

[0044] FIGS. 6a and 6b are a cross-sectional view of the neural probe taken along section lines B-B and C-C in FIG. 1 respectively that show how the insulating layers 8 and 9 shown in FIG. 5 are etched to define the shape of the final neural probe 1. In FIGS. 6a, 6b, 7a and 7b the microelectrodes 4, bonding pads 5 and interconnects 6 omitted so as to simplify the description of the process steps.

[0045] As shown in FIGS. 6a and 6b, insulating layers 8 and 9 are etched down to the silicon base layer 7. The etching of insulating layers 8 and 9 can be performed using a mask and a buffered Oxide Etch (BOE) etch solution or just hydrofluoric acid. The etched areas 12 shown in FIG. 6a will define the peripheral side edges of the backend 2 of the final neural probe 1 as will be understood as the description of the present invention proceeds. The etched areas 13 shown in FIG. 6b will define the peripheral side edges of the shank 3 of the final neural probe 1 as will be understood as the description of the present invention proceeds.

[0046] While not shown, it is understood that the upper and lower peripheral edges of the backend of the final neural probe will be formed by etching the insulating layers 8 and 9 in a similar manner.

[0047] FIGS. 7a and 7b are a cross-sectional view of the neural probe taken along section lines B-B and C-C in FIG. 1 respectively that show how the etched out portion of the insulating layers 8 and 9 is extended into the upper portion of the silicon base layer 7 by an etching process using potassium hydroxide and a mask. The upper portion of the silicon base layer 7 can be etched to a depth of about 80 .Math.m or greater. The etched areas 14 shown in FIG. 7a will define the peripheral side edges of the backend 2 of the final neural probe 1 as will be understood as the description of the present invention proceeds. The etched areas 15 shown in FIG. 7b will define the peripheral side edges of the shank 3 of the final neural probe 1 as will be understood as the description of the present invention proceeds.

[0048] While not shown, it is understood that the upper and lower peripheral edges of the backend of the final neural probe will be formed by etching the top portion of the silicon water 7 in a similar manner.

[0049] FIG. 8 is a top view that shows diced areas or dicing lanes that are used to form the final neural probes.

[0050] FIGS. 9a and 9b are a cross-sectional views of the neural probe taken along section lines B-B and C-C in FIG. 8 respectively that show how dicing areas or dicing lanes are aligned to form the final neural probes.

[0051] After the etching processes discussed above in reference to FIGS. 6a, 6b, 7a and 7a are finished, dicing tape is applied to the top surface of the silicon wafer from which a plurality of the neural probes are manufactured and used to mount the silicon water to a dicing table so that the silicon base layer 7 is on top.

[0052] As show in FIGS. 8 and 9a, the back side of the silicon wafer is diced along peripheral dicing lanes 16 that intersect the etched areas 14 shown in FIG. 7a. Likewise, as shown in FIGS. 8 and 9b, the back side of the silicon wafer is diced along a center dicing lane 17 that intersects the etched areas 15 shown in FIG. 7b.

[0053] As also shown in FIG. 8, dicing lanes 18 and 19 are formed along the upper and lower peripheral edges of the backend 2 which intersect similarly located etch areas of the silicon wafer.

[0054] The final thickness of the shank 3 of the neural probe 1 is determined by the dicing step when the silicon wafer is diced along dicing lane 17. The kerf of the dicing blade used in the dicing step is selected to correspond to a desired shank width (with etched areas 13 in the insulating layers 8 and 9, and etched areas 15 in the upper portion of the silicon base layer 7 being appropriately spaced apart and aligned). Dicing can be performed with dicing blades having different kerfs

[0055] After the dicing shown in FIGS. 8, 9a and 9b is complete, dicing tape is applied to the back side of the silicon wafer and the dicing tape is removed from the front side of the silicon wafer so that the individually manufactured neural probes can be picked up for assembly.

[0056] As shown in FIGS. 8 and 9a, the thickness of the backend of the final neural probes is not uniform due to the locations of the dicing lanes 16 and 17, and the space between the dicing lanes 16 and 17. If desired, additional dicing lanes could be used to make the thickness of the backend uniform.

[0057] The manufacturing steps described herein with reference to FIG. 2 -9b can be varied and adapted to manufacture neural probes that have different shapes that the neural probe shown in FIG. 1.

[0058] For embodiments in which the location and the number of shanks is different, the pattern for etching of the insulating layers and dicing of the back of the backside of the silicon wafer can be adjusted to achieve the final shape of the desired neural probes. The same or different shaped neural probes can be patterned and formed from a single silicon wafer, including neural probes having shanks located at different positions from the backsides, different numbers of shanks, shanks having different lengths and/or widths and/or thicknesses and neural probes having different numbers of microelectrodes and bonding pads.

[0059] The processes for forming the insulating layers and etching the insulating layers and the top portion of the silicon base layer can include those processes noted above as well as any conventional known processes known and used in the art of semiconductor manufacturing or MEMS.

[0060] Although the present invention has been described with reference to particular means, materials and embodiments, from the foregoing description, one skilled in the art can easily ascertain the essential characteristics of the present invention and various changes and modifications can be made to adapt the various uses and characteristics without departing from the spirit and scope of the present invention as described above and set forth in the attached claims.