Method and apparatus for determining a target light intensity from a phase-control signal

Abstract

A dimmable ballast circuit for a compact fluorescent lamp controls the intensity of a lamp tube in response to a phase-control voltage received from a dimmer switch. The ballast circuit comprises a phase-control-to-DC converter circuit that receives the phase-control voltage, which is characterized by a duty cycle defining a target intensity of the lamp tube, and generates a DC voltage representative of the duty cycle of the phase-control voltage. Changes in the duty cycle of the phase-control voltage that are below a threshold amount are filtered out by the converter circuit, while intentional changes in the duty cycle of the phase-control voltage are reflected in changes in the target intensity level and thereby the intensity level of the lamp tube.

Claims

1. A circuit for controlling an intensity level of a lighting load, the circuit configured to receive a phase-control voltage characterized by a duty cycle, the circuit comprising: a load regulation circuit adapted to be coupled to the lighting load for control of the intensity level of the lighting load; and a control circuit configured to determine a target intensity level for the lighting load in response to the duty cycle of the phase-control voltage, the control circuit configured to receive an actual-intensity signal representative of an actual intensity level of the lighting load, the control circuit configured to control the load regulation circuit to adjust the actual intensity level of the lighting load towards the target intensity level; wherein the control circuit is configured to adjust the target intensity level for the lighting load using a first time constant in response to changes in the duty cycle of the phase-control voltage that are less than a threshold amount, and to adjust the target intensity level of the lighting load using a second time constant less than the first time constant in response to changes in the duty cycle of the phase-control voltage that are greater than the threshold amount.

2. The circuit of claim 1, wherein the control circuit is configured to convert the phase-control voltage into a target signal that is representative of the target intensity level of the lighting load, the control circuit configured to compare a magnitude of the target signal and a magnitude of the actual-intensity signal to produce a drive control signal, the load regulation circuit configured to receive the drive control signal and to adjust the actual intensity level of the lighting load towards the target intensity level in response to the drive control signal.

3. The circuit of claim 2, wherein changes in the duty cycle of the phase-control voltage cause a magnitude of a filtered voltage of the control circuit to change by an amount in excess of a threshold voltage thereby to be reflected in the magnitude of the target signal generated by the control circuit.

4. The circuit of claim 3, further comprising: a rectifier circuit configured to convert the phase-control voltage into a rectified phase-control voltage, the control circuit configured to receive the rectified phase-control voltage.

5. The circuit of claim 4, wherein the control circuit comprises a phase-control-voltage converter circuit that includes: a first circuit configured to convert the rectified phase-control voltage into a phase-control signal having a duty cycle related to the duty cycle of the phase-control voltage; a second circuit configured to convert the phase-control signal to a ramp signal; and a third circuit configured to filter the ramp signal to generate a DC-level signal.

6. The circuit of claim 5, wherein the third circuit comprises a first filter circuit characterized by a third time constant and a second filter circuit electrically coupled in series with the first filter circuit, the second filter circuit characterized by a fourth time constant.

7. The circuit of claim 6, wherein the first filter circuit is configured to filter the ramp signal to generate a filtered ramp signal and the fourth time constant of the second filter circuit is voltage dependent, whereby the fourth time constant is approximately equal to the first time constant if a change in a magnitude of the filtered ramp signal is less than the threshold voltage and is approximately equal to the second time constant if a change in the magnitude of the filtered ramp signal is greater than the threshold voltage.

8. The circuit of claim 7, wherein the first and second filter circuits each comprise resistor-capacitor circuits.

9. The circuit of claim 8, wherein each of the first and second filter circuits has a capacitor connected to a common terminal and a resistor of the second filter circuit is coupled between the capacitors of the filter circuits, the second filter circuit further comprising two anti-parallel-connected diodes coupled across the resistor of the second filter circuit, whereby the capacitor of the second filter circuit charges or discharges through the resistor between the capacitors when a change in the magnitude of the filtered ramp signal is below the threshold voltage, and charges or discharges through one of the diodes when a change in the magnitude of the filtered ramp signal is greater than the threshold voltage.

10. The circuit of claim 9, wherein the threshold voltage is equal to approximately a forward voltage of one of the diodes, the capacitor of the second filter circuit configured to stop charging or discharging through the one of the diodes when a difference between voltages across the capacitors of the first and second filter circuits drops below a forward voltage of one of the diodes.

11. The circuit of claim 5, wherein the second filter circuit is configured to have the first time constant when the filtered ramp signal increases or decreases by an amount less than the threshold voltage, and to have the second time constant when the filtered ramp signal increases or decreases by an amount greater than the threshold voltage.

12. The circuit of claim 3, wherein the circuit receives the phase-control voltage from a dimmer switch that is powered from an AC voltage supply, and the magnitude of the filtered voltage changes by greater amounts for changes in the duty cycle of the phase-control voltage than for voltage fluctuations and noise of the AC voltage supply.

13. The circuit of claim 1, further comprising: a bus-voltage-generating circuit receiving the phase-control voltage and producing a DC bus voltage; wherein the load regulation circuit is configured to receive the DC bus voltage.

14. The circuit of claim 1, wherein the control circuit comprises a microprocessor.

15. The circuit of claim 1, wherein the lighting load comprises a fluorescent lamp and the load regulation circuit comprises a dimmable ballast circuit.

16. The circuit of claim 1, wherein the lighting load comprises a LED light source and the load regulation circuit comprises an LED driver circuit.

17. A control circuit for a load control circuit for a lighting load, the control circuit configured to receive a phase-control voltage characterized by a duty cycle, the control circuit comprising: a phase-control-voltage converter circuit configured to compare the phase-control voltage to a target signal for determining a target intensity level for the lighting load; and an error amplifier circuit configured to compare a magnitude of the target signal and a magnitude of an actual-intensity signal representative of the actual intensity level of the lighting load, the error amplifier circuit further configured to generate a drive control signal for controlling the actual intensity level of the lighting load towards the target intensity level; wherein the phase-control-voltage converter circuit is configured to adjust the target intensity level for the lighting load using a first time constant in response to changes in the duty cycle of the phase-control voltage that are less than a threshold amount, and to adjust the target intensity level of the lighting load using a second time constant less than the first time constant in response to changes in the duty cycle of the phase-control voltage that are greater than the threshold amount.

18. A method of controlling a lighting load comprising: receiving a phase-control voltage, the phase-control voltage characterized by a duty cycle; determine a target intensity level for the lighting load in response to the duty cycle of the phase-control voltage; receiving an actual-intensity signal representative of an actual intensity level of the lighting load; controlling the actual intensity level of the lighting load towards the target intensity level; adjusting the target intensity level of the lighting load using a first time constant in response to changes in the duty cycle of the phase-control voltage that are less than a threshold amount; and adjusting the target intensity level of the lighting load using a second time constant less than the first time constant in response to changes in the duty cycle of the phase-control voltage that are greater than the threshold amount.

19. The method of claim 18, further comprising: converting the phase-control voltage into a target signal that is representative of the target intensity level of the lighting load; comparing a magnitude of the target signal and a magnitude of the actual-intensity signal to produce the drive control signal; adjusting the actual intensity level of the lighting load towards the target intensity level in response to a drive control signal.

20. The method of claim 19, further comprising: filtering out changes in the duty cycle of the phase-control voltage that are below the threshold amount.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will now be described in greater detail in the following detailed description with reference to the drawings in which:

(2) FIG. 1 is a simplified block diagram of a prior art lighting control system including a “two-wire” dimmer switch for controlling the amount of power delivered to a screw-in compact fluorescent lamp;

(3) FIG. 2 is a simplified block diagram of the screw-in compact fluorescent lamp of the lighting control system of FIG. 1;

(4) FIG. 3A shows an example waveform of a bus voltage of the screw-in compact fluorescent lamp of FIG. 2;

(5) FIG. 3B shows an example waveform of a lamp current of the screw-in compact fluorescent lamp of FIG. 2;

(6) FIG. 4 is a side view of a dimmable screw-in compact fluorescent lamp according to a first embodiment of the present invention;

(7) FIG. 5 is a simplified schematic diagram of the screw-in compact fluorescent lamp of FIG. 4;

(8) FIG. 6 is a simplified schematic diagram of the electrical circuitry of the screw-in compact fluorescent lamp of FIG. 4 showing a load regulation circuit and two power supplies in greater detail;

(9) FIG. 7 is a simplified schematic diagram of an inverter circuit of the load regulation circuit and an over-voltage protection circuit of the screw-in compact fluorescent lamp of FIG. 4;

(10) FIG. 8 is a simplified schematic diagram of a control circuit of the screw-in compact fluorescent lamp of FIG. 4;

(11) FIG. 9 is an example plot of the magnitude of a lamp voltage with respect to the magnitude of a lamp current of the screw-in compact fluorescent lamp of FIG. 4;

(12) FIG. 10A shows an example waveform of a bus voltage of the screw-in compact fluorescent lamp of FIG. 4;

(13) FIG. 10B shows an example waveform of a lamp current of the screw-in compact fluorescent lamp of FIG. 4 according to the first embodiment of the present invention;

(14) FIG. 11 is a simplified schematic diagram of a control circuit of the dimmable screw-in compact fluorescent lamp according to a second embodiment of the present invention; and

(15) FIG. 12 is a simplified flowchart of a control procedure executed periodically by a microprocessor of the control circuit of FIG. 11.

DETAILED DESCRIPTION OF THE INVENTION

(16) The foregoing summary, as well as the following detailed description of the preferred embodiments, is better understood when read in conjunction with the appended drawings. For the purposes of illustrating the invention, there is shown in the drawings an embodiment that is presently preferred, in which like numerals represent similar parts throughout the several views of the drawings, it being understood, however, that the invention is not limited to the specific methods and instrumentalities disclosed.

(17) FIG. 4 is a side view of a dimmable screw-in compact fluorescent lamp 120 according to a first embodiment of the present invention. The dimmable screw-in compact fluorescent lamp 120 comprises a light source, e.g., a fluorescent lamp tube 122, which may be formed in a spiral (as shown in FIG. 4), in two or more U-bends, or in any other suitable form. The lamp tube 122 may be filled with a fill-gas mixture having a fall-gas pressure of approximately 2 Torr and a fill-gas ratio of approximately 85:15 argon to neon. The dimmable screw-in compact fluorescent lamp 120 further comprises an enclosure 24 for housing a load regulation circuit 130 (FIG. 5), e.g., an electronic ballast circuit, which is electrically coupled to the lamp tube 122 for illuminating the lamp tube.

(18) The screw-in compact fluorescent lamp 120 has a screw-in base 126 adapted to be coupled to a standard Edison socket, such that the lamp is adapted to be coupled to a two-wire dimmer switch (such as the dimmer switch 30) via the phase-control connection PC of the screw-in base 126 and to the neutral side N of an AC power source via the neutral connection NC (as in the prior art lighting control system 100 shown in FIG. 1). As defined herein, a “two-wire” dimmer switch or load control device does not require a direct connection to the neutral side N of the AC power source. In other words, all currents conducted by the two-wire dimmer switch must also be conducted through the load. A two-wire dimmer switch may have only two terminals (i.e., the hot terminal H and the dimmed hot terminal DH as shown in FIG. 1). Alternatively, a two-wire dimmer switch could comprise a three-way dimmer switch that may be used in a three-way lighting system and has at least three load terminals, but does not require a neutral connection. In addition, a two-wire dimmer switch may comprise an additional connection that provides for communication with a remote control device (for remotely controlling the dimmer switch), but does not require the dimmer switch to be directly connected to neutral.

(19) FIG. 5 is a simplified schematic diagram of a dimmable screw-in compact fluorescent lamp 120 according to the first embodiment of the present invention. As previously mentioned, the screw-in base 126 provides for only two electrical connections: the phase-control connection PC to the dimmer switch for receiving the phase-control voltage V.sub.PC and the neutral connection NC to the neutral side N of the AC power source. The load regulation circuit 130 of the screw-in compact fluorescent lamp 120 is operable to adjust the intensity of the lamp tube 122 to a target intensity L.sub.TRGT (i.e., a desired intensity) in response to the duty-cycle DC.sub.PC of the phase-control signal V.sub.PC. The target intensity L.sub.TRGT may range between a low-end intensity L.sub.LE (e.g., approximately 1%) and a high-end intensity L.sub.HE (e.g., approximately 100%).

(20) The screw-in compact fluorescent lamp 120 comprises a filter network 200 coupled to the phase-control connection PC and the neutral connection NC of the connector 126 for receiving the phase-control voltage V.sub.PC from the dimmer switch 30. The filter network 200 comprises an inductor L201 (e.g., having an inductance of approximately 680 μH) and two capacitors C202, C203 (e.g., having capacitances of approximately 33 nF). The filter network 200 operates to prevent noise generated by the load regulation circuit 130 from being conducted on the AC mains wiring. The filter network 200 couples the phase-control voltage V.sub.PC to a voltage doubler circuit 205 (i.e., a bus-voltage-generating circuit), which generates a direct-current (DC) bus voltage V.sub.BUS across two series connected bus capacitors C.sub.B1, C.sub.B2. The first bus capacitor C.sub.B1 conducts the load current I.sub.LOAD through a diode D206 (and the dimmer switch 30) to charge during the positive half-cycles, while the second bus capacitor C.sub.B2 conducts the load current I.sub.LOAD through a diode D208 to charge during the negative half-cycles. Accordingly, the peak magnitude of the bus voltage V.sub.BUS is approximately twice the peak voltage of the AC mains line voltage V.sub.AC. A half-bus voltage V.sub.HB is generated across the first bus capacitor C.sub.B1 and has a magnitude equal to approximately half of the bus voltage V.sub.BUS.

(21) The load regulation circuit 130 (i.e., the electronic ballast circuit) includes a half-bridge inverter circuit 210 for converting the DC bus voltage V.sub.BUS to a high-frequency square-wave voltage V.sub.SQ having an operating frequency f.sub.OP. The load regulation circuit 130 further comprises an output filter circuit, e.g., a resonant tank circuit 220, for filtering the square-wave voltage V.sub.SQ to produce a substantially sinusoidal high-frequency AC voltage, which is coupled to the electrodes of the lamp tube 122. A control circuit 230 is coupled to the inverter circuit 210 for providing a drive control signal V.sub.DR to the inverter circuit 210 for adjusting the operating frequency f.sub.OP of the square wave voltage V.sub.SQ and thus the magnitude of a lamp current I.sub.LAMP conducted through the lamp tube 122 in order to turn the lamp tube on and off and adjust the intensity of the lamp tube. Alternatively, the screw-in compact fluorescent lamp 120 could comprise a different high-efficiency lighting load, such as, a dimmable screw-in LED light source having an LED light engine, and the load regulation circuit 130 could comprise an LED driver. An example of the LED driver 102 is described in greater detail in commonly-assigned, co-pending U.S. patent application Ser. No. 12/813,908, filed Jun. 11, 2009, and U.S. patent application Ser. No. 13/416,741, filed Mar. 9, 2012, both entitled LOAD CONTROL DEVICE FOR A LIGHT-EMITTING DIODE LIGHT SOURCE, the entire disclosures of which are hereby incorporated by reference.

(22) The screw-in compact fluorescent lamp 120 further comprises two power supplies: an inverter power supply 240 and a control power supply 250. The inverter power supply 240 receives the half-bus voltage V.sub.HB across the first bus capacitor C.sub.B1 and generates a direct-current (DC) inverter supply voltage V.sub.INV (e.g., approximately 15 volts) for powering the control circuitry of the inverter circuit 210. The control power supply 250 draws current from the resonant tank circuit 220 and generates a DC control supply voltage V.sub.CC (e.g., approximately 12 volts) for powering the control circuit 230 while the inverter circuit 210 is generating the high-frequency square-wave voltage V.sub.SQ. When the screw-in compact fluorescent lamp 120 is first powered up, the inverter power supply 240 is operable to generate the inverter supply voltage V.sub.INV before the control power supply 250 begins to produce the control supply voltage V.sub.CC. After the inverter power supply 240 is generating the inverter supply voltage V.sub.INV, the inverter circuit 210 is able to begin generating the high-frequency square-wave voltage V.sub.SQ, such that the control power supply 250 is able to draw current from the resonant tank circuit 220. Accordingly, the control power supply 250 then produces the control supply voltage V.sub.CC to power the control circuit 230.

(23) The screw-in compact fluorescent lamp 120 further comprises an over-voltage protection (OVP) circuit 260, which provides an OVP control signal V.sub.OVP to the inverter circuit 210 for protecting the lamp tube 122 and the load regulation circuit 130 during over-voltage conditions. A lamp current sense circuit 270 is coupled in series with the lamp tube 122 to conduct the lamp current I.sub.LAMP and to generate a lamp current control signal V.sub.ILAMP representative of a magnitude of the lamp current I.sub.LAMP. The screw-in compact fluorescent lamp 120 further comprises a rectifier circuit 280 (e.g., a full-wave rectifier diode bridge as shown in FIG. 5), which has AC terminals coupled to receive the phase-control voltage V.sub.PC from the filter network 200 and DC terminals for providing a rectified voltage V.sub.RECT.

(24) The rectified voltage V.sub.RECT is received by an artificial load circuit 290 for conducting an artificial load current I.sub.ART through the dimmer switch 30 in addition to the load current I.sub.LOAD conducted by the bus capacitors C.sub.B1, C.sub.B2 when the bus capacitors are charging. If the dimmer switch 30 includes a triac for generating the phase-control voltage V.sub.PC, the artificial load circuit 290 is able to conduct enough current to ensure that the magnitude of the total current conducted through the triac of the dimmer switch exceeds the rated latching and holding currents of the triac. In addition, the artificial load circuit 290 may conduct a timing current if the dimmer switch 30 comprises a timing circuit and may conduct a charging current if the dimmer switch comprises a power supply, such that these currents need not be conducted through the load regulation circuit 130 and do not affect the intensity of the lamp tube 122.

(25) The artificial load circuit 290 comprises a current-passing switch, e.g., a FET Q282, coupled in series with a resistor R284 (e.g., having a resistance of approximately 12.4Ω), where the series combination of the drain-source junction of the FET Q282 and the resistor R284 is coupled across the DC terminals of the rectifier circuit 280. The gate of the FET Q282 is coupled to the drain of the FET Q282 through a resistor R285 (e.g., having a resistance of approximately 1 Me), such that the FET Q282 is rendered conductive and conducts the artificial load current I.sub.ART when the magnitude of the rectified voltage V.sub.RECT increases from approximately zero volts to exceed a turn-on threshold (e.g., approximately 4 volts). Accordingly, the FET Q282 is rendered conductive, such that the artificial load circuit 290 conducts the artificial load current I.sub.ART through the dimmer switch 30 after the triac is rendered conductive (if the dimmer switch is using the forward phase-control dimming technique), or shortly after the beginning of each half-cycle (if the dimmer switch is using the reverse phase-control dimming technique). The artificial load circuit 290 further comprises an NPN bipolar junction transistor Q286 having a base-emitter junction coupled across the resistor R284 and a collector coupled to the gate of the FET Q282. The transistor Q286 controls the FET Q282 in the linear region to provide over-current protection of the FET Q282 when the voltage across the resistor R284 exceeds the rated base-emitter voltage of the transistor Q286 (e.g., approximately 0.7 volt).

(26) The artificial load circuit 290 also comprises an NPN bipolar junction transistor Q288 having a collector coupled to the gate of the FET Q282, and a zener diode Z292, having, for example, break-over voltage V.sub.BR of approximately 13.2 volts. Three resistors R294, R295, R296 are coupled in series between the DC terminals of the rectifier circuit 180 and have, for example, resistances of approximately 22 kΩm 470 kΩ, and 150 kΩ, respectively. The zener diode Z292 is coupled between the base of the transistor Q288 and the junction of the resistors R295, R296. A capacitor C298 is coupled across the resistor R296 and has, for example, a capacitance of approximately 1000 pF. When the magnitude of the rectified voltage V.sub.RECT exceeds a turn-off threshold (e.g., approximately 60 volts), the zener diode Z292 conducts current into the base of the transistor Q288. Accordingly, the transistor Q288 is rendered conductive and the FET Q282 is rendered non-conductive, such that the artificial load circuit 290 stops conducting the artificial load current I.sub.ART. If the dimmer switch 30 is using the forward phase-control dimming technique, the capacitor C298 provides some delay, such that the artificial load circuit 290 conducts the artificial load current I.sub.ART for a period of time after the triac is rendered conductive.

(27) The artificial load circuit 290 also provides a phase-control input control signal V.sub.PC-IN to the control circuit 230. Specifically, the artificial load circuit 290 comprises a PNP bipolar junction transistor Q299 having a collector coupled to the control circuit 230 for providing the phase-control input control signal V.sub.PC-IN. The emitter-base junction of the transistor Q299 is coupled across the resistor R294, such that the transistor Q299 is rendered conductive shortly after the triac is rendered conductive (with forward phase-control dimming) or shortly after the beginning of each half-cycle (with reverse phase-control dimming). The control circuit 230 uses the phase-control input control signal V.sub.PC-IN to determine the duty-cycle DC.sub.PC of the phase-control voltage V.sub.PC (i.e., the conduction time T.sub.CON of the bidirectional semiconductor switch 32 of the dimmer switch 30). The control circuit 230 determines the present magnitude of the lamp current I.sub.LAMP from the lamp current control signal V.sub.ILAMP received from the lamp current sense circuit 270. The control circuit 230 then adjusts the operating frequency f.sub.OP of the square wave voltage V.sub.SQ to control the magnitude of the lamp current I.sub.LAMP to a desired level that is dependent upon the duty-cycle DC.sub.PC of the phase-control voltage V.sub.PC to thus control the intensity of the lamp tube 122 to the target intensity L.sub.TRGT.

(28) FIG. 6 is a simplified schematic diagram of the electrical circuitry of the screw-in compact fluorescent lamp 120 showing the inverter circuit 210, the resonant tank circuit 220, the inverter power supply 240, the control power supply 250, and lamp current sense circuit 270 in greater detail. The inverter circuit 210 comprises first and second series-connected switching devices (e.g., FETs Q212, Q214) and an inverter control circuit 216, which may comprise, for example, an inverter control integrated circuit (IC) U300 (FIG. 5), such as part number FAN7532, manufactured by Fairchild Semiconductor Incorporated. The inverter control IC U300 of the inverter control circuit 216 is powered by the inverter supply voltage V.sub.INV and controls the FETs Q212, Q214 in response to the drive control signal V.sub.DR received from the control circuit 230 as will be described in greater detail below with reference to FIG. 7. The inverter control circuit 216 renders the FETs Q212, Q214 conductive and non-conductive on a complementary basis (such that only one of the FETs is conducting at a time) using a constant duty cycle (e.g., approximately 50%). When the first FET Q212 is conductive, the output of the inverter circuit 210 is pulled up towards the bus voltage V.sub.BUS. When the second FET Q214 is conductive, the output of the inverter circuit 210 is pulled down towards circuit common. The magnitude of the lamp current I.sub.LAMP conducted through the lamp tube 122 is controlled by adjusting the operating frequency f.sub.OP of the high-frequency square wave voltage V.sub.SQ generated by the inverter circuit 210.

(29) The resonant tank circuit 220 comprises a resonant inductor L222 adapted to be coupled in series between the inverter circuit 210 and the lamp tube 122, and a resonant capacitor C224 adapted to be coupled in parallel with the lamp tube. For example, the inductor L222 may have an inductance of approximately 1.4 mH, while the resonant capacitor C224 may have a capacitance of approximately 1.2 nF, such that resonant tank circuit is characterized by a resonant frequency of approximately 110 kHz. The resonant tank circuit 220 further comprises a DC-blocking capacitor C226 that has a capacitance of, for example, approximately 2.7 nF and operates to minimize the DC component of the lamp current I.sub.LAMP conducted through the lamp tube 122.

(30) When the lamp tube 122 is not illuminated and the control circuit 230 receives a command to turn the lamp tube on (from the phase-control voltage V.sub.PC), the control circuit first preheats filaments 228A, 228B of the lamp tube 122 and then attempts to strike the lamp tube. The load regulation circuit 130 may comprise, for example, two filament windings 229A, 229B that are magnetically coupled to the resonant inductor L222 and electrically coupled to the respective filaments 228A, 228B for generating filament voltages for heating the filaments of the lamp tube 122 prior to striking the lamp. To preheat the filaments 228A, 228B, the inverter circuit 210 controls the operating frequency f.sub.OP of the square wave voltage V.sub.SQ to a preheat frequency f.sub.PH (e.g., approximately 150 kHz) for a preheat time period T.sub.PH (e.g., approximately 700 msec). An example of a ballast having a circuit for heating the filaments of a fluorescent lamp is described in greater detail in U.S. Pat. No. 7,586,268, issued Sep. 8, 2009, titled APPARATUS AND METHOD FOR CONTROLLING THE FILAMENT VOLTAGE IN AN ELECTRONIC DIMMING BALLAST, the entire disclosure of which is hereby incorporated by reference.

(31) The inverter power supply 240 receives the half-bus voltage V.sub.HB developed across the first bus capacitor C.sub.B1 and generates the inverter supply voltage V.sub.INV across a storage capacitor C242 (e.g., having a capacitance of approximately 1 μF). The inverter power supply 240 comprises a simple zener-regulated power supply having a zener diode Z243, which is coupled across the storage capacitor C242 and may have, for example, a break-over voltage of approximately 13.2 volts. When the screw-in compact fluorescent lamp 120 is first powered up, the storage capacitor C242 is able to charge by conducting a small trickle current from the AC power source 15 through a resistor R244 (e.g., having a resistance of approximately 392 kΩ) until the inverter supply voltage V.sub.INV is developed across the storage capacitor C242. After the magnitude of the inverter supply voltage V.sub.INV exceeds the rated operating voltage of the inverter control IC U300 of the inverter control circuit 216, the inverter control IC begins to control the FETs Q212, Q214 to be conductive and non-conductive to generate the square wave voltage V.sub.SQ.

(32) The inverter power supply 240 further comprises a snubber capacitor C245 that has, for example, a capacitance of approximately 470 pF and provides a path for charging the storage capacitor C242 after the inverter control circuit 216 begins generating the square wave voltage V.sub.SQ. The snubber capacitor C245 is coupled between junction of the two FETs Q212, Q214 and the storage capacitor C242 through a diode D246 and a resistor R246 (e.g., having a resistance of approximately 5.6Ω). The storage capacitor C242 is able to charge when the first FET Q212 is conductive (i.e., when the square-wave voltage V.sub.SQ is being pulled high towards the bus voltage V.sub.BUS). When the second FET Q214 is conductive and the square-wave voltage V.sub.SQ is being pulled low towards circuit common, the snubber capacitor C245 is able to discharge through the second FET Q214 and a diode D248. Accordingly, after the inverter control circuit 216 begins generating the square wave voltage V.sub.SQ, the inverter power supply 240 is operable to generate the inverter supply voltage V.sub.INV by conducting current through the snubber capacitor C245 rather than conducting current through the resistor R244, which would needlessly dissipate an excessive amount of power.

(33) The control power supply 250 comprises a linear regulator, for example, an adjustable linear regulator U252, such as part number LM317L, manufactured by Fairchild Semiconductor Incorporated. The control power supply 250 comprises a winding 254 magnetically coupled to the resonant inductor L222 of the resonant tank circuit 220 for generating an electromagnetically-coupled voltage, such that the linear regulator U252 is able to draw current from the resonant tank circuit through a diode D255 when the inverter control circuit 216 is generating the square-wave voltage V.sub.SQ. A capacitor C256 is coupled across the input of the linear regulator U252 and has, for example, a capacitance of approximately 0.1 μF. A first resistor R258 is coupled between the output of the adjustable linear regulator U252 and the adjustment pin of the linear regulator, while a second resistor R259 is coupled between the adjustment pin and circuit common. For example, the first and second resistors R258, R259 may have resistances of approximately 475Ω and 5.23 kΩ, respectively, such that the control supply voltage V.sub.CC at the output of the linear regulator U252 has a nominal magnitude of approximately 15 volts.

(34) FIG. 7 is a simplified schematic diagram of the inverter circuit 210 and the OVP circuit 260. As previously mentioned, the inverter control circuit 216 includes the inverter control IC U300, which is powered by the inverter supply voltage V.sub.INV. The inverter control IC U300 is directly coupled to the gates of the FETs Q212, Q214 for controlling the FETs to be conductive and non-conductive (via pins 16 and 13). The inverter control circuit 216 comprises a preheat-frequency-set resistor R.sub.PH, which is coupled to a preheat-frequency-set input (pin 7) of the inverter control IC U300 for setting the preheat frequency f.sub.m. The preheat-frequency-set resistor R.sub.PH may have a resistance of, for example, approximately 27 kΩ, such that the preheat frequency f.sub.PH is approximately 150 kHz. The inverter control circuit 216 also comprises a preheat-time-set capacitor C.sub.PH, which is coupled to a preheat-time-set input (pin 5) of the inverter control IC U300 for setting the length of the preheat time period T.sub.PH. For example, the preheat-time-set capacitor C.sub.PH may have a capacitance of approximately 0.33 μF, such that the preheat time period T.sub.PH is approximately 700 msec.

(35) During the preheat time period T.sub.PH, a voltage V.sub.RPH generated across the preheat-frequency-set resistor R.sub.PH (i.e., at pin 7) is maintained constant, while a voltage V.sub.CPH generated across the preheat-time-set capacitor C.sub.PH (i.e., at pin 5) increases in magnitude with respect to time from approximately zero volts. When the voltage V.sub.CPH across the preheat-time-set capacitor C.sub.PH exceeds a preheat voltage threshold V.sub.PH at the end of the preheat time period T.sub.PH, the inverter control IC U300 then controls the operating frequency f.sub.OP to attempt to strike the lamp tube 122. The voltage V.sub.RPH across the preheat-frequency-set resistor R.sub.PH and the voltage V.sub.CPH across the preheat-time-set capacitor C.sub.PH are also provided to the control circuit 230, such that the control circuit is operable to properly control the inverter control IC U300 during the preheat time period T.sub.PH as will be described in greater detail below.

(36) The inverter control circuit 216 comprises an operating-frequency-set resistor R.sub.T coupled to an frequency-set-resistor input (pin 8) of the inverter control IC U300 and an operating-frequency-set capacitor C.sub.T coupled to a frequency-set-capacitor input (pin 6) for setting the operating frequency f.sub.OP of the square-wave voltage V.sub.SQ when the lamp tube 122 is illuminated (i.e., after the lamp tube has been struck). For example, the operating-frequency-set resistor R.sub.T may have a resistance of approximately 30 kΩ and the operating-frequency-set capacitor C.sub.T may have a capacitance of approximately 330 pF, such that a default operating frequency of the square-wave voltage V.sub.SQ is approximately 110 kHz.

(37) The inverter control circuit 216 further comprises an NPN bipolar junction transistor Q310 having a collector-emitter junction coupled between the frequency-set-resistor input of the inverter control IC U300 and circuit common through a resistor R312 (e.g., having a resistance of approximately 10 kΩ). The base of the transistor Q310 is coupled to receive the drive control signal V.sub.DR from the control circuit 230. The drive control signal V.sub.DR has a DC magnitude that is representative of a target operating frequency f.sub.TRGT to which the operating frequency f.sub.OP should be controlled to control the intensity of the lamp tube 122 to the target intensity L.sub.TRGT. The transistor Q310 is controlled to operate in the linear region, such that the transistor Q310 provides a controllable impedance between the frequency-set-resistor input of the inverter control IC U300 and circuit common in response to the DC magnitude of the drive control signal V.sub.DR. Accordingly, the control circuit 230 is operable to adjust the operating frequency f.sub.OP of the square-wave voltage V.sub.SQ by controlling the impedance provided by the transistor Q310 and thus the current conducted through the frequency-set-resistor input of the inverter control IC U300.

(38) The inverter control circuit 216 receives the OVP control signal V.sub.OVP from the OVP circuit 260. Specifically, the OVP control signal V.sub.OVP is coupled to an open lamp protection (OLP) input (pin 10) of the inverter control IC U300 through a resistor R320 (e.g., having a resistance of approximately 10 kΩ), and is coupled to circuit common through a capacitor C322 (e.g., having a capacitance of approximately 0.1 μE). The OVP circuit 260 comprises a voltage divider having resistors R261, R262 for scaling the magnitude of the lamp voltage V.sub.LAMP down to a magnitude that is appropriate to be received by the inverter control IC U300. For example, the resistors R261, R262 may have resistances of approximately 1 MO and 25.5 kΩ, respectively. The junction of the resistors R261, R262 is coupled to a capacitor C264 (e.g., having a capacitance of approximately 0.1 μF) through a diode D265. The junction of the capacitor C264 and the diode D265 is coupled to the inverter control circuit 216 through a zener diode Z266 for generating the OVP control signal V.sub.OVP, which is coupled to circuit common through a resistor R268 (e.g., having a resistance of approximately 100 kΩ). For example, the zener diode Z266 may have a break-over voltage of approximately 13.2 volts.

(39) During normal operation, the voltage at the OLP input of the inverter control IC U300 remains low (i.e., at approximately circuit common). However, in the event of an over-voltage condition across the lamp tube 122, the zener diode Z266 begins to conduct, such that the voltage at the OLP input of the inverter control IC U300 increases in magnitude. When the magnitude of the voltage at the OLP input exceeds an OLP threshold voltage of the inverter control IC U300 (e.g., approximately 2 volts), the inverter control IC disables the outputs (i.e., pins 13 and 16) such that the FETs Q212, Q214 are rendered non-conductive and the lamp tube 122 is not illuminated until the control circuit 230 controls the inverter circuit 210 to attempt to restrike the lamp tube once again.

(40) FIG. 8 is a simplified schematic diagram of the control circuit 230. The control circuit 230 comprises a two-speed phase-to-DC converter circuit 400 for converting the phase-control input control signal V.sub.PC-IN to a DC target voltage V.sub.TRGT that is representative of the duty-cycle DC.sub.PC of the phase-control voltage V.sub.PC and thus the target intensity L.sub.TRGT of the lamp tube 122. The DC target voltage V.sub.TRGT is amplified by a non-inverting amplifier circuit 420 to generate an amplified target voltage V.sub.A-TRGT, such that the magnitude of the amplified target voltage V.sub.A-TRGT is within a correct range to be received by an error amplifier circuit 430. For example, the DC target voltage V.sub.TRGT may be in the range of approximately 1-4 volts, while the amplified target voltage V.sub.A-TRGT is in the range of approximately 0.5-6.5 volts. A non-linear amplifier circuit 440 receives the lamp current control signal V.sub.ILAMP from the lamp current sense circuit 270 and generates an amplified lamp current signal V.sub.A-ILAMP. The error amplifier circuit 430 receives the amplified target voltage V.sub.A-TRGT and the amplified lamp current signal V.sub.T-ILAMP and generates the drive control signal V.sub.DR to adjust the operating frequency f.sub.OP of the inverter circuit 210, so as to minimize the error between the amplified target voltage V.sub.A-TRGT and the amplified lamp current signal V.sub.T-ILAMP.

(41) The phase-to-DC converter circuit 400 comprises a voltage divider having two resistors R401, R402 for scaling down the phase-control input control signal V.sub.PC-IN. For example, the resistors R401, R402 may have resistances of approximately 1 MΩ and 47 kΩ, respectively. Next, the phase-to-DC converter circuit 400 generates a switched voltage V.sub.S that has a duty-cycle approximately equal to the duty cycle DC.sub.PC of the phase-control input control signal V.sub.PC-IN. Specifically, the junction of the resistors R401, R402 is coupled to the base of a first NPN bipolar junction transistor Q404 that has a collector-emitter junction coupled between the control supply voltage V.sub.CC and circuit common through a resistor R405 (e.g., having a resistance of approximately 220 kΩ). The junction of the collector of the transistor Q404 and the resistor R405 is coupled to the base of a second NPN bipolar junction transistor Q406 that has a collector-emitter junction coupled between the control supply voltage V.sub.CC and circuit common through two resistors R408, R409 (e.g., having resistances of approximately 40 kΩ and 1 kΩ, respectively). Accordingly, the switched voltage V.sub.S is generated at the collector of the second transistor Q406.

(42) When the magnitude of the phase-control input control signal V.sub.PC-IN is approximately zero volts (i.e., when the bidirectional semiconductor switch 32 of the dimmer switch 30 is non-conductive), the first transistor Q404 is rendered non-conductive, such that the second transistor Q406 is rendered conductive and the switched voltage V.sub.S is pulled low towards circuit common. When the magnitude of the phase-control input control signal V.sub.PC-IN is greater than a phase-control threshold, e.g., approximately 15 volts (i.e., when the bidirectional semiconductor switch 32 of the dimmer switch 30 is conductive), the first transistor Q404 is rendered conductive, such that the second transistor Q406 is rendered non-conductive and the switched voltage V.sub.S is pulled high towards control supply voltage V.sub.CC through the resistors R408, R409.

(43) A ramp voltage V.sub.R is generated across a capacitor C410 (e.g., having a capacitance of approximately 0.22 μF) in response to the square-wave voltage V.sub.S. When the second transistor Q406 is non-conductive, the capacitor C410 is able to charge towards the control supply voltage V.sub.CC through the resistor R408, such that the magnitude of the ramp voltage V.sub.R increases with respect to time while the switched voltage V.sub.S is high. When the second transistor Q406 is conductive, the capacitor C410 is able to discharge through the resistor R409, such that the magnitude of the ramp voltage V.sub.R decreases at a second rate that is much faster than the first rate at which the ramp voltage increases in magnitude. Accordingly, the ramp voltage V.sub.R is generated across the capacitor C410 and has a duty cycle equal to approximately the duty cycle of the phase-control input control signal V.sub.PC-IN. Next, the ramp voltage V.sub.R is filtered by a first filter circuit, e.g., a resistor-capacitor (RC) circuit (including a resistor R411 and a capacitor C412), to generate a filtered voltage V.sub.F. For example, the resistor R411 has a resistance of approximately 220 kΩ and the capacitor C412 has a capacitance of approximately 0.22 μF, such that the first RC circuit has a time constant τ.sub.RC1 of approximately 48.4 msec.

(44) The filtered voltage V.sub.F from the first RC circuit is then filtered by a second RC circuit (having a resistor R413 and a capacitor C414) to generate the target voltage V.sub.TRGT. Two diodes D416, D418 are coupled in anti-parallel connection across the resistor R413. For example, the resistor R413 has a resistance of approximately 2.2 MO and the capacitor C414 has a capacitance of approximately 0.22 such that a time constant τ.sub.RC2 of the second RC circuit has a nominal value of approximately 484 msec (i.e., approximately 10 times slower than the first RC circuit). The magnitude of the target voltage V.sub.TRGT is a function of the square of the conduction time T.sub.CON of the bidirectional semiconductor switch 32 of the dimmer switch 30, i.e., V.sub.TRGT=f(T.sub.CON.sup.2). Accordingly, the control circuit 230 is operable to adjust the intensity of the lamp tube 122 in response to the duty-cycle DC.sub.PC of the phase-control voltage V.sub.PC according to a “square-law” dimming curve. As a result, the control circuit 230 provides finer tuning of the intensity of the lamp tube 122 near the low-end intensity L.sub.LE, such that larger variations in the conduction time T.sub.CON of the bidirectional semiconductor switch 32 result in smaller changes in the intensity of the lamp tube 122 near the low-end intensity L.sub.LE.

(45) Voltage fluctuations in the AC mains line voltage V.sub.AC of the AC power source 15 or noise on the AC mains line voltage V.sub.AC can cause the duty-cycle DC.sub.PC of the phase-control signal V.sub.PC and the magnitude of the filtered voltage V.sub.F to vary slightly. Therefore, the slow nominal value τ.sub.RC2-NOM of the time constant τ.sub.RC2 of the second RC circuit provides enough filtering such that the target voltage V.sub.TRGT is not responsive to changes in the filtered voltage V.sub.F that are less than a predetermined threshold, e.g., approximately the forward voltage of the diodes D416, D418, i.e., a diode drop (e.g., approximately 0.7 volts).

(46) However, changes in the target intensity L.sub.TRGT at the dimmer switch 30 that result in the dimmer switch changing the duty cycle DC.sub.PC of the phase-control signal V.sub.PC cause the magnitude of the filtered voltage V.sub.F to change by greater amounts and at faster rates than the voltage fluctuations and noise of the AC mains line voltage V.sub.AC. Therefore, when the magnitude of the filtered voltage V.sub.F changes by more than the forward voltage of the diodes D416, D418, one of the diodes D416, D418 will begin to conduct such that the magnitude of the target voltage V.sub.TRGT across the capacitor C414 changes quickly in response to changes in the target intensity L.sub.TRGT. Specifically, the first diode D416 is operable to conduct current into the capacitor C414 when the target intensity L.sub.TRGT increases, such that the time constant τ.sub.RC2 has a fast value τ.sub.RC2-FAST that is less than the nominal value τ.sub.RC2-NOM. In addition, the capacitor C414 is operable to discharge through the diode D418 with the fast value τ.sub.RC2-FAST when the target intensity L.sub.TRGT decreases. Accordingly, the two-speed phase-to-DC converter circuit 400 is able to filter out changes in the duty cycle DC.sub.PC of the phase-control voltage V.sub.PC due to voltage fluctuations and noise of the AC mains line voltage V.sub.AC while still providing a fast response as a result of changes in the target intensity L.sub.TRGT.

(47) Each of the diodes D416, D418 stops conducting when the difference between the magnitudes of the target voltage V.sub.TRGT and the filtered voltage V.sub.F falls below approximately the forward voltage of the respective diode. After the diodes D416, D418 stop conducting, the magnitude of the target intensity L.sub.TRGT will slowly change to be equal to the magnitude of the filtered voltage V.sub.F (according to the nominal time constant τ.sub.RC2-NOM) until the magnitudes of the voltages are equal. This results in a slow fading of the intensity of the lamp tube 122 at the end of a change in the target intensity L.sub.TRG, which provides a pleasant, soft effect on a human eye that is observing the change in the intensity of the lamp tube.

(48) The non-inverting amplifier circuit 420 comprises an operational amplifier (“op amp”) U421, such as, for example, part number LM2902PWR, manufactured by National Semiconductor Corporation. The target voltage V.sub.TRGT is coupled to the non-inverting input of the op amp U421, while an offset voltage V.sub.OFF is coupled to the inverting input of the op amp through a resistor R422 (e.g., having a resistance of approximately 160 kΩ). The offset voltage V.sub.OFF is generated by a voltage divider that is coupled between the control supply voltage V.sub.CC and circuit common, and includes two resistors R424, R425. For example, the resistors R424, R425 may have resistances of approximately 33 kΩ and 5 kΩ, respectively, such that the offset voltage V.sub.OFF has a magnitude of approximately 2 volts. The output of the op amp U421 is coupled the inverting input via the parallel combination of a resistor R426 (e.g., having a resistance of approximately 150 kΩ) and a capacitor C428 (e.g., having a capacitance of approximately 0.22 μF). The magnitude of the amplified target voltage V.sub.A-TRGT ranges from approximately 0.5 to 6.5 volts as the magnitude of the target voltage V.sub.TRGT ranges from approximately 1 to 4 volts.

(49) The non-linear amplifier circuit 440 receives the lamp current control signal V.sub.ILAMP from the lamp current sense circuit 270, which is shown in FIG. 6. The lamp current control signal V.sub.ILAMP is generated across the parallel combination of a resistor R272 (e.g., having a resistance of approximately 42) and a capacitor C274 (e.g., having a capacitance of approximately 2.2 μF). During the negative half-cycles of the lamp current I.sub.LAMP, the lamp current is conducted through a diode D276 and the parallel combination of the resistor R272 and the capacitor C274. During the positive half-cycles of the lamp current I.sub.LAMP, the lamp current is conducted through a diode D278 and is not conducted through the parallel combination of the resistor R272 and the capacitor C274. Accordingly, the lamp current control signal V.sub.ILAMP has a negative magnitude that is representative of the magnitude of the lamp current I.sub.LAMP during the negative half-cycles of the lamp current. Since the resistor R272 only conducts the lamp current I.sub.LAMP every other half-cycle, the resistor R272 dissipates half of the amount of power that would be dissipated if the resistor R272 conducted the lamp current each half-cycle.

(50) Referring back to FIG. 8, the non-linear amplifier circuit 440 comprises an op amp U441 having a non-inverting input coupled to circuit common and an inverting input coupled to receive the lamp current control signal V.sub.ILAMP through a resistor R442 (e.g., having a resistance of approximately 1 kΩ). The output of the op amp U441 is coupled to the inverting input through a resistor R444 (e.g., having a resistance of approximately 68.1 kΩ). The non-linear amplifier circuit 440 further comprises a PNP bipolar junction transistor Q445 and a resistor R446 (e.g., having a resistance of approximately 27 kΩ). The series combination of the collector-emitter junction of the transistor Q445 and the resistor R446 is also coupled between the inverting input and the output of the op amp U441. A capacitor C448 is coupled is parallel with the resistor R446 and may have, for example, a capacitance of approximately 470 pF.

(51) When the magnitude of the lamp current I.sub.LAMP is less than a current threshold (e.g., approximately 100 mA), the magnitude of the amplified lamp current signal V.sub.A-ILAMP is less than approximately the rated emitter-base voltage of the transistor Q445. At this time, only the resistor R444 is coupled between the inverting input and the output of the op amp U441, such that the non-linear amplifier circuit 440 is characterized by a first gain α.sub.1 (e.g., approximately −68). However, when the magnitude of the lamp current L.sub.LAMP is greater than the current threshold, the transistor Q445 is rendered conductive, such that the resistor R446 is coupled in parallel with the resistor R444 between the inverting input and the output of the op amp U441. Accordingly, above the current threshold, the non-linear amplifier circuit 440 is characterized by a second gain α.sub.2 that has a smaller magnitude than the first gain α.sub.1 (e.g., approximately −25).

(52) The error amplifier circuit 430 comprises an op amp U431 having a non-inverting input coupled to receive the amplified lamp current signal V.sub.A-ILAMP and an inverting input coupled to receive the amplified target voltage V.sub.A-TRGT through a resistor R432 (e.g., having a resistance of approximately 30 kΩ). The error amplifier circuit 430 further comprises two capacitors C434, C435 (e.g., each having a capacitance of approximately 4.7 nF) and a resistor R436 (e.g., having a resistance of approximately 47 kΩ). The capacitor C434 is coupled between the inverting input and the output of the op amp U431, while the series combination of the capacitor C435 and the resistor R436 is also coupled between the inverting input and the output of the op amp U431. The output of the op amp U431 is coupled to circuit common through a resister divider having two resistors R438, R439 (e.g., having resistances of 18.7 kΩ and 6.8 kΩ, respectively), where the drive control signal V.sub.DR is produced at the junction of the resistors R438, R439. The error amplifier circuit 430 operates to adjust the operating frequency f.sub.OP of the inverter circuit 210 so as to minimize the error (i.e., the difference) between the amplified lamp current signal V.sub.A-ILAMP and the amplified target voltage V.sub.A-TRGT. For example, the error amplifier circuit 430 may be characterized by a cutoff frequency of greater than or equal to approximately 10 kHz (i.e., the control circuit 230 has a bandwidth greater than or equal to approximately 10 kHz).

(53) As previously mentioned, the lamp tube 122 of the screw-in compact fluorescent lamp 120 of the first embodiment of the present invention may be filled with the fill-gas mixture having a fill-gas pressure of approximately 2 Torr and a fill-gas ratio of approximately 85:15 argon to neon. FIG. 9 is an example V-I curve 500 (i.e., the plot of the magnitude of the lamp voltage V.sub.LAMP across the lamp tube 122 with respect to the magnitude of the lamp current I.sub.LAMP conducted through the lamp tube) according to the first embodiment of the present invention. FIG. 9 also shows an example V-I curve 550 of the prior art screw-in compact fluorescent lamp 20 that has a fill gas of 100% argon at a pressure of approximately 4 Torr.

(54) By combining the lamp tube 122 having the fill-gas mixture having a fill-gas ratio of approximately 85:15 argon to neon at a pressure of approximately 2 Torr and the error amplifier 430 having a cutoff frequency of approximately 10 kHz, the V-I curve 500 of the screw-in compact fluorescent lamp 120 of the first embodiment of the present invention is much “flatter” than the V-I curve 550 of the prior art screw-in compact fluorescent lamp 20 as shown in FIG. 9. In other words, the magnitude of the lamp voltage V.sub.LAMP does not changes as much with respect to the magnitude of the lamp current I.sub.LAMP as in the prior art screw-in compact fluorescent lamp 20. Therefore, the size of the components of the resonant tank circuit 220 may be smaller and the resonant tank circuit may operate more efficiently during normal operation. Since the filament windings 229A, 229B are magnetically coupled to the resonant inductor L222, the flatter V-I curve 500 of the screw-in compact fluorescent lamp 120 of the first embodiment of the present invention provides for more favorable magnitudes of the filament voltages across the dimming range of the lamp tube 122, particularly, near the near the low-end intensity L.sub.LE when the magnitude of the lamp voltage V.sub.LAMP begins to decrease as the magnitude of the lamp current I.sub.LAMP decreases.

(55) FIGS. 10A and 10B show example waveforms of the DC bus voltage V.sub.BUS and the lamp current I.sub.LAMP, respectively, of the screw-in compact fluorescent lamp 120 of the first embodiment of the present invention. Since the cutoff frequency of the error amplifier circuit 430 (i.e., approximately 10 kHz) is much greater than the frequency of the voltage ripple of the bus voltage V.sub.BUS (i.e., approximately 120 Hz), the control circuit 230 is able to adjust the operating frequency f.sub.OP of the square-wave voltage V.sub.SQ (and thus the lamp current I.sub.LAMP) within a single half-cycle of the AC power source 15. Therefore, the operating frequency f.sub.OP changes in magnitude in response to the voltage ripple of the bus voltage V.sub.BUS during each half-cycle and the lamp current I.sub.LAMP has an envelope I.sub.ENV that is relatively constant or flat (as shown in FIG. 10B). It has been observed that this high speed operation of the error amplifier circuit 430 reduces flickering in the lamp tube 122, particularly when the lamp tube is cold and/or has just been started up. In addition, since the operating frequency f.sub.OP of the inverter circuit 210 changes during each half-cycle even when the screw-in compact fluorescent lamp 120 is maintaining the target intensity L.sub.TRGT of the lamp tube 122 constant, the compact fluorescent lamp does not generate EMI noise at specific frequencies, but spreads the frequency of the EMI noise out over a range, such that the peak magnitude of the noise is decreased.

(56) Referring back to FIG. 8, the control circuit 230 further comprises a preheat adjustment circuit 450 that modifies the operation of the phase-to-DC converter circuit 400 while the load regulation circuit 130 is preheating the filaments 228A, 228B of the lamp tube 122 (i.e., during the preheat time period T.sub.PH). The preheat adjustment circuit 450 comprises an op amp U452 having a non-inverting input coupled to receive the voltage V.sub.RPH across the preheat-frequency-set resistor R.sub.PH of the inverter control circuit 216, and an inverting input coupled to receive the voltage V.sub.CPH across the preheat-time-set capacitor C.sub.PH. The output of the op amp U452 is coupled to the capacitor C410 of the phase-to-DC converter circuit 400 through a resistor R454 (e.g., having a resistance of approximately 464 kΩ). As previously mentioned, while the inverter control IC U300 is preheating the filaments 228A, 228B of the lamp tube 122, the voltage V.sub.RPH across the preheat-frequency-set resistor R.sub.PH is maintained constant, while the voltage V.sub.CPH across the preheat-time-set capacitor C.sub.PH increases in magnitude with respect to time from approximately zero volts. During the preheat time period T.sub.PH, the op amp U452 injects current into the capacitor C410 of the phase-to-DC converter circuit 400, such that the magnitude of the target voltage V.sub.TRGT increases. Therefore, if the lamp tube 122 is being turned on to an intensity near the low-end intensity L.sub.LE, the magnitude of the lamp current I.sub.LAMP will be large enough at the end of the preheat time period T.sub.PH to ensure that the arc current is established in the lamp tube when the lamp tube is struck. After the arc current has been properly established in the lamp tube 122, the op amp U452 stops injecting current into the capacitor C410 of the phase-to-DC converter circuit 400 and the intensity of the lamp tube is controlled in response to the target intensity L.sub.TRGT determined from the duty-cycle DC.sub.PC of the phase-control voltage V.sub.PC.

(57) FIG. 11 is a simplified schematic diagram of a control circuit 630 of the dimmable screw-in compact fluorescent lamp 120 according to a second embodiment of the present invention. The control circuit 630 comprises a microprocessor U600 that implements the functions of the control circuit 330 of the first embodiment that were executed by the two-speed phase-to-DC converter circuit 400, the non-inverting amplifier circuit 420, and the error amplifier circuit 430. The control circuit 630 comprises a resistive divider including two resistors R601, R602 for scaling the phase-control input control signal V.sub.PC-IN to generate a scaled phase-control input control signal V.sub.PC-S. The microprocessor U600 receives the scaled phase-control input control signal V.sub.PC-S and the amplified target voltage V.sub.A-TRGT from the non-linear amplifier circuit 440. The microprocessor U600 generates a drive control signal V.sub.DR to control the intensity level of the lamp tube 122 to a target intensity level L.sub.TRGT. Alternatively, the microprocessor U600 may be implemented as a microcontroller, a programmable logic device (PLD), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or any suitable controller or processing device.

(58) FIG. 12 is a simplified flowchart of a control procedure 700 executed periodically by the microprocessor U600, e.g., once every half-cycle of the AC power source 15. The microprocessor U600 first measures the duty cycle V.sub.PC of the scaled phase-control input control signal V.sub.PC-S at step 710, and then determines a requested intensity level L.sub.PRES from the duty cycle V.sub.PC of the scaled phase-control input control signal V.sub.PC-S at step 712. The microprocessor U600 then determines a phase-control input change value Δ.sub.PC, i.e., the absolute value of the difference between the new requested intensity level L.sub.PRES and the present target intensity level L.sub.TRGT from the last sample, at step 714.

(59) The microprocessor U600 uses a digital low-pass filter (LPF) to process the values of the requested intensity level L.sub.PRES. If the phase-control input change value ΔPC is less than a phase-control input change threshold Δ.sub.TH at step 716, the microprocessor U600 adjusts the pole of the digital low-pass filter such that the passband frequency f.sub.P of the filter is a first predetermined frequency (e.g., approximately 0.5 Hz) at step 718. If the phase-control input change value Δ.sub.PC is not less than the phase-control input change threshold ΔTH at step 716, the microprocessor U600 adjusts the pole of the digital low-pass filter so that the passband frequency f.sub.P of the filter is a second predetermined frequency (e.g., approximately 5 Hz) at step 720. Accordingly, when the duty-cycle DC.sub.PC of the phase-control signal V.sub.PC is remaining relatively constant (i.e., when the phase-control input change value Δ.sub.PC is less than the phase-control input change threshold Δ.sub.TH), the requested intensity level L.sub.PRES is more heavily filtered, and the target intensity level L.sub.TRGT is adjusted with a slow time constant τ.sub.DLPF-SLOW. When the duty cycle DC.sub.PC is changing rapidly, the requested intensity level L.sub.PRES is filtered less, and the target intensity level L.sub.TRGT is adjusted with a fast time constant τ.sub.DLPF-FAST. For example, the phase-control input change threshold Δ.sub.TH may be equal to the target intensity level L.sub.TRGT divided by ten, such that the microprocessor U600 adjusts the target intensity level L.sub.TRGT using the fast time constant τ.sub.DLPF-FAST when there is greater than or equal to a 10% change in the target intensity level L.sub.TRGT.

(60) After adjusting the passband frequency f.sub.P of the digital low-pass filter at steps 718, 720, the microprocessor U600 processes the requested intensity level L.sub.PRES through the digital low-pass filter at step 722 to determine the target intensity level L.sub.TRGT to which the microprocessor will now control the intensity level of the lamp tube 122. The microprocessor U600 then samples the amplified lamp current signal V.sub.A-ILAMP at step 724, and determines an actual intensity level L.sub.ACTUAL from the sampled values of the amplified lamp current signal V.sub.A-ILAMP at step 726. The microprocessor U600 then determines an error e.sub.L between the target intensity level L.sub.TRGT and the actual intensity level L.sub.ACTUAL at step 728 and controls the drive control signal V.sub.DR in response to the error e.sub.L to adjust the lighting intensity of the lamp tube 122 towards the target intensity level L.sub.TRGT at step 730 before the control procedure 700 exits.

(61) While the present invention has been described with reference to the screw-in compact fluorescent lamp 120, the concepts of the present invention could be used in lighting control systems having a ballast circuit that is separate from the controlled fluorescent lamps, for example, mounted to a junction box next to a lighting fixture in which the lamps are installed. In addition, the circuits and methods of determining the target intensity level L.sub.TRGT in response to the duty cycle DC.sub.PC of the phase-control signal V.sub.PC could be used in another type of load control device, such as, for example, a light-emitting diode (LED) driver for driving an LED light source (i.e., an LED light engine); a screw-in luminaire including a dimmer circuit and an incandescent or halogen lamp; a dimming circuit for controlling the intensity of an incandescent lamp, a halogen lamp, an electronic low-voltage lighting load, a magnetic low-voltage lighting load, or another type of lighting load; an electronic switch, controllable circuit breaker, or other switching device for turning electrical loads or appliances on and off; a plug-in load control device, controllable electrical receptacle, or controllable power strip for controlling one or more plug-in electrical loads; and a motor control unit for controlling a motor load, such as a ceiling fan or an exhaust fan.

(62) Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.