System and method for reducing power loss in switched-capacitor power converters

Abstract

A system for reducing power loss in a switched-capacitor converter includes a first and second switched capacitor sub-converter each having a flying capacitor and a first, second, third, and fourth switching device. Each switching device is controlled by one of a first, second, third, and fourth clock signal. The first, second, third and fourth clock signals of the second switched capacitor sub-converter are inverted such that the first switched capacitor sub-converter operates during a first phase and the second switched capacitor converter operates during a second phase that is 1800 degrees out of phase from the first phase. The system also includes a resonant charge sharing portion for coupling a bottom-plate parasitic capacitance of the first switched capacitor sub-converter to a bottom-plate parasitic capacitance of the second switched capacitor converter.

Claims

1. A system for reducing power loss in a switched-capacitor converter, the system comprising: a first and second switched capacitor sub-converter each having a first, second, third, and fourth switching device each controlled by one of a first, second, third, and fourth clock signal, and a flying capacitor, wherein the first, second, third and fourth clock signals of the second switched capacitor sub-converter are inverted such that the first switched capacitor sub-converter operates during a first phase and the second switched capacitor converter operates during a second phase that is 180 degrees out of phase from the first phase; and, a resonant charge sharing portion for coupling a bottom-plate parasitic capacitance of the first switched capacitor sub-converter to a bottom-plate parasitic capacitance of the second switched capacitor converter.

2. The system of claim 1, the resonant charge sharing portion comprising a sharing inductor coupled in series with a sharing switch.

3. The system of claim 2, wherein a capacitance value of the bottom-plate parasitic capacitance is the same for each of the first and second switched capacitor sub-converters, and the sharing switch is in an on mode for a length of time defined by π√{square root over (L.sub.sC.sub.bp/2)} where L.sub.s is an inductance of the sharing inductor and C.sub.bp is the bottom-plate parasitic capacitance of at least one of the first and second switched capacitor sub-converters.

4. The system of claim 2, wherein a capacitance value of the bottom-plate parasitic capacitance is not equal for each of the first and second switched capacitors, and the sharing switch is in an on mode for a length of time is defined by $\pi \sqrt{L_s\frac{C_{bp1}*C_{bp2}}{C_{bp1}+C_{bp2}}},$ where L.sub.s is the inductance of the sharing inductor, C.sub.bp1 is the bottom-plate parasitic capacitance value of the first switched capacitor sub-converter, and C.sub.bp2 is the bottom-plate parasitic capacitance value of the second switched capacitor sub-converter.

5. The system of claim 1, the first and second switched capacitor converters being resonant such that a resonant inductor is coupled in series with the flying capacitor.

6. The system of claim 1, wherein, within each first and second switched capacitor converters, the first switching device is electrically coupled between an input node and a first flying node, the second switching device is electrically coupled between the first flying node and an output node, the third switching device is electrically coupled between the output node and a second flying node, and the fourth switching device is electrically coupled between the second flying node and ground.

7. The system of claim 6, wherein, within each of the first and second switched capacitor converters, the flying capacitor is electrically coupled between each of the first and second flying nodes, and a bottom-plate parasitic capacitance is between the second flying node and ground.

8. The system of claim 7, wherein, within each of the first and second switched capacitor converters, a resonant inductor is coupled in series with the flying capacitor between first flying node and the flying capacitor.

9. The system of claim 7, wherein, within each of the first and second switched capacitor converters, a resonant inductor is coupled between the second flying node and the flying capacitor.

10. The system of claim 9, wherein the resonant charge sharing portion comprises a sharing switch, controlled via a fifth clock signal, coupled to the second flying node, within each of the first and second switched capacitor converters.

11. The system of claim 10, wherein the sharing switch is in an on state, as determined by the fifth clock signal, for a length of time defined by $\begin{array}{cc}\pi \sqrt{\left(L_{x1}+L_{x2}\right)\frac{C_{bp1}*C_{bp2}}{C_{bp1}+C_{bp2}}},& \end{array}$ where L.sub.x1 is the inductance value of the resonant inductor of the first switched capacitor converter, L.sub.x2 is the inductance value of the resonant inductor of the second switched capacitor converter, C.sub.bp1 is the capacitance value of the bottom-plate parasitic capacitance of the first switched capacitor converter, and C.sub.bp2 is the capacitance value of the bottom-plate parasitic capacitance of the second switched capacitor converter.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) FIG. 1 depicts an exemplary prior art 2:1 switched-capacitor converter.

(2) FIG. 2 depicts an exemplary prior art physical representation of the flying capacitor Cx, of FIG. 1.

(3) FIG. 3 depicts a common representation for a switched capacitor voltage conversion element.

(4) FIG. 4 is a prior-art graph depicting effective resistance normalized to effective series resistance versus frequency for switched-capacitor and ReSC converters.

(5) FIG. 5A depicts a prior-art multi-phase switched-capacitor converter including a charge recycling system.

(6) FIG. 5B illustrates an exemplary gate driver circuit for generating signals clk1 through clk4 to drive the charge recycling system of FIG. 5A.

(7) FIG. 6 depicts a timing diagram of signal waveforms for the charge recycling system of FIG. 5A.

(8) FIG. 7 depicts an exemplary system for reducing power loss in switched-capacitor power converters utilizing a resonant charge sharing scheme, in one embodiment.

(9) FIG. 8 depicts a signal timing and waveform diagram for the system of FIG. 7, in an embodiment.

(10) FIG. 9 depicts a power loss graph depicting power loss versus frequency of switch-capacitor converters in cases of hard switching, resistive charge sharing, and resonant charge sharing.

(11) FIG. 10 depicts exemplary simulation results generated in a SPICE simulation for the converter in FIG. 7.

(12) FIG. 11 depicts an alternate system for reducing power loss in a ReSC converter, in one embodiment.

(13) FIG. 12 depicts an alternate system for reducing power loss in a ReSC power converter, in one embodiment.

DETAILED DESCRIPTION OF THE DRAWINGS

(14) FIG. 7 depicts an exemplary system 700 for reducing power loss in switched-capacitor power converters utilizing a resonant charge sharing portion 722, in one embodiment. System 700 includes a first switched-capacitor sub-converter 702 and a second switched-capacitor sub-converter 704 similar thereto. First and second switched-capacitor sub-converters 702, 704 are similar to first and second switched-capacitor sub-converters 502, 504, discussed above. First switched-capacitor sub-converter 702 includes a plurality of first switching devices 706. For example, a first switch 706(1) of the plurality of first switching devices 706 is electrically coupled between an input node and a first flying node, and a second switch 706(2) is electrically coupled between the flying node and an output node, the third switch 706(3) is electrically coupled between the output node and a second flying node, and a fourth switch 706(4) is electrically coupled between the output node and ground. Second switched-capacitor sub-converter 702 has a similar architecture including a plurality of second switching devices 708. Within the disclosure herein, switching device may be an n-channel or p-channel FET transistor, as illustrated in FIG. 7, or may alternatively be any other type of switching device known in the art such as a different type of FET, a BJT, an IGBT, etc.

(15) For example, in the embodiment illustrated in FIG. 7, each switched-capacitor sub-converter 702, 704 includes two pMOS transistors and two nMOS transistors in one embodiment. Each one of the plurality of first and second switching devices 706, 708 is independently controlled by a clock signal 710. Second switched-capacitor sub-converter 704 further includes a plurality of inverters 712 and the clock signals 710 controlling switches 708 are configured such that second switched capacitor sub-converter 704 operates 180 degrees out of phase as compared to first switched-capacitor sub-converter 702. Each of first and second switched-capacitor sub-converters further include a first (C.sub.bp1) and second (C.sub.bp2) bottom-plate parasitic capacitance 714, 716, respectively, as well as a first and second flying capacitor 718, 720, respectively.

(16) System 700 further includes a resonant charge sharing portion 722 including an inductor 724 (Lx) connected in series with a switch 726. Resonant charge sharing portion 722 is coupled between first bottom-plate parasitic capacitance 714 and second bottom-plate parasitic capacitance 716. Switch 726 is controlled by clock signal 728 such that, during an interval between each change in phase (i.e. during the transition from phase 1 to phase 2, and the transition from phase 2 to phase 1 as discussed in further detail below with reference to FIG. 8), clock signal 728 turns switch (Sx) 726 to “On.” During this “On” time, one of first and second bottom-plate parasitic capacitances 714, 716 is charged substantially to V.sub.out and the other to zero volts. Charge flows through inductor 724, storing energy in inductor 724. If and when the voltage potential across whichever of first and second bottom-plate parasitic capacitances 714, 716 that was initially charged to V.sub.out is substantially equal to zero volts, or below some other predetermined threshold, clock signal 728 controls switch 726 to “off.” The above charge transfer process is essentially a resonant process as it requires transferring energy from the electrostatic domain to the magnetic domain and then back to the electrostatic domain.

(17) Within system 700, assuming the resistance of switch 726 is small, the energy transfer theoretically has 100% efficiency because the energy within bottom-plate parasitic capacitances 714, 716 is transferred between first and second switch-capacitor converter 702, 704 without loss.

(18) In one embodiment, clock signal 728 is controlled such that the time that clock signal 728 controls switch 726 in the “on” state is substantially equal to ½ of the resonant period for the loop that contains the first bottom-plate parasitic capacitance 714, the inductor 724 and the second bottom-plate parasitic capacitance 716. For example, the resonant frequency of such loop is as follows:

(19) $\begin{array}{cc}{f}_0=\frac{1}{2\pi \sqrt{L_R{C}_R}},& \mathrm{Equation}\left[5\right]\end{array}$
where L.sub.R and C.sub.R are the inductance and capacitance respectively of the loop. L.sub.R is substantially equal to the inductance of inductor 724 and C.sub.R is substantially equal to

(20) $\frac{1}{2}{C}_{bp1}=\frac{1}{2}{C}_{bp2}$
in the embodiment where C.sub.bp1=C.sub.bp2 The resonant period is 1/f.sub.0, therefore the time that switch 726 is in the “on” state is substantially equal to 1/(2.Math.f.sub.0), or π√{square root over (L.sub.xC.sub.bp/2)}, where C.sub.bp is the bottom-plate parasitic capacitance of either C.sub.bp1 714 or C.sub.bp2 716. In an embodiment where C.sub.bp1≠C.sub.bp2, then switch 726 would be in the “on” state for a time represented by

(21) $\pi \sqrt{L_x\frac{C_{bp1}{C}_{bp2}}{C_{bp1}+C_{bp2}}}.$

(22) Although system 700 is illustrated as transferring energy from the bottom-plate parasitic capacitance, system 700 may equally apply for the top plate parasitic capacitance. For example, the parasitic drain-bulk capacitance of the MOSFET switches (e.g. switches 706) represents a significant common-mode capacitance in many cases and may be lumped into bottom-plate parasitic capacitance C.sub.bp1 714 and bottom-plate parasitic capacitance C.sub.bp2 716. Also, because flying capacitors 718 and 720 are usually significantly larger in magnitude than C.sub.bp1 714 and C.sub.bp2 716, they act as a short circuit at high frequency which enables transferring charge also for the top-plate common-mode capacitance (C.sub.tp). Similarly, this enables resonant charge transfer not only for the parasitic capacitance of the switches 706 controlled by clock signal 710(3) and clock signal 710(4), but also those controlled by clock signal 710(1) and clock signal 710(2).

(23) FIG. 8 depicts a signal timing and waveform diagram 800 for system 700, of FIG. 7 during a transition from a first phase to a second phase. As discussed above, when clock signal 728 (clk5) is high, current flows through inductor 724 to transfer energy between capacitance C.sub.bp1 714 and capacitance C.sub.bp2 716. The current is approximately sinusoidal in this time period because the resonant operation of the charge sharing portion 722. In an ideal case, wherein there is negligible or zero resistance in the resonant loop consisting of inductor 724 and first and second bottom-plate parasitic capacitances 714, 716, and switch 726, system 700 can transfer energy with substantially zero loss. However, if there is series resistance in the resonant loop, the charge transfer process will incur some power loss. However, unlike the prior art systems discuss with regards to FIGS. 1-6, system 700 will typically recover 50% or greater energy stored within the bottom-plate parasitic capacitances 714, 716.

(24) The resonant charge sharing process occurs during a time period when all switches 706(1-4) and 708(1-4) are off. During this time, clock signal 728 transitions high, turning on switch 726. At this same time, clock signal 710(1) is high such that switches 706(1) and 708(2) are off; clock signal 710(2) is low such that switches 706(2) and 708(1) are off; clock signal 710(3) is high such that switches 706(3) and 708(4) are off; clock signal 710(4) is low such that switches 706(4) and 708(3) are off. Therefore, because switches 706 and 708 are off, the only path for current to flow when switch 726 is on, is through inductor 724, which transfers charge between capacitor C.sub.bp1 and C.sub.bp2.

(25) It should be noted that there is normally a substantial time delay between the time when clock signal 710(2) and clock signal 710(4) transition from high to low and the time when clock signal 728 transitions from low to high. This is to prevent overlap of the on-state of switches 706(2), 706(4), 708(1), and 708(3) with the on-state of switch 726. This time delay is normally referred to as a “dead-time” as all switches are off during this time period. The dead-time is normally substantially shorter than any of the time periods when switches are on. Similarly, there is some dead-time between the time when clock signal 728 transitions low and the time when clock signal 710(1) and clock signal 710(3) transition low to prevent overlap of the on-state of switches 706(1), 706(3), 708(2), and 708(4) with the on-state of switch 726.

(26) FIG. 9 depicts a power loss graph 900 depicting power loss versus frequency for (i) prior art hard switching of bottom-plate parasitic capacitance, of FIGS. 1-2, 902 (ii) prior art resistive charge sharing of FIG. 5, 904, (iii) the resonant charge sharing of system 700 at 1 mΩ, of FIG. 7, 906, (iv) the resonant charge sharing of system 700 at 100 mΩ, of FIG. 7, 908, and (v) the resonant charge sharing of system 700 at 500 mΩ, of FIG. 7, 910 as generated with SPICE simulation. The simulation considers a SC converter with bottom-plate parasitic capacitance of 300 pF in a configuration similar to FIG. 7 above. The V.sub.in is 2.0V, and V.sub.out is 1.0V in an ideal case.

(27) In the traditional case 902, (i.e. FIG. 1 where the bottom-plate capacitors are hard switched between V.sub.out and GND), the power loss is (C.sub.pb1+C.sub.bp2)V.sub.out.sup.2f.sub.sw. At f.sub.sw=100 MHz, and the power loss to bottom-plate parasitic capacitance is substantially 60 mW. In the prior art case 904 (i.e. FIG. 5), the power loss at 100 MHz is 30 mW.

(28) Within the embodiment described in FIG. 7, if the series resistance, in the resonant charge sharing portion 722 comprising capacitance 714, capacitance C.sub.bp2 716, inductor L.sub.x 724 and switch S.sub.x 726, is substantially zero (i.e. case 906) the power loss due to bottom-plate parasitic capacitance is substantially zero for all switching frequencies. In case 906, the power loss is shown for the total resistance in resonant charge sharing portion 722 being 100 mΩ. In case 908, the power loss is shown for the total resistance in resonant charge sharing portion 722 being 500 mΩ. In all three cases 906, 908, 910, it is clearly illustrated that the embodiments herein potentially substantially reduce power loss compared to the prior art.

(29) FIG. 10 depicts exemplary simulation results generated in a SPICE simulation for the converter in FIG. 7. The SPICE simulation depicts the following signals: clk1 1002, clk2 1004, clk3 1006, clk4 1008, clk5 1010, Vc.sub.bp1 1012, Vc.sub.bp2 1014, and the current signal I.sub.Lx 1016. In the simulation, V.sub.in was substantially 2 volts, V.sub.out was substantially 1 volt, C.sub.bp1 and C.sub.bp2 were each 1 nF, inductor 724 was 1 nH, and the switching frequency was substantially 80 MHz. The values for Lx, C.sub.bp1 and C.sub.bp2 were set such that they predict a resonant frequency of substantially 225 MHz, which is consistent with the duration of the pulse with of clock signal 728 in the high-state which is substantially 2.2 ns or half the resonant period for a 225 MHz signal. The simulation models the resistance in series with inductor 724 as 1 mΩ and it can be seen that will small resistance in the resonant path that substantially all of the energy in bottom-plate parasitic capacitance 714 can be transferred to bottom-plate parasitic capacitance 716 and vice versa.

(30) FIG. 11 depicts an alternate system 1100 for reducing power loss in a ReSC converter, in one example. System 1100 includes a first ReSC sub-converter 1102 and a second ReSC sub-converter 1104. First switched capacitor sub-converter 1102 is similar to first switched capacitors above (502, 702) and includes a plurality of transistors 1106, a first flying capacitor 1118 and a first bottom-plate parasitic capacitance 1114. First switched capacitor sub-converter 1102 differs from the above described first switched capacitors 502, 702 in that first switched capacitor sub-converter 1102 is a resonant switched capacitor converter. The resonant characteristic is caused by a first resonant inductor 1119 coupled in series between first flying capacitor 1118 and the drain of first transistor 1106(1).

(31) Second resonant switched capacitor sub-converter 1104 is similar to first switched capacitor sub-converter 1102 in that it is resonant (i.e. sub-converter 1104 includes a second resonant inductor 1121 coupled in series between the drain of transistor 1108(1) and flying capacitor 1120.

(32) System 1100 further includes a resonant charge sharing portion 1122 having an inductor 1124 and a switch 1126. Resonant charge sharing portion 1122 operates in a similar manner as discussed above with regards to resonant charge sharing portion 722. For example, each of first and second resonant switched capacitor sub-converters 1102, 1104 operate at 180 degrees out of phase with each other. Switch 1126 is controlled via a clock signal (clk5) 1128. Inductor 1124, switch 1126, and clock signal 1128 within resonant charge sharing portion 1122 are similar to inductor 724, switch 726, and clock signal 728, respectively, within resonant charge sharing portion 722, discussed above.

(33) System 1100 offers the benefit of the resonant switched capacitor converter architecture as opposed to the architecture of system 700, as well as the prior art. Therefore, system 1100 is able to operate with nearly the same effective resistance as an equivalent SC converter (i.e. system 700) with the same total capacitance, but at a lower frequency. The addition of the resonant charge sharing portion 1122 enables a typical resonant switched capacitor converter architecture to operate with substantially less bottom-plate switching loss, for example less than 50%, as discussed with regards to FIGS. 7-8, above.

(34) FIG. 12 depicts an alternate system 1200 for reducing power loss in a ReSC power converter, in one example. System 1200 includes a first resonant switched capacitor sub-converter 1202 and a second resonant switched capacitor sub-converter 1204. Resonant switched capacitor sub-converters 1202 and 1204 are similar to resonant switched capacitor sub-converters 1102 and 1104 however resonant switched capacitor sub-converters 1202 and 1204 do not include a resonant inductor in series with the flying capacitor. Instead, first and second resonant switched capacitor sub-converters 1202 and 1204 each include a respective first and second resonant inductor 1230, 1232 coupled to the flying capacitor 1218, 1220, respectively. I.e. first resonant inductor 1230 is coupled to the drain of third transistor 1206(3) and the node between flying capacitor 1218 and bottom-plate capacitor 1214. Second resonant inductor 1232 is coupled to the drain of third transistor 1208(3) and the note between flying capacitor 1220 and bottom-plate capacitor 1216.

(35) System 1200 includes resonant charge sharing portion 1222 which includes switch 1226 controlled via clock signal 1228. Unlike resonant charge sharing portion 722, 1122, discussed above, resonant charge sharing portion 1222 does not include an inductor (i.e. inductors 724, 1124). Instead, resonant charge sharing portion 1222 utilizes resonant inductors 1230, 1232 within first and second resonant switched capacitor sub-converters 1202, 1204.

(36) The time interval in which switch 1226 is turned “on”, i.e. via control by clock signal 1228 is determined by the following:

(37) $\begin{array}{cc}\pi \sqrt{\left(L_{x1}+L_{x2}\right)\frac{C_{bp1}*C_{bp2}}{C_{bp1}+C_{bp2}}}.& \mathrm{Equation}\left[6\right]\end{array}$
Also in this configuration, the parasitic top plate capacitance may be lumped into C.sub.bp1 and C.sub.bp2. The parasitic common-mode capacitance connected to the drain terminals of switches controlled by clock signals 1210(1) and 1210(2) may additionally be lumped into the bottom-plate parasitic capacitances. However, because switch 1226 is directly connected between the drain terminals of switches controlled by clock signals 1210(3) and 1210(4), the configuration shares charge between the parasitic common mode capacitance at the drain terminals of these switches.

(38) Features described above as well as those claimed below may be combined in various ways without departing from the scope hereof. The following examples illustrate some possible, non-limiting combinations:

(39) (A1) A system for reducing power loss in a switched-capacitor converter may include a first and second switched capacitor sub-converter each having a first, second, third, and fourth switching device each controlled by one of a first, second, third, and fourth clock signal, and a flying capacitor, wherein the first, second, third and fourth clock signals of the second switched capacitor sub-converter are inverted such that the first switched capacitor sub-converter operates during a first phase and the second switched capacitor converter operates during a second phase that is 180 degrees out of phase from the first phase; and, a resonant charge sharing portion for coupling a bottom-plate parasitic capacitance of the first switched capacitor sub-converter to a bottom-plate parasitic capacitance of the second switched capacitor converter.

(40) (A2) In the system denoted above as (A1), the resonant charge sharing portion may include a sharing inductor coupled in series with a sharing switch.

(41) (A3) In any of the systems denoted above as (A1) through (A2), the capacitance value of the bottom-plate parasitic capacitance may be the same for each of the first and second switched capacitor sub-converters, and the sharing switch may be in an on mode for a length of time defined by π√{square root over (L.sub.sC.sub.bp/2)} where L.sub.s is the inductance of the sharing inductor and C.sub.bp is the bottom-plate parasitic capacitance value of at least one of the first and second switched capacitor sub-converters.

(42) (A4) In either system denoted above as (A1) and (A2), the capacitance value of the bottom-plate parasitic capacitance is not equal for each of the first and second switched capacitors, and the sharing switch is in an on mode for a length of time is defined by

(43) $\pi \sqrt{L_s\frac{C_{bp1}*C_{bp2}}{C_{bp1}+C_{bp2}}},$
where L.sub.s is the inductance of the sharing inductor, C.sub.bp1 is the bottom-plate parasitic capacitance value of the first switched capacitor sub-converter, and C.sub.bp2 is the bottom-plate parasitic capacitance value of the second switched capacitor sub-converter.

(44) (A5) In any of the systems denoted above as (A1) through (A4), the first and second switched capacitor converters may be resonant such that a resonant inductor is coupled in series with the flying capacitor.

(45) (A6) In any of the systems denoted above as (A1) through (A5), within each first and second switched capacitor converters, the first switching device may be electrically coupled between an input node and a first flying node, the second switching device may be electrically coupled between the first flying node and an output node, the third switching device may be electrically coupled between the output node and a second flying node, and the fourth switching device may be electrically coupled between the second flying node and ground.

(46) (A7) In the system denoted above as (A6), within each of the first and second switched capacitor converters, the flying capacitor may be electrically coupled between each of the first and second flying nodes, and a bottom-plate parasitic capacitance may be between the second flying node and ground.

(47) (A8) In either of the systems denoted above as (A6) and (A7), within each of the first and second switched capacitor converters, a resonant inductor may be coupled in series with the flying capacitor between first flying node and the flying capacitor.

(48) (A9) In any of the systems denoted above as (A6) through (A8), within each of the first and second switched capacitor converters, a resonant inductor may be coupled between the second flying node and the flying capacitor.

(49) (A10) In any the systems denoted above as (A1) through (A9), the resonant charge sharing portion may include a sharing switch, controlled via a fifth clock signal, coupled to the second flying node, within each of the first and second switched capacitor converters.

(50) (A11) In the system denoted as (A10), the sharing switch may be in an on state, as determined by the fifth clock signal, for a length of time defined by

(51) $\begin{array}{cc}\pi \sqrt{\left(L_{x1}+L_{x2}\right)\frac{C_{bp1}*C_{bp2}}{C_{bp1}+C_{bp2}}},& \end{array}$
where L.sub.x1 is the inductance value of the resonant inductor of the first switched capacitor converter, L.sub.x2 is the inductance value of the resonant inductor of the second switched capacitor converter, C.sub.bp1 is the capacitance value of the bottom-plate parasitic capacitance of the first switched capacitor converter, and C.sub.bp2 is the capacitance value of the bottom-plate parasitic capacitance of the second switched capacitor converter.

(52) Changes may be made in the above methods and systems without departing from the scope hereof. It should thus be noted that the matter contained in the above description or shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. The following claims are intended to cover all generic and specific features described herein, as well as all statements of the scope of the present method and system, which, as a matter of language, might be said to fall therebetween.