Current-limiting circuit

Abstract

A current-limiting circuit that includes a transistor connected between an input terminal and an output terminal of the current-limiting circuit. A controller is arranged to monitor a current flowing through the transistor and to control the transistor based on the monitored current so as to limit the current, wherein a voltage dropped across the transistor varies over a range of values during operation in a current-limiting mode. The controller includes a timing module arranged to control, based on a value of the voltage across the transistor, a period of time for which the transistor limits the current. For all ranges of voltage that may be dropped across the transistor during the current-limiting mode, the timing module is arranged to control the respective period of time for each range, such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

Claims

1. A current-limiting circuit, comprising: a transistor connected between an input terminal of the current-limiting circuit and an output terminal of the current-limiting circuit; and a controller arranged to monitor a current flowing through the transistor and operable in a current-limiting mode to control the transistor based on the monitored current so as to limit the current, wherein a voltage dropped across the transistor varies over a range of values during operation in the current-limiting mode, the controller comprising: a timing module arranged to control, based on a value of the voltage across the transistor during operation in the current-limiting mode, a period of time for which the transistor limits the current during operation in the current-limiting mode, wherein, for ranges of voltage across the transistor during operation in the current-limiting mode that lie below a threshold voltage, the timing module is arranged to control respective periods of time such that the transistor dissipates an amount of energy that is substantially the same for the ranges of voltage below the threshold voltage, and for ranges of voltage across the transistor during operation in the current-limiting mode that lie above the threshold voltage, the timing module is arranged to control respective periods of time such that, further a range of voltage is from the treshold voltage, the smaller the amount of energy dissipated by the transistor.

2. The current-limiting circuit according to claim 1, wherein the timing module is arranged to control the period of time for which the transistor limits the current during operation in the current-limiting mode to vary as
A/(B*V.sub.DS+C*max[V.sub.DS−V.sub.TH,0]), wherein V.sub.DS denotes the value of the voltage across the transistor during operation in the current-limiting mode, V.sub.TH is the threshold voltage and A, B and C are constants, the values of A, B, C and V.sub.TH being such that, for all ranges of voltage dropped across the transistor during operation in the current-limiting mode, the timing module is arranged to control the respective period of time for each range such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

3. The current-limiting circuit according to claim 1, further comprising: a temperature sensor arranged to measure a temperature of the transistor, wherein, for all ranges of voltage dropped across the transistor during operation in the current-limiting mode, the controller is arranged to control, based on the temperature measured by the temperature sensor.

4. A current-limiting circuit comprising: a transistor connected between an input terminal of the current-limiting circuit and an output terminal of the current-limiting circuit; and a controller arranged to monitor a current flowing through the transistor and operable in a current-limiting mode to control the transistor based on the monitored current so as to limit the current, wherin a voltage dropped across the transistor varies over a range of values during operations in the current-limiting mode, the controller including a timing module arranged to control, based on a value of the voltage across the transistor during operations in the current-limiting mode, a period of time for which the transistor limits the current during operations in the current-limiting mode, the timing module comprising: a capacitor; a charging circuit arranged to charge the capacitor at a rate dependent on the voltage across the transistor during operation in the current-limiting mode; and a control signal generator arranged to generate a control signal to cause the controller to cease operating in the current-limiting mode when a voltage across the capacitor reaches a predetermined capacitor voltage threshold, wherein the charging circuit is arranged to charge the capacitor such that the voltage across the capacitor reaches the predetermined capacitor voltage threshold in the period of time required for the transistor to dissipate substantially the maximum amount of energy that it is capable of dissipating without sustaining damage during operation in the current-limiting mode.

5. The current-limiting circuit according to claim 4, wherein the charging circuit is arranged to charge the capacitor such that the voltage across the capacitor reaches the predetermined capacitor voltage threshold in a period of time given by
A/(B*V.sub.DS+C*max[V.sub.DS−V.sub.TH,0])+D, wherein V.sub.DS denotes the value of the voltage across the transistor during operation in the current-limiting mode, V.sub.TH is a threshold voltage that sets a threshold for V.sub.DS and A, B, C and D are constants, the values of A, B, C, D and V.sub.TH being such that, for all ranges of voltage dropped across the transistor during operation in the current-limiting mode, the timing module is arranged to control a respective period of time for each range such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

6. The current-limiting circuit according to claim 4, wherein: the controller is further arranged to monitor the voltage across the transistor during operation in the current-limiting mode, and operable in the current-limiting mode to control the transistor based on both the monitored current and the monitored voltage so as to limit both the current through the transistor and power dissipated by the transistor; and the charging circuit is arranged to charge the capacitor such that the voltage across the capacitor reaches the predetermined capacitor voltage threshold in a period of time given by
E/V.sub.DS+F, wherein V.sub.DS denotes the value of the voltage across the transistor during operation in the current-limiting mode, and E and F are constants, the values of E and F being such that, for all ranges of voltage dropped across the transistor during operation in the current-limiting mode, the timing module is arranged to control a respective period of time for each range such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

7. A current-limiting circuit comprising: a transistor connected between an input terminal of the current-limiting circuit and an output terminal of the current-limiting cicuit; and a controller arranged to monitor a current flowing through the transistor and operable in a current-limiting mode to control the transistor based on the monitored current so as to limit the current, wherein a voltage dropped across the transistor varies over a range of values during operations in the current-limiting mode, the controller including a timing module arranged to control, based on a value of the voltage across the transistor during operations in the current-limiting mode, a period of time for which the transistor limits the current during operations in the current-limiting mode, the timing module comprising: a calculator arranged to calculate, using a function of the voltage across the transistor during operation in the current-limiting mode and of one or more parameters, the period of time for which the transistor limits the current during operation in the current-limiting mode; and a control signal generator arranged to generate a control signal to cause the controller to cease operating in the current-limiting mode when the calculated period of time elapses, wherein the one or more parameters are such that, for all ranges of voltage dropped across the transistor during operation in the current-limiting mode, the timing module is arranged to control a respective period of time for each range such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

8. The current-limiting circuit according to claim 7, wherein the timing module further comprises: a voltage monitor arranged to monitor the voltage dropped across the transistor and determine an initial value of the voltage, VD.sub.DSi, that is dropped across the transistor during operation in the current-limiting mode, wherein the calculator is arranged to calculate the period of time for which the transistor limits the current during operation in the current-limiting mode as
A/(B*V.sub.DSi+C*max[V.sub.DSi−V.sub.TH,0])+D, wherein V.sub.TH is a threshold voltage that sets a threshold for the voltage dropped across the transistor and A, B, C and D are constants, the values of A, B, C, D and V.sub.TH being such that, for all ranges of voltage dropped across the transistor during operation in the current-limiting mode, the timing module is arranged to control the respective period of time for each range such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

9. The current-limiting circuit according to claim 7, wherein: the controller is further arranged to monitor the voltage across the transistor during operation in the current-limiting mode, and operable in the current-limiting mode to control the transistor based on both the monitored current and the monitored voltage so as to limit both the current through the transistor and power dissipated by the transistor; the timing module further comprises a voltage monitor arranged to monitor the voltage dropped across the transistor and determine an initial value of the voltage, V.sub.Dsi, that is dropped across the transistor during operation in the current-limiting mode; the calculator is arranged to calculate the period of time for which the transistor limits the current during operation in the current-limiting mode as
E/V.sub.DSi+F, wherein E and F are constants whose values are such that, for all ranges of voltage dropped across the transistor during operation in the current-limiting mode, the timing module is arranged to control the respective period of time for each range such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

10. A current-limiting circuit comprising: a transistor connected between an input terminal of the current-limiting circuit and an output terminal of the current-limiting circuit; and a controller arranged to monitor a current flowing through the transistor and monitor a voltage across the transistor during operation in a current-limiting mode, and operable in the current-limiting mode to control the transistor based on both the monitored current and the monitored voltage so as to limit both the current through the transistor and power dissipated by the transistor, the controller including a timing module arranged to control a period of time for which the transistor limits the current during operation in the current-limiting mode to vary as
E/V.sub.DS+F, wherein V.sub.DS denotes the value of the voltage across the transistor during operation in the current-limiting mode, and E and F are constants, the values of E and F being such that, for all ranges of voltage dropped across the transistor during operation in the current-limiting mode, the timing module is arranged to control a respective period of time for each range such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

11. A method of configuring a current-limiting circuit comprising a transistor connected between an input terminal of the current-limiting circuit and an output terminal of the current-limiting circuit, and a controller arranged to monitor a current flowing through the transistor and operable in a current-limiting mode to control the transistor based on the monitored current so as to limit the current, wherein a voltage dropped across the transistor varies over a range of values during operation in the current-limiting mode, the method comprising: determining, for all ranges of voltage dropped across the transistor during operation in the current-limiting mode, a respective period of time for each range, for which period of time the transistor can limit the current without sustaining damage; and configuring the controller to control the transistor to limit the current during operation in the current-limiting mode such that, for ranges of voltage across the transistor during operation in the current-limiting mode that lie below a threshold voltage, the respective periods of time are such that the transistor dissipates an amount of energy that is substantially the same for the ranges of voltage below the threshold voltage, and for ranges of voltage across the transistor during operations in the current-limiting mode that lie above the threshold voltage, the respective periods of time are such that the amount of energy dissipated by the transistor decreases as the range of voltage departs further from the threshold voltage.

12. The method according to claim 11, wherein the controller is configured to control the period of time for which the transistor limits the current during operation in the current-limiting mode to vary as
A/(B*V.sub.DS+C*max[V.sub.DS−V.sub.TH,0])+D, wherein V.sub.DS denotes a value of the voltage across the transistor during operation in the current-limiting mode, V.sub.TH is the threshold voltage and A, B, C and D are constants, and the values of A, B, C, D and V.sub.TH are selected during configuration of the controller such that, for all ranges of voltage dropped across the transistor during operation in the current-limiting mode, the controller controls the respective period of time for each range such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

13. The method according to claim 11, wherein: the controller is further arranged to monitor the voltage across the transistor during operation in the current-limiting mode, and operable in the current-limiting mode to control the transistor based on both the monitored current and the monitored voltage so as to limit the both the current through the transistor and power dissipated by the transistor; and configuring the controller to control the period of time for which the transistor limits the current during operation in the current-limiting mode to vary as
E/V.sub.DS+F, wherein V.sub.DS denotes a value of the voltage across the transistor during operation in the current-limiting mode, and E and F are constants, and the values of E and F are selected during configuration of the controller such that, for all ranges of voltage dropped across the transistor during operation in the current-limiting mode, the controller controls the respective period of time for each range such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

(2) FIG. 1 shows an example of a conventional current-limiting circuit forming part of a plug-in integrated circuit board;

(3) FIG. 2 illustrates the pulse energy capability of a typical MOSFET used in a current-limiting circuit;

(4) FIG. 3 illustrates the variations with drain-source voltage of the pulse energy dissipated by the MOSFET in cases where the MOSFET is controlled by different types of conventional current-limiting controller described herein, and also shows the MOSFET's pulse energy capability of FIG. 2, for comparison;

(5) FIG. 4 illustrates the variations with drain-source voltage of the pulse energy dissipated by a MOSFET in embodiments of the present invention, and also shows the MOSFET's pulse energy capability of FIG. 2, for comparison;

(6) FIG. 5 shows a plug-in board having a current-limiting circuit according to an embodiment of the present invention;

(7) FIG. 6 shows details of the current-limiting circuit of a first embodiment of the present invention;

(8) FIG. 7 shows details of the timing module in the current-limiting circuit of the first embodiment;

(9) FIG. 8 illustrates a method of configuring a current limiting circuit according to the first embodiment;

(10) FIG. 9 shows a variant of the current-limiting circuit of the first embodiment, which controls the current-limiting transistor based on calculated values of the transistor ON time;

(11) FIG. 10 is a schematic showing components of a programmable signal processing apparatus that can be configured to function as the timing module in the variant of the first embodiment;

(12) FIG. 11 illustrates a current-limiting circuit according to a second embodiment of the present invention; and

(13) FIG. 12 shows details of the timing module in the current-limiting circuit of the second embodiment.

DETAILED DESCRIPTION OF EMBODIMENTS

(14) [First Embodiment]

(15) FIG. 5 illustrates a current-limiting circuit 600 according to a first embodiment of the present invention, which, as in the background example of FIG. 1, is provided as part of a plug-in integrated circuit board 100 having a DC/DC converter module 400 and low-voltage circuitry 500 that are the same as those in FIG. 1. The description of these and other common components in FIGS. 1 and 5, which are labelled by like reference signs, will therefore not be repeated here. The following description will instead focus on the differences between the embodiments of the present invention and the background example of FIG. 1. It should be noted that a current-limiting circuit according to an embodiment of the present invention may be provided in a different kind of plug-in board than the one illustrated in FIG. 5, as part of the backplane circuitry, or as a stand-alone module that may be sold separately.

(16) FIG. 6 is a schematic illustration of the current-limiting circuit 600 of the present embodiment, wherein the controller 630 comprises a timing module 632 and a current-limiting transistor controller 634. The timing module 632 is arranged to communicate with the current-limiting transistor controller 634 so as to control a period of time for which the transistor Q1 limits the transistor current I.sub.DS during operation of the controller 630 in the current-limiting mode. Moreover, the timing module 632 is configured to control, based on at least one value of the voltage dropped across the transistor Q1 during operation in the current-limiting mode, the transistor ON time such that, for all ranges of voltage V.sub.DS that may be dropped across the transistor Q1 during operation in the current-limiting mode, the respective period of time for each range is such that the transistor Q1 dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

(17) In the present embodiment, the timing module 632 is arranged to sense the voltage across the series combination of the transistor Q1 and the current sense resistor R.sub.s, which is essentially the same as the voltage drop across the transistor Q1 owing to the value of R.sub.s being much smaller than the MOSFET channel resistance for any gate voltage used during current limitation in the present embodiment. The timing module 632 may alternatively be arranged to determine the voltage across transistor Q1 alone. In both cases, the voltage sensed by the timing module 632 is indicative of V.sub.DS (in other words, provides a measure of V.sub.DS).

(18) The timing module 632 may be physically implemented in various different ways. The timing module 632 may, as in the present embodiment, rely on the charging of a capacitor for its control of the transistor's ON time (t.sub.ON), and comprise a charging circuit arranged to charge the capacitor at a rate dependent on the voltage across the transistor Q1 during operation in the current-limiting mode, as well as a control signal generator that is arranged to generate a control signal to cause the controller to cease operating in the current-limiting mode when a voltage across the capacitor reaches a predetermined capacitor voltage threshold. In this case, the charging circuit is arranged to charge the capacitor such that the voltage across the capacitor reaches the predetermined capacitor voltage threshold in the period of time required for the transistor to dissipate substantially the maximum amount of energy that it is capable of dissipating without sustaining damage during operation in the current-limiting mode. A timing module of this kind may be implemented in various different ways, depending on how it is required to determine the transistor's ON time as a function of the voltage dropped across the transistor (Q1) during operation in the current-limiting mode. One example of such a timing module that is used in the present embodiment and has the advantage of being simple to fabricate with very few components, will be described in the following with reference to FIG. 7.

(19) In the present embodiment, the current-limiting transistor controller 634 is arranged to monitor I.sub.DS and is operable in the current-limiting mode to control the transistor Q1 based on the monitored current so as to limit the current flow through the transistor Q1, for the period of time controlled by the timing module 632. Thus, in contrast to the background example described above with reference to FIG. 1, the controller 630 of the present embodiment does not control the transistor Q1 to keep the power dissipated (i.e. the product I.sub.DS.Math.V.sub.DS) below a maximum permitted power, P.sub.max.

(20) Where the current-limiting transistor Q1 takes the form of a MOSFET, as in the present embodiment, or another type of transistor exhibiting similar pulse energy capability (e.g. an NPN transistor), then, owing to the shape of the pulse energy capability curve for these kinds of transistor, the timing module 632 is preferably configured to control the period of time for which the transistor Q1 limits the current during operation in the current-limiting mode such that, for ranges of V.sub.DS during operation in the current-limiting mode that lie below a threshold voltage, the respective periods of time are such that the transistor Q1 dissipates an amount of energy that is substantially the same for all of the ranges of voltage. Thus, the amount of energy dissipated for all values of V.sub.DS within the first voltage region shown in FIG. 2 is substantially the same as the maximum energy E.sub.max that the transistor Q1 is capable of dissipating without sustaining damage. Furthermore, for ranges of voltage across the transistor Q1 during operation in the current-limiting mode that lie above the threshold voltage (i.e. in the second region shown in FIG. 2), the respective periods of time are such that the amount of energy dissipated by the transistor Q1 decreases as the range of voltage departs further from the threshold voltage. In other words, for ranges of voltage across the transistor Q1 during operation in the current-limiting mode that lie above the threshold voltage, the timing module 632 is arranged to control the respective periods of time such that, the further a range of voltage is from the threshold voltage, the smaller the amount of energy dissipated by the transistor Q1. Thus, the amount of energy dissipated for all values of V.sub.DS within the second voltage region shown in FIG. 2 is also substantially the same as the maximum energy that the transistor Q1 is capable of dissipating without sustaining damage.

(21) By configuring the timing module 632 to operate in this way, the transistor Q1 is controlled to conduct the inrush current for the maximum period of time that it can without sustaining damage, regardless of the voltage that is dropped across it. This allows the transistor Q1 to be used to its full potential, thereby achieving the advantages set out above.

(22) In more detail, the timing module 632 may, as in the present embodiment, be arranged to control t.sub.ON to vary with V.sub.DS as follows:
t.sub.ON=A/(B*V.sub.DS+C*max[V.sub.DS−V.sub.TH,0])+D,  Eqn. 1
wherein V.sub.TH is the aforementioned threshold voltage (not to be confused with the MOSFET's gate threshold voltage), and A, B, C and D are constants (the constant offset D may be set equal to zero). The value of V.sub.DS in Eqn. 1 may, for example, be the initial value of V.sub.DS when the controller 630 starts operating in the current-limiting mode after detecting that the transistor current I.sub.DS exceeds the limit of I.sub.DSmax. The values of A, B, C, D and V.sub.TH are such that, for all ranges of voltage that may be dropped across the transistor Q1 during operation in the current-limiting mode, the timing module 632 controls the respective period of time for each range such that the transistor Q1 dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

(23) It is noted that the functional form of t.sub.ON(V.sub.DS) in Eqn. 1 is given by way of example only, and the timing module 632 may more generally control t.sub.ON in dependence on V.sub.DS in any other way such that, for all ranges of voltage V.sub.DS that may be dropped across the transistor Q1 during operation in the current-limiting mode, the respective period of time for each range is such that the transistor Q1 dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage. The form of t.sub.ON(V.sub.DS) given by Eqn. 1, however, has the advantage that it can be implemented in a simple timing module circuit having few components, as will now be explained.

(24) In the present embodiment, the timing module 632 takes the particularly simple form shown at 632-1 in FIG. 7, relying on the charging of a capacitor C.sub.T to control t.sub.ON, as noted above. Owing to the form of t.sub.ON(V.sub.DS) in the present embodiment (Eqn. 1), the timing module can be implemented as a simple circuit, comprising a charging circuit having resistors R.sub.1 and R.sub.2, a zener diode Z.sub.1, and a controlled current source 635. The charging current generated by the controlled current source 635 is equal to the sum of the currents flowing through resistors R.sub.1 and R.sub.2. In the present example, the charging circuit includes an op-amp circuit that works as a current mirror, sensing the current I.sub.TIMER through resistors R.sub.1 and R.sub.2 and charging the capacitor C.sub.T with this current.

(25) By the above-described arrangement, the timing module is able to provide accurate timing even where V.sub.DS changes during current limitation. The charging circuit is arranged to charge the capacitor C.sub.T at a rate that is dependent on the voltage across transistor Q1 during operation in the current-limiting mode. The timing module 632-1 also includes a control signal generator in the exemplary form of a comparator 636, which is arranged to generate a control signal to cause the current-limiting transistor controller 634 to stop operating in the current-limiting mode when a voltage across the capacitor C.sub.T reaches a predetermined capacitor voltage threshold. The capacitor voltage threshold is determined by the reference voltage V.sub.timeout that is applied to one of the amplifier's inputs, as shown in FIG. 7.

(26) The switch Sw1 is closed when the current-limiting transistor controller 634 is not operating in the current-limiting mode, and the switch Sw2 is open so that the capacitor C.sub.T cannot be charged. However, as soon as the current-limiting transistor controller 634 begins operating in the current-limiting mode, it generates switch control signals to open switch Sw1 and close switch Sw2 so as to allow the capacitor Cr to be charged by the controlled current source 635. Furthermore, once the voltage across the capacitor C.sub.T has reached the predetermined capacitor voltage threshold, switch Sw2 is opened and switch Sw1 is closed in order to reset (discharge) the capacitor C.sub.T. The discharge of C.sub.T may not happen instantaneously and, in particular, the rate of the discharge may be arranged to decrease with the temperature of the transistor Q1. For instance, it may happen that the controller goes into current limiting mode but leaves current limiting mode before the predetermined capacitor voltage threshold has been reached. In this case, it may be preferable to slowly discharge the capacitor C.sub.T (e.g. using a controlled current limiter connected to switch Sw1, as shown in FIG. 7) so that, if the controller enters current limiting mode again, the charging will not start from 0 V but from a higher level; in this case, the predetermined capacitor voltage threshold will be reached in less time, thus safeguarding the transistor Q1.

(27) In the present embodiment, the charging circuit is arranged to charge the capacitor C.sub.T such that the voltage across the capacitor C.sub.T reaches the predetermined capacitor voltage threshold in a period of time given by Eqn. 1 above. The required form of t.sub.ON(V.sub.DS) can be achieved by appropriately selecting the components in the charging circuit and the reference voltage V.sub.timeout applied to the comparator 636, as will now be explained.

(28) The voltage V.sub.CT across the capacitor C.sub.T may be expressed as follows:

(29) $V_{\mathrm{CT}}=\frac{1}{C_T}{\int }_0^{t_{\mathrm{ON}}}\left(\frac{V_{\mathrm{DS}}\left(t\right)}{R_2}+\frac{\max \left(V_{\mathrm{DS}}\left(t\right)-V_{\mathrm{TH}},0\right)}{R_1}\right)dt,$
where V.sub.TH is the threshold voltage of the zener diode Z.sub.1. The zener diode Z.sub.1 only conducts when the voltage across it is greater than V.sub.TH. For a fixed V.sub.DS (i.e. a V.sub.DS that does not vary with time), the primitive function can be calculated for the integral above as follows:

(30) $V_{\mathrm{CT}}=\frac{1}{C_T}{\int }_0^{t_{\mathrm{ON}}}\left(\frac{V_{\mathrm{DS}}}{R_2}+\frac{\max \left(V_{\mathrm{DS}}-V_{\mathrm{TH}},0\right)}{R_1}\right)dt.Math.V_{\mathrm{CT}}=\frac{1}{C_T}\left(\frac{V_{\mathrm{DS}}}{R_2}+\frac{\max \left(V_{\mathrm{DS}}-V_{\mathrm{TH}},0\right)}{R_1}\right)t_{\mathrm{ON}}$

(31) As V.sub.CT is equal to V.sub.timeout when the ON time has elapsed,

(32) $V_{\mathrm{timeout}}=\frac{1}{C_T}\left(\frac{V_{\mathrm{DS}}}{R_2}+\frac{\max \left(V_{\mathrm{DS}}-V_{\mathrm{TH}},0\right)}{R_1}\right)t_{\mathrm{ON}}.Math.t_{\mathrm{ON}}=\frac{V_{\mathrm{timeout}}{C}_T}{\frac{V_{\mathrm{DS}}}{R_2}+\frac{\max \left(V_{\mathrm{DS}}-V_{\mathrm{TH}},0\right)}{R_1}}$

(33) Thus, in this example, the constants in Eqn. 1 are as follows: A=V.sub.timeoutC.sub.T, B=1/R.sub.2, C=1/R.sub.1 and D=0.

(34) In the present example, the current limit to be enforced by the controller, I.sub.LIM, is set at 15 A. The zener voltage, V.sub.TH, of zener diode Z.sub.1 should be chosen to be the same as the voltage at which the knee occurs in the pulse energy capability diagram. From FIG. 2, V.sub.TH=40 V, and the energy pulse capability in voltage region 1, E.sub.VR1, is 900 mJ. When operating in voltage region 1, V.sub.DS*I.sub.LIM*t.sub.ON=E.sub.VR1. From the above,

(35) $\begin{array}{cc}{V}_{\mathrm{timeout}}=\frac{1}{C_T}\left(\frac{V_{\mathrm{DS}}}{R_2}+\frac{\max \left(V_{\mathrm{DS}}-V_{\mathrm{TH}},0\right)}{R_1}\right)t_{\mathrm{ON}}& \mathrm{Eqn}.2\end{array}$

(36) As V.sub.DS<V.sub.TH in voltage region 1,

(37) $\begin{array}{cc}{V}_{\mathrm{timeout}}=\frac{1}{C_T}\frac{V_{\mathrm{DS}}}{R_2}{t}_{\mathrm{ON}}& \mathrm{Eqn}.3\end{array}$

(38) As V.sub.DSI.sub.LIMt.sub.ON=E.sub.VR1, it follows from Eqn. 3 that V.sub.timeout can be expressed as follows:

(39) $V_{\mathrm{timeout}}=\frac{1}{C_T}\frac{V_{\mathrm{DS}}}{R_2}\frac{E_{\mathrm{VR}1}}{V_{\mathrm{DS}}{I}_{\mathrm{LIM}}}=\frac{1}{C_T}\frac{1}{R_2}\frac{E_{\mathrm{VR}1}}{I_{\mathrm{LIM}}}$

(40) Taking V.sub.timeout=4 V and C.sub.T=10 nF as typical values,

(41) $V_{\mathrm{timeout}}=\frac{1}{C_T}\frac{1}{R_2}\frac{E_{\mathrm{VR}1}}{I_{\mathrm{LIM}}}.Math.R_2=\frac{1}{C_T{V}_{\mathrm{timeout}}}\frac{E_{\mathrm{VR}1}}{I_{\mathrm{LIM}}}$

(42) Using the above values for C.sub.T, V.sub.timeout, E.sub.VR1 and I.sub.LIM, R.sub.2 is 1.5 MΩ. To determine R.sub.1, the maximum permissible value of V.sub.DS (typically the maximum input voltage to the circuit) needs to be determined. In the present example, it is assumed that the maximum permissible value of V.sub.DS, V.sub.DSMAX, is 75 V. From FIG. 2, the corresponding maximum pulse energy, E.sub.VDSMAX (given by V.sub.DSMAX*I.sub.LIM*t.sub.ON) is about 425 mJ. Evaluating Eqn. 2 at V.sub.DS=V.sub.DSMAX leads to the following expression for V.sub.timeout:

(43) $\begin{array}{cc}{V}_{\mathrm{timeout}}=\frac{1}{C_T}\left(\frac{V_{\mathrm{DSMAX}}}{R_2}+\frac{V_{\mathrm{DSMAX}}-V_{\mathrm{TH}}}{R_1}\right)t_{\mathrm{ON}}& \mathrm{Eqn}.4\end{array}$

(44) As V.sub.DSMAXI.sub.LIMt.sub.ON=E.sub.VDSMAX, the transistor ON time, t.sub.ON, may be expressed as E.sub.VDSMAX/(V.sub.DSMAXI.sub.LIM). Inserting this expression for t.sub.ON into Eqn. 4, the value of R.sub.1 may be obtained as follows:

(45) $R_1=\frac{V_{\mathrm{DSMAX}}-V_{\mathrm{TH}}}{V_{\mathrm{timeout}}{C}_T\frac{V_{\mathrm{DSMAX}}{I}_{\mathrm{LIM}}}{E_{\mathrm{VDSMAX}}}-\frac{V_{\mathrm{DSMAX}}}{R_2}}.Math.R_1=626k\Omega$

(46) The controller 630 of the present embodiment may be configured using a configuration method that will now be described with reference to FIG. 8.

(47) In step S10, it is determined, for all ranges of voltage that may be dropped across the transistor Q1 during operation in the current-limiting mode, a respective period of time for each range, for which period of time the transistor Q1 can limit the current while dissipating substantially the maximum amount of energy that it is capable of dissipating without sustaining damage. This could be done, for example, by applying a plurality of input voltages V.sub.B to the plug-in board 100, and determining the maximum possible transistor ON time (i.e. the longest period of time for which the transistor Q1 can perform the current limitation without sustaining damage) for each of these input voltages. The transistor ON time for other values of the initially applied input voltage may be obtained by extrapolating between the experimentally determined values of the maximum ON time, if necessary or desirable.

(48) In step S20, the controller 630 is configured to control the transistor Q1 to limit the current Ins during operation in the current-limiting mode such that, for all ranges of voltage that may be dropped across the transistor Q1 during operation in the current-limiting mode, the transistor Q1 is controlled to limit the current for the respective determined period of time in each of the voltage ranges. In the present embodiment, this can be done by appropriately selecting the components in the charging circuit and the reference voltage V.sub.timeout applied to the comparator 636 of timing module 632-1.

(49) [Variant of the First Embodiment]

(50) In the first embodiment of the invention described above, the timing module 632 is provided in the form of a simple circuit 632-1, which relies on the charging of a capacitor to determine t.sub.ON. However, the timing module 632 may alternatively be implemented by appropriately configuring a digital signal processing apparatus to calculate t.sub.ON as a function of V.sub.DS. Thus, the timing module 632 may alternatively comprise a calculator that is arranged to calculate, using a function of V.sub.DS during operation in the current-limiting mode and of one or more parameters, the period of time for which the transistor limits the current during operation in the current-limiting mode, as well as a control signal generator arranged to generate a control signal to cause the controller to cease operating in the current-limiting mode when the calculated period of time elapses. In this case, the one or more parameters are such that, for all ranges of voltage that may be dropped across the transistor during operation in the current-limiting mode, the timing module is arranged to control the respective period of time for each range such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage. A variant of the first embodiment that employs a timing module of this general kind will now be described with reference to FIGS. 9 and 10.

(51) FIG. 9 shows a variant of the first embodiment, comprising a timing module 632-2 that has a voltage monitor 637, an ON time calculator 638, and a control signal generator 639, as well as other components that are the same as in the first embodiment and labelled with like reference signs. The voltage monitor 637 is arranged to monitor the voltage across the transistor Q1 and determine an initial value of the voltage, V.sub.DSi, which is dropped across the transistor during operation in the current-limiting mode. This could be done by performing a measurement of V.sub.DS as soon as the controller begins current limitation, or by averaging two or more values of V.sub.DS that are measured in succession immediately after current limitation has begun. In this variant, the ON time calculator 638 is arranged to calculate the period of time (t.sub.ON) for which the transistor Q1 limits the current during operation in the current-limiting mode according to Eqn. 1, using the determined value of V.sub.DSi. As in the embodiment, the values of A, B, C, D and V.sub.TH are such that, for all ranges of voltage that may be dropped across the transistor Q1 during operation in the current-limiting mode, the timing module 632-2 controls the respective period of time for each range such that the transistor Q1 dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

(52) The timing module 632-2 of the above-described variant of the first embodiment may, for example, be implemented in programmable signal processing apparatus 800 as shown in FIG. 10. The programmable signal processing apparatus 800 comprises a processor 810, a working memory 820 and an instruction store 830 storing computer-readable instructions which, when executed by the processor 810, cause the processor 810 to perform the above-described processing operations to generate control signals that cause the current-limiting transistor controller 634 to stop operating in the current-limiting mode. The instruction store 830 also stores the values of A, B, C, D and V.sub.TH that are used to calculate t.sub.ON. The programmable signal processing apparatus 800 also includes an input/output (I/O) module 840 which operates to transmit the generated control signals to the current-limiting transistor controller 634. The instruction store 830 may comprise a ROM pre-loaded with the computer-readable instructions and parameter values. Alternatively, the instruction store 830 may comprise a RAM or similar type of memory, and the computer-readable instructions and parameters can be input thereto from a computer program product, such as a non-transitory computer-readable storage medium 850 such as a CD-ROM, etc. or a computer-readable signal 860 carrying the computer-readable instructions.

(53) A method similar to that described above with reference to FIG. 8 may be used to configure the controller of this variant of the first embodiment. However, in this case, the controller 630 would be configured (in a step analogous to step S20 of FIG. 8) to control the transistor Q1 in the manner described above by selecting appropriate values of A, B, C, D and V.sub.TH (i.e. such that, for all ranges of voltage that may be dropped across the transistor during operation in the current-limiting mode, the controller 630 controls the respective period of time for each range such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage), and storing the selected values in the instruction store 830.

(54) [Second Embodiment]

(55) A current-limiting circuit according to a second embodiment of the invention is illustrated in FIG. 11. The current-limiting circuit 700 of the present embodiment comprises a controller 730 having a timing module 732, and a current-limiting and power-limiting transistor controller 734.

(56) The timing module 732 is arranged to communicate with controller 734 so as to control a period of time for which the transistor Q1 limits the transistor current I.sub.DS during operation of the controller 730 in the current-limiting mode. Moreover, the timing module 732 is configured to control, based on at least one value of the voltage dropped across the transistor Q1 during operation in the current-limiting mode, the transistor ON time such that, for all ranges of voltage V.sub.DS that may be dropped across the transistor Q1 during operation in the current-limiting mode, the respective period of time for each range is such that the transistor Q1 dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

(57) As in the first embodiment, the timing module 732 is arranged to sense the voltage across the series combination of the transistor Q1 and the current sense resistor R.sub.s, which is essentially the same as the voltage drop across the transistor Q1 owing to the value of R.sub.s being much smaller than the MOSFET channel resistance for any gate voltage used during current limitation in the present embodiment. The timing module 732 may alternatively be arranged to determine the voltage across transistor Q1 alone. In both cases, the voltage sensed by the timing module 732 is indicative of V.sub.DS (in other words, provides a measure of V.sub.DS).

(58) The timing module 732 may, as in the present embodiment, rely on the charging of a capacitor for its control of the transistor's ON time (t.sub.ON), and comprise a charging circuit arranged to charge the capacitor at a rate dependent on the voltage across the transistor Q1 during operation in the current-limiting mode, as well as a control signal generator that is arranged to generate a control signal to cause the controller to cease operating in the current-limiting mode when a voltage across the capacitor reaches a predetermined capacitor voltage threshold. In this case, the charging circuit is arranged to charge the capacitor such that the voltage across the capacitor reaches the predetermined capacitor voltage threshold in the period of time required for the transistor to dissipate substantially the maximum amount of energy that it is capable of dissipating without sustaining damage during operation in the current-limiting mode. A timing module of this kind may be implemented in various different ways, depending on how it is required to determine the transistor's ON time as a function of the voltage dropped across the transistor Q1 during operation in the current-limiting mode. One example of such a timing module that is used in the present embodiment and has the advantage of being simple to fabricate with very few components, will be described in the following with reference to FIG. 12.

(59) In the present embodiment, the current-limiting and power-limiting transistor controller 734 is arranged to monitor I.sub.DS and is operable in the current-limiting mode to control the transistor Q1 based on the monitored current so as to limit the current flow through the transistor Q1, for the period of time controlled by the timing module 732. In addition, the controller 734 is arranged to control the transistor Q1 to keep the power dissipated (i.e. the product I.sub.DS.Math.V.sub.DS) below a maximum permitted power, P.sub.max. Thus, the controller 734 is operable in the current-limiting mode to control the transistor Q1 based on both the monitored current I.sub.DS and the monitored voltage V.sub.DS so as to limit both the current through the transistor Q1 and the power dissipated by the transistor Q1.

(60) Where the current-limiting transistor Q1 takes the form of a MOSFET, as in the present embodiment, or another type of transistor exhibiting similar pulse energy capability, then, owing to the shape of the pulse energy capability curve for these kinds of transistor, the timing module 732 is preferably configured to control the period of time for which the transistor Q1 limits the current during operation in the current-limiting mode such that, for ranges of V.sub.DS during operation in the current-limiting mode that lie below a threshold voltage, the respective periods of time are such that the transistor Q1 dissipates an amount of energy that is substantially the same for all of the ranges of voltage. Thus, the amount of energy dissipated for all values of V.sub.DS within the first voltage region shown in FIG. 2 is substantially the same as the maximum energy E.sub.max that the transistor Q1 is capable of dissipating without sustaining damage. Furthermore, for ranges of voltage across the transistor Q1 during operation in the current-limiting mode that lie above the threshold voltage (i.e. in the second region shown in FIG. 2), the respective periods of time are such that, the further a range of voltage is from the threshold voltage, the smaller the amount of energy dissipated by the transistor Q1. Thus, the amount of energy dissipated for all values of V.sub.DS within the second voltage region shown in FIG. 2 is also substantially the same as the maximum energy that the transistor Q1 is capable of dissipating without sustaining damage. By configuring the timing module 732 to operate in this way, the transistor Q1 is controlled to conduct the inrush current for the maximum period of time that it can without sustaining damage, regardless of the voltage that is dropped across it. This allows the transistor Q1 to be used to its full potential, thereby achieving the advantages set out above.

(61) In more detail, the timing module 732 may, as in the present embodiment, be arranged to control to.sub.ON to vary with V.sub.DS as follows:
t.sub.ON=E/V.sub.DS+F,  Eqn. 5
wherein E and F are constants (the offset F may be set equal to zero). The value of V.sub.DS in Eqn. 5 may, for example, be the initial value of V.sub.DS when the controller 730 starts operating in the current-limiting mode after detecting that the transistor current I.sub.DS exceeds the limit of I.sub.DSmax. The values of E and F are such that, for all ranges of voltage that may be dropped across the transistor Q1 during operation in the current-limiting mode, the timing module 732 controls the respective period of time for each range such that the transistor Q1 dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

(62) In the present embodiment, the timing module 732 takes the particularly simple form shown at 732-1 in FIG. 12, relying on the charging of a capacitor C.sub.T to control t.sub.ON, as noted above. Owing to the form of t.sub.ON(V.sub.DS) in the present embodiment (Eqn. 5), the timing module can be implemented in a particularly simple circuit, comprising a charging circuit having a resistor R.sub.1 and a controlled current source 735. The charging current generated by the controlled current source 735 is equal to the current I.sub.TIMER flowing through resistor R.sub.1. In the present example, the charging circuit includes an op-amp circuit that works as a current mirror, sensing the current through resistor R.sub.1 and charging the capacitor C.sub.T with this current.

(63) By the above-described arrangement, the timing module is able to provide accurate timing even where V.sub.DS changes during current limitation. The charging circuit is arranged to charge the capacitor C.sub.T at a rate that is dependent on the voltage across transistor Q1 during operation in the current-limiting mode. The timing module 732-1 also includes a control signal generator in the exemplary form of a comparator 636, which is the same as in the first embodiment. The switches Sw1 and Sw2 are controlled by the current-limiting and power-limiting transistor controller 734 to operate in the same manner as in the first embodiment.

(64) In the present embodiment, the charging circuit is arranged to charge the capacitor C.sub.T such that the voltage across the capacitor C.sub.T reaches the predetermined capacitor voltage threshold in a period of time given by Eqn. 5 above. The required form of t.sub.ON(V.sub.DS) can be achieved by appropriately selecting the components in the charging circuit and the reference voltage V.sub.timeout applied to the comparator 636, as will now be explained.

(65) The voltage V.sub.CT across the capacitor C.sub.T may be expressed as follows:

(66) 0$V_{\mathrm{CT}}=\frac{1}{C_T}{\int }_0^{t_{\mathrm{ON}}}\frac{V_{\mathrm{DS}}\left(t\right)}{R_1}dt$

(67) For a fixed V.sub.DS that does not vary with time during operation in the current limiting mode, the V.sub.CT can be expressed as follows:

(68) $V_{\mathrm{CT}}=\frac{1}{C_T}{\int }_0^{t_{\mathrm{ON}}}\frac{V_{\mathrm{DS}}\left(t\right)}{R_1}dt=\frac{1}{C_T}\frac{V_{\mathrm{DS}}}{R_1}{t}_{\mathrm{ON}}$

(69) As V.sub.CT is equal to V.sub.timeout when the ON time has elapsed,

(70) $V_{\mathrm{timeout}}=\frac{1}{C_T}\frac{V_{\mathrm{DS}}}{R_1}{t}_{\mathrm{ON}}.Math.t_{\mathrm{ON}}=V_{\mathrm{timeout}}{C}_T{R}_1\frac{1}{V_{\mathrm{DS}}}$

(71) Thus, in this example, t.sub.ON(V.sub.DS) takes the form of Eqn. 5, with E=V.sub.timoutC.sub.TR.sub.1 and F=0.

(72) In the present example, the current limit to be enforced by the current-limiting and power-limiting transistor controller 734, I.sub.LIM, is set at 15 A. From FIG. 2, the pulse energy capability of the transistor Q1 in voltage region 1, E.sub.VR1, is 900 mJ. When operating in voltage region 1, V.sub.DS*I.sub.LIM*t.sub.ON=E.sub.VR1, and we have

(73) $t_{\mathrm{ON}}=V_{\mathrm{timeout}}{C}_T{R}_1\frac{1}{V_{\mathrm{DS}}}$$V_{\mathrm{DS}}{I}_{\mathrm{LIM}}{t}_{\mathrm{ON}}=E_{\mathrm{VR}1}.Math.t_{\mathrm{ON}}=\frac{E_{\mathrm{VR}1}}{V_{\mathrm{DS}}{I}_{\mathrm{LIM}}}$$\mathrm{insert}\mathrm{above}$$\frac{E_{\mathrm{VR}1}}{V_{\mathrm{DS}}{I}_{\mathrm{LIM}}}=V_{\mathrm{timeout}}{C}_T{R}_1\frac{1}{V_{\mathrm{DS}}}.Math.R_1=\frac{E_{\mathrm{VR}1}}{I_{\mathrm{LIM}}}\frac{1}{V_{\mathrm{timeout}}{C}_T}.Math.R_1=1.5M\Omega$

(74) To determine the power limit, P.sub.LIM, that is to be enforced by the current-limiting and power-limiting transistor controller 734, the maximum permissible V.sub.DS (typically the maximum input voltage to the circuit), V.sub.DSMAX, is taken to be 75 V in the present example. FIG. 2 yields E.sub.VDSMAX=425 mJ. As P.sub.LIM*t.sub.ON=E.sub.VDSMAX, and as R.sub.1 has been determined, P.sub.LIM can be derived as follows:

(75) $t_{\mathrm{ON}}=V_{\mathrm{timeout}}{C}_T{R}_1\frac{1}{V_{\mathrm{DSMAX}}}$$\mathrm{insert}\mathrm{in}$$P_{\mathrm{LIM}}{t}_{\mathrm{ON}}=E_{\mathrm{VDSMAX}}$$\mathrm{and}\mathrm{we}\mathrm{get}$$P_{\mathrm{LIM}}{V}_{\mathrm{timeout}}{C}_T{R}_1\frac{1}{V_{\mathrm{DSMAX}}}=E_{\mathrm{VDSMAX}}.Math.P_{\mathrm{LIM}}=\frac{E_{\mathrm{VDSMAX}}{V}_{\mathrm{DSMAX}}}{V_{\mathrm{timeout}}{C}_T{R}_1}.Math.P_{\mathrm{LIM}}=531W$

(76) The controller 730 of the present embodiment may be configured using the configuration method that has been described above with reference to FIG. 8.

(77) [Variant of the Second Embodiment]

(78) In the second embodiment described above, the timing module 732 is provided in the form of a simple circuit 732-1, which relies on the charging of a capacitor to determine t.sub.ON. However, the timing module 732 may alternatively be implemented by appropriately configuring a digital signal processing apparatus to calculate t.sub.ON as a function of V.sub.DS. Thus, the timing module 732 may alternatively comprise a calculator that is arranged to calculate, using a function of V.sub.DS during operation in the current-limiting mode and of one or more parameters, the period of time for which the transistor limits the current during operation in the current-limiting mode, as well as a control signal generator arranged to generate a control signal to cause the controller to cease operating in the current-limiting mode when the calculated period of time elapses. In this case, the one or more parameters are such that, for all ranges of voltage that may be dropped across the transistor during operation in the current-limiting mode, the timing module is arranged to control the respective period of time for each range such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage.

(79) Thus, a variant of the second embodiment may comprise a timing module having a voltage monitor and a control signal generator that are the same as those described above with reference to FIGS. 9 and 10. However, in contrast to the example of FIGS. 9 and 10, the ON time calculator of the present variant is arranged to calculate the period of time for which the transistor limits the current during operation in the current-limiting mode according to Eqn. 5.

(80) The controller 730 of the present embodiment may be configured using a configuration method similar to that described above in connection with the variant of the first embodiment. However, in the present case, the controller 730 would be configured (in a step analogous to step S20 of FIG. 8) to control the transistor Q1 in the manner described above by selecting appropriate values of E and F (i.e. such that, for all ranges of voltage that may be dropped across the transistor during operation in the current-limiting mode, the controller 730 controls the respective period of time for each range such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage), and storing the selected values in the instruction store 830.

(81) [Modifications]

(82) Many modifications can be made to the embodiments, without departing from the scope of the present invention.

(83) For example, the current-limiting circuits of the above embodiments and variants are configured to control the ON time of the current-limiting transistor to dissipate substantially the maximum amount of energy that it is capable of dissipating without sustaining damage at a given transistor temperature (e.g. 25° C.). These embodiments could, however, be modified to allow for near-optimal control of the transistor's ON time not only at a single temperature but over a range of temperatures in which the current-limiting circuit is to be used. Thus, the current-limiting circuit may further comprise a temperature sensor arranged to measure a temperature of the transistor Q1. In this case, for all ranges of voltage that may be dropped across the transistor Q1 during operation in the current-limiting mode, the controller would be arranged to control, based on the temperature measured by the temperature sensor, the respective period of time for each range such that the transistor dissipates substantially the maximum amount of energy that it is capable of dissipating without sustaining damage. For example, where the controller is implemented in the form of a digital signal processor (DSP) as in the above-described variants of the embodiments, the ON time calculator may store a respective set of one or more parameters for each of several different temperature ranges, and be arranged to select a set of parameter(s) for use in calculating t.sub.ON in dependence on the temperature measured by the temperature sensor.

(84) Furthermore, although the digital signal processing apparatus of the above-described variants comprises an ON time calculator for calculating the period of time for which the transistor Q1 limits the current during operation in the current-limiting mode, the digital signal processing apparatus may alternatively be configured to mimic the operation of the timing module of the embodiments. More specifically, in a further variant, a microcontroller with an analog-to-digital converter (ADC) could be used to implement the control. The microcontroller may sample V.sub.DS via the ADC at regular interval. When operation in the current-limiting mode begins, the program run by the microcontroller could start accumulating values of a function g(V.sub.DS):

(85) $C_{\mathrm{TIMEOUT}}<\underset{n=0}{\overset{m}{.Math.}}g\left(V_{\mathrm{DS}}\right)$

(86) When the accumulated value reaches a level C.sub.TIMEOUT, the transistor Q1 is turned off. The weighting function g could be A*V.sub.DS+B*max(V.sub.DS−V.sub.TH,0) in a variant of the first embodiment, yielding an on-time proportional to 1/(A*V.sub.DS+B*max(V.sub.DS−V.sub.TH, 0)). Alternatively, in a variant of the second embodiment, it could be a constant times V.sub.DS, yielding an on-time proportional to 1/V.sub.DS. Any other function that matches the transistor's pulse capability curve (e.g. as shown in FIG. 2) could alternatively be used.

(87) The foregoing description of embodiments of the present invention has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the invention to the present form disclosed. Alterations, modifications and variations can be made without departing from the spirit and scope of the present invention.