Amplifier output power limiting circuitry

Abstract

An amplifier system having: an amplifier having a linear operating region where an output signal produced by the amplifier at the output terminal has a power level increasing proportionally with the increasing input signal power level up to a compression region of the amplifier where the output power is inhibited from increasing with increasing input signal power; and a DC current limiting circuit, coupled between a DC power supply and the amplifier, to: supply DC current from the DC power supply that is equal to quiescent current to the amplifier from the DC power supply when the amplifier operates in the linear region; enable the amplifier to draw increasing DC current from the DC power supply above the quiescent current with increasing input signal power until the output signal power reaches the desired compression point level which is lower than that of a stand-alone amplifier without the DC current limiting circuit; and, then limits the current drawn by the amplifier from the DC power supply.

Claims

1. An amplifier system, comprising: an amplifier having a linear operating region where an output signal produced by the amplifier at the output terminal has a power level increasing proportionally with the increasing input signal power level up to a compression region of the amplifier, and a limiter circuit, coupled between a DC power supply and the amplifier, to: supply a current equal to the quiescent current to the amplifier from the DC power supply when the amplifier operates in the linear region; enable the amplifier to draw increasing current from the DC power supply above the quiescent current with increasing input signal power until the input signal power reaches the compression point level; and, then limits the current drawn by the amplifier from the DC power supply.

2. The system recited in claim 1 wherein when the amplifier operates in the linear region, the limiter circuit is in a low resistance state; and wherein when the limiter limits the current drawn by the amplifier from the DC power supply, the limiter is in a high resistance state.

3. A system, having an input terminal and an output terminal, comprising: an amplifier connected to the input terminal for receiving an input signal at the input terminal and for producing an output signal at the output terminal, the amplifier having a linear operating region where an output signal produced by the amplifier at the output terminal has a power level increasing proportionally with the increasing input signal power level and a compression operating region where the output signal power produced by the amplifier has a compression power level, P.sub.out.sub._.sub.cmpr, invariant with the input signal power level when the power of the input signal is above a predetermined input power level; a DC current limiting circuit, coupled between a DC power supply and a bias terminal of the amplifier, for biasing the amplifier to limit the output power at the output terminal of the system to a level below the compression power level P.sub.out.sub._.sub.cmpr while enabling the output power of the system to vary proportionally with input signal power when the input signal power level is below the predetermined power level; and wherein the DC current limiting circuit: allows the amplifier to draw current from the DC power supply through the DC current limiting circuit having a first, substantially constant, level for a first range of input signal power level; allows the current drawn from the DC power supply through the DC current limiting circuit to increase from the first substantially constant level to a second, higher, level for a range of input power level greater than the first range of input signal power level; and, inhibits the current being drawn from the DC power supply through the DC bias limiting circuit current from increasing above the second level for a third range of input signal power level greater than the second range of input signal power level.

4. A circuit, comprising an amplifier having: an input terminal for receiving an input signal, an output terminal for producing an output signal; and a current supply terminal for receiving a bias current, the amplifier having a linear operating region and a compression region, the operating region of the amplifier being a function of the input signal and DC bias, the amplifier amplifying the input signal to produce the output signal; a non-linear circuit coupled between a DC voltage supply and the current supply terminal, the DC voltage supply providing a current to the amplifier through the non-linear circuit, the current producing a voltage (ΔV) across the non-linear circuit, such voltage (ΔV) being a function of the input signal, the non-linear circuit operating in an ohmic region when (ΔV) has a first level, operating in a saturation region when (ΔV) has a second level greater than then first level, or operating in a transition region between the ohmic region and the saturation region when (ΔV) has a third level greater than the first level and lower than the second level, the non-linear circuit operating in the ohmic region when the input signal operates the amplifier in the linear region of the amplifier and the non-linear circuit operating in the saturation region when the input signal operates the amplifier in the in the compression region of the amplifier.

5. The amplifier system recited in claim 1 wherein the limiter comprises a Nonlinear Mesa Resistor (NMR) semiconductor device.

6. The amplifier system recited in claim 1 wherein the limiter comprises a Field Effect Transistor with Connected Gate and Source Electrodes.

7. A system, having an input terminal and an output terminal, comprising: an amplifier connected to the input terminal for receiving an input signal at the input terminal and for producing an output signal at the output terminal, the amplifier having a linear operating region wherein the amplifier operates in accordance with the superposition principle and a compression operating region where the output signal power produced by the amplifier has a compression power level, P.sub.out.sub._.sub.cmpr, invariant with the input signal power level when the power of the input signal is above a predetermined input power level; and a DC current limiting circuit, coupled between a DC power supply and a bias terminal of the amplifier, for biasing the amplifier to limit the maximum output power at the output terminal of the system to a level below the compression power level P.sub.out.sub._.sub.cmpr.

Description

DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a diagram of a FET amplifier according to the PRIOR ART;

(2) FIG. 2 is a diagram of a FET amplifier system according to the PRIOR ART

(3) FIG. 3 is a diagram of a FET amplifier system according to the PRIOR ART;

(4) FIG. 4 is a diagram of a FET amplifier system according to the PRIOR ART;

(5) FIG. 5 is a diagram of a FET amplifier according to the disclosure;

(6) FIG. 6 is a set of curves showing the relationship between input power P.sub.in and output power P.sub.out for the FET amplifier of FIG. 1 (indicated by curve A), for the FET amplifier system of FIG. 2 (indicated by curve B), and the FET amplifier system of FIG. 5 (indicated by curve C);

(7) FIG. 7 is a set of curves showing the relationship between input power P.sub.in and current from a POWER_SUPPLY 2 to the FET amplifier of FIG. 1 (indicated by curve A), to the FET amplifier system of FIG. 2 (indicated by curve B), and to the FET amplifier system of FIG. 5 (indicated by curve C);

(8) FIG. 8 is a set of curves showing the relationship between input power P.sub.in and a voltage produced at the drain of the FET amplifier of FIG. 1 (indicated by curve A), at the drain of the FET amplifier system of FIG. 2 (indicated by curve B), and at the drain of the FET amplifier system of FIG. 5 (indicated by curve C);

(9) FIG. 9 is a top view of a structure, Nonlinear Mesa Resistor (NMR), used as a DC current limiting circuit used in the FET amplifier system of FIG. 5, such structure having relationship between voltage across it and current through it with two distinct regions: first where the current and the voltage are proportional and second where the current is independent of the voltage according to the disclosure;

(10) FIG. 10 is a curve showing the relationship between a voltage (V.sub.dc2−V.sub.dd) across the a DC current limiting circuit of FIG. 9 and current drawn by the FET amplifier of FIG. 5, such voltage being produced by the current passing from a POWER_SUPPLY 2 for the amplifier through a DC current limiting circuit of FIG. 9 coupled between the POWER_SUPPLY 2 and the drain of the FET amplifier of FIG. 5;

(11) FIG. 11 is a pair of curves, one of the curves, labeled curve C, showing the relationship between a voltage produced across the DC biasing circuit of the PET amplifier of FIG. 5 and current drawn by the FET amplifier of FIG. 5 over the operating range of the FET amplifier of FIG. 5 and a second one of the pair of curves, labeled B showing the relationship between a voltage produced across the constant current source of the FET amplifier system of FIG. 4 over the operating range of the FET amplifier system of FIG. 4;

(12) FIGS. 12A and 12B is a set of curves, produced from computer simulations, showing the relationships between compressed output power vs. input signal frequency (FIG. 12A) and 3.sup.rd order output intercept point (OIP3) vs. input signal frequency (FIG. 12B) for the FET amplifier of FIG. 1 (indicated by curve A), for the FET amplifier system of FIG. 2 (indicated by curve B), and two curves for the FET amplifier system with NMR of FIG. 9 (indicated by curves C1 and C2 representing two different NMR configurations.

(13) FIG. 13 are a set of curves useful in understanding the effect of the DC current limiting circuit used in the FET amplifier system of FIG. 5;

(14) FIG. 14 is a top view of a structure used as the DC current limiting circuit in the FET amplifier system of FIG. 5, such structure having relationship between voltage across it and current through it with two distinct regions: first where the current and the voltage are proportional and second where the current is independent of the voltage according another embodiment of the disclosure;

(15) FIG. 15 is a curve showing the relationship between a voltage (V.sub.dc2−V.sub.dd) across the DC current limiting of FIG. 14 and current drawn by the FET amplifier of FIG. 5, such voltage being produced by the current passing from a POWER_SUPPLY 2 for the amplifier through the DC current limiting circuit of FIG. 14 coupled between the POWER_SUPPLY 2 and the drain of the FET amplifier of FIG. 5;

(16) FIG. 16 is a pair of curves, one of the curves, labeled curve C, showing the relationship between a voltage produced across the DC current limiting circuit of the FET amplifier of FIG. 5 and current drawn by the FET amplifier of FIG. 5 over the operating range of the FET amplifier of FIG. 5 and a second one of the pair of curves, labeled B showing the relationship between a voltage produced across the constant current source of the FET amplifier system of FIG. 4 over the operating range of the FET amplifier system of FIG. 4.

DETAILED DESCRIPTION

(17) Referring now to FIG. 5, an amplifier system 10 is shown. Here, in this example, the amplifier system includes FET amplifier 12 having a FET with a grounded source (S). The system 10 includes a DC POWER SUPPLY 1, producing a voltage Vdc1, coupled to the gate (G) of the FET amplifier 12 and a DC POWER SUPPLY 2 producing a voltage Vdc2. The amplifier system 12 includes a DC current limiting circuit 14 coupled between the FET amplifier 12 and the DC POWER SUPPLY 2, as indicated, producing a voltage Vdd at the drain terminal of the amplifier 12 and passing a current, Idd, to the drain of the FET in a manner to be described in more detail in connection with FIG. 10. It is noted that while here both the amplifier 12 and the DC current limiter 14 are on the same integrated circuit CHIP, it should be understood that the amplifier 12 and limiter circuit 14 may be on separate, electrically interconnected, integrated circuit chips. An input signal, here in this example an RF input signal, is fed to an input terminal 16 of the amplifier system 10 and AC coupled to the gate (G) of the FET amplifier 12. The amplified input signal is produced as an output signal at the drain and is AC coupled to an output terminal 18 of the amplifier system 10, as indicated. The DC POWER SUPPLY 1 supplies a gate bias voltage Vdc1=Vgg to the gate and a DC bias current Igg to the gate of the FET amplifier 12. The DC POWER SUPPLY 2 supplies a voltage Vdd to the FET amplifier 12 through DC current limiting circuit 14. The details of the DC current limiting circuit 14 will be described below, suffice it to say here that current Idd supplied to the FET amplifier 14 from the DC POWER SUPPLY 2 stays constant and equal to the quiescent current I.sub.Q while the amplifier is in the linear region and increases from the quiescent current I.sub.Q with increasing input signal power to a maximum current level I.sub.LIMIT.sub._.sub.C as indicated by curve C in FIG. 7 while the amplifier is in the non-linear region. Further, the current Idd produces a voltage drop, ΔV=V.sub.NR,q=(Vdc2−Vdd) across the DC current limiting circuit 14, where Vdd is the voltage at the drain of the FET amplifier 12 (where Vdc2>Vdd) and that the relationship between the input signal power Pin and the voltage Vdd is shown by curve C in FIG. 8. The relationship between input power P.sub.in and output power P.sub.out for the FET amplifier 12 in indicated by curve C in FIG. 6. It is also noted that V.sub.dd,q=V.sub.dc2−V.sub.NR,q<V.sub.dc2 and V.sub.NR,q<V.sub.CCS,q; where V.sub.dd,q is the quiescent drain bias voltage at the Vdd terminal of the FET amplifier 12, V.sub.NR,q is the voltage drop across the DC current limiting circuit 14 under the quiescent condition; and V.sub.CCS,q is the voltage drop across the constant current source of the system in FIG. 4 under the quiescent condition.

(18) The DC POWER SUPPLY 1 and DC POWER SUPPLY 2 are set to establish the quiescent point of the FET amplifier 12. This quiescent point (Q-point) causes the FET amplifier 12 to draw a quiescent current I.sub.Q through the drain (D); that is, in the absence of, or at low input power levels, Idd=I.sub.Q at the quiescent point, as indicated by curve C in FIG. 7. In response to the power level of the input signal, the drain (D) of the FET amplifier 12 draws current Idd from the DC POWER SUPPLY 2 through the DC current limiting circuit 14, to be described in more detail below. The drawn current Idd produces a voltage drop, ΔV=(Vdc2−Vdd) across the DC bias limiting circuit 14, where Vdd is the voltage at the drain of the FET amplifier 12 (where Vdc2>Vdd) and that the relationship between the drawn current Idd and the voltage drop ΔV is shown in FIG. 8. It is particularly noted that the DC current limiting circuit 14 is configured so that the current Idd passing through the DC current limiting circuit 14 increases to the maximum current level I.sub.LIMIT (a level less than the maximum current the FET amplifier itself is able to draw, as described above in connection with FIG. 1). It is still further noted that in this example, at current levels of Idd less than I.sub.LIMIT, the voltage drop ΔV increases proportionately with Idd, here indicated as an ohmic region and that above I.sub.LIMIT the DC current limiting circuit 14 operates in a saturation region.

(19) Referring to FIG. 11, the operating range of the DC current limiting circuit 14 over the I-V (Current vs. Voltage) operating range of the amplifier system 10 is indicated by the arrow P.sub.in.sub._.sub.C of curve C. Thus, it is noted that for low input power levels Idd=I.sub.Q. As the input power increases, the current Idd increases above I.sub.Q, the voltage drop ΔV across DC bias current circuit 14 increases proportionately until Idd reaches I.sub.LIMIT where the voltage drop ΔV across the DC bias limiting circuit 14 reaches V.sub.KNEE. As the input signal power continues to increase, Idd remains at I.sub.LIMIT and the voltage drop ΔV continues to increase. By way of comparison, the I-V curve of the constant current source of the amplifier system in FIG. 4 is shown by the arrow Pin_B on curve B in FIG. 11. It is noted that the FET amplifier system in FIG. 4 operates with constant current at the quiescent current I.sub.Q and over its entire operating range and that the voltage drop across the constant current source is greater than the voltage drop, ΔV, across the DC current limiting circuit 14. Therefore, for the same Vdc2, the voltage at the drain (D) of the FET in the FET amplifier 12 of FIG. 5 is higher than the voltage at the drain (D) of the FET amplifier of FIG. 4. As a result, the FET amplifier 12 of FIG. 5, while operating in its linear region will have lower intermodulation distortion, which is synonymous to having higher IP3, than that in the FET amplifier of FIG. 4.

(20) The relationship between Idd and input signal power of the amplifier system 10 is shown by curve C in FIG. 7. The relationship between P.sub.in and output power P.sub.out of the amplifier system 10 is shown by curve C in FIG. 6; it being noted that the maximum output power of the amplifier system 10 in FIG. 5 (curve C in FIG. 6) is less than the FET amplifier itself described above in connection with FIG. 1 (curve A in FIG. 6). The relationship between the voltage at the drain (D) of the amplifier system 10 is indicated by curve C in FIG. 8; it is being noted that, as described above, the voltage Vdd at the drain (D) of the FET in amplifier system 10 is lower than the voltage Vdd at the drain (D) of the FET in the amplifier of FIG. 4 due to voltage drop across the DC current limiting circuit 14.

(21) Referring to FIG. 13, the effect of inserting the DC current limiting circuit 14 on the amplifier system 10 performance in terms of Idd and Pout is shown. The upper and lower curves on the left show the relationships of Idd and P.sub.out, respectively, as functions of input power for the FET amplifier of FIG. 1. The curve in the middle shows the relationship between Idd and ΔV=(Vdc2−Vdd) for the DC current limiting circuit 14; and the upper and lower curves on the right show the relationships between of Idd and P.sub.out, respectively, as functions of input power for the FET amplifier 10 of FIG. 5. It is noted that the maximum output power P.sub.out of the FET amplifier 10 of FIG. 5, is lower than the maximum output power P.sub.out of the FET amplifier FIG. 1.

(22) Thus, to put it another way, the DC current limiting circuit 14 acts as a nonlinear resistor. When the amplifier 10 is in the quiescent state or in the linear region, the DC bias limiting circuit 14 is in a low-resistance state (where the DC current limiting circuit has a resistance R1, FIG. 10); a voltage drop (V.sub.dc2−V.sub.dd) across the DC current limiting circuit 14 is small and equal to the product of I.sub.Q and resistance of the DC current limiting circuit 14, thus the DC voltage at the V.sub.dd terminal of the amplifier is lower than that for a stand-alone amplifier in FIG. 1 without the DC bias limiting circuit 14 by a small value of the voltage drop (V.sub.dc2−V.sub.dd) where (V.sub.dc2−V.sub.dd)<V.sub.KNEE; DC power available to the amplifier is not significantly smaller than that for a stand-alone amplifier in FIG. 1 without the DC current limiting circuit 14; as a result, the amplifier system's IP3 is not significantly lower than that of a stand-alone amplifier (FIG. 1). As the amplifier 10 enters its non-linear region, it draws increasing amount of DC current I.sub.dd through the DC current limiting circuit 14 from the DC POWER SUPPLY 2. The DC current limiting circuit 14 remains in its low-resistance state until I.sub.dd reaches a certain current level (I.sub.limit), when the DC current limiting circuit 14 moves into a high-resistance state (where the DC current limiting circuit has a resistance R2>>R1, typically two orders of magnitude greater, FIG. 10) wherein the DC current limiting circuit 14 limits the I.sub.dd to I.sub.limit. Continuing increase in input power level leads to I.sub.dd remaining constant and equal to I.sub.limit (as shown in curve labeled C in FIG. 7; the DC current limiting circuit 14 voltage drop (V.sub.dc2−V.sub.dd) increasing (as shown in curve labeled C in FIG. 8); V.sub.dd decreasing; P.sub.out is being inhibited to increase beyond a level P.sub.out.sub._.sub.comr.sub._.sub.C as shown in curve labeled C in FIG. 6 which is lower than that for a stand-alone amplifier (FIG. 1) (as shown in curve labeled A in FIG. 6). Thus, with such an arrangement of the amplifier system 10 of FIG. 5, the two goals of limiting output power in the non-linear region and preserving IP3 in the linear region are being achieved.

(23) Thus, the amplifier 12 has a linear operating region wherein the amplifier operates in accordance with the superposition principle (that is, the net response at a given place and time caused by two or more stimuli is the sum of the responses which would have been caused by each stimulus individually) and a compression operating region where the output signal power produced by the amplifier 12 has a compression power level, P.sub.out.sub._.sub.comr, invariant with the input signal power level when the power of the input signal is above a predetermined input power level. Further, the DC current limiting circuit 14 biases the amplifier 12 to limit the maximum output power at the output terminal of the system 10 to a level below the compression power level P.sub.out.sub._.sub.comr while the system 10 operates in its compression region.

(24) Referring to FIG. 9, here the DC current limiting circuit 14 having the relationship between a voltage produced at the drain of the FET amplifier of FIG. 5 as a function of current drawn by the FET amplifier of FIG. 5 shown in FIG. 10 is implemented with a Nonlinear Mesa Resistor (NMR). The NMR is formed by placing two ohmic contacts on two opposite sides of a rectangular semiconductor active region. Its current-voltage relationship includes an ohmic (low-resistance) region where the voltage drop across the resistor is approximately proportional to the current through the resistor by coefficient of proportionality, Ohmic Region Resistance R.sub.ohm; and a saturation (high-resistance) region where the current is substantially independent of the voltage drop and equal to Saturation Region Open-Channel Current I.sub.max. Both R.sub.ohm and I.sub.max are defined by features of technology (mesa resistivity R.sub.mess.sub._.sub.rho and open-channel current normalized to a unit of width I.sub.max[A/mm]) and physical dimensions (width W and length L). For example, in an AlGaAs/InGaAs/AlGaAs pseudomorphic High Electron Mobility Transistor (pHEMT) technology, R.sub.mess.sub._.sub.rho and I.sub.max[A/mm] are determined mostly by thicknesses and mole fractions of the constituent epitaxial layers; and by doping concentration level of a pulse doping layer (not shown) in the structure. Thus, here

(25) $\mathrm{Ohmic}\mathrm{Region}{\mathrm{ResistanceR}}_{\mathrm{ohm}}\left[\Omega \right]=\frac{\mathrm{dV}}{\mathrm{dI}}\approx R_{\mathrm{Mesa}\_\mathrm{Rho}}\left[\frac{\Omega }{\mathrm{square}}\right]*\frac{L}{W};$
and Saturation Region Open-Channel Current

(26) $I_{\max }\left[A\right]\approx I_{\max }\left[\frac{A}{\mathrm{mm}}\right]*W\left[\mathrm{mm}\right]$

(27) As shown in FIG. 11, to use the NMR as a DC current limiting circuit 14, it needs to be sized (i.e., L and W selected) in such a way that the amplifier's I.sub.Q falls in the NMR's ohmic region while the I.sub.limit is set to be equal to the NMR's I.sub.max. In general, the length L is selected as small as possible to minimize the ohmic region's series resistance, and thus preserve IP3 of the amplifier system 10 of FIG. 5. The width W is selected based on the desired I.sub.limit to achieve required P.sub.out.sub._.sub.cmpr.sub._.sub.C. FIG. 11 also illustrates how NMR can be sized to operate as a Constant Current Source (Active Load), representative of prior art performance shown in curves labeled B in FIGS. 6 and 12.

(28) FIGS. 12A and 12B demonstrate the output power limiting capability of the amplifier system in FIG. 5 achieved while preserving the system's linearity. This is illustrated by simulation results of the compressed output power and 3.sup.rd order output intercept point as functions of input signal frequency for: the amplifier of FIG. 1, indicated by curve A in FIG. 12; the amplifier of FIG. 4, indicated by curve B in FIG. 12; and the amplifier system 10 of FIG. 5, indicated by curves C1 and C2, respectively, in FIG. 12.

(29) It is noted that W.sub.NR>W.sub.CCS (where W.sub.NR is the width of the structure shown in FIG. 9 implemented as nonlinear resistor and where, for comparison purposes, W.sub.CCS is the width for the constant current source when implemented for use in the system of FIG. 4); R.sub.ohm.sub._.sub.NR<R.sub.ohm.sub._.sub.CCS (where R.sub.ohm.sub._.sub.NR is the ohmic region's resistance of the structure shown in FIG. 9 implemented as nonlinear resistor and where, for comparison purposes, R.sub.ohm.sub._.sub.CCS is the resistance of the structure of FIG. 9 when implemented as the constant current source for use in the system of FIG. 4); and I.sub.max.sub._.sub.NR>I.sub.max.sub._.sub.CCS (where I.sub.max.sub._.sub.NR is the saturation region's open-channel current of the structure shown in FIG. 9 implemented as nonlinear resistor and where, for comparison purposes, I.sub.max.sub._.sub.CCS is the saturation region's open-channel current of the constant current source when implemented for use the system of FIG. 4) I.sub.limit.sub._.sub.NR>I.sub.limit.sub._.sub.CCS (where I.sub.limit.sub._.sub.NR and I.sub.limit.sub._.sub.CCS are the desired limit currents of the structure shown in FIG. 9 implemented as nonlinear resistor and when implemented for use as a constant current source in the system of FIG. 4, respectively).

(30) Referring to FIGS. 12A and 12B, an effect of NMR's width W on the linear region's IP3 and nonlinear region's compressed output power P.sub.out.sub._.sub.cmpr is demonstrated. An NMR with smaller width (curve C2) has lower P.sub.out.sub._.sub.cmpr and comparable IP3 than an NMR with larger width (curve C1). In general, smaller W leads to lower I.sub.limit, and as a result, lower P.sub.out.sub._.sub.cmpr. On the other hand, smaller W may result in higher R.sub.ohm and lower IP3. This trade-off can be quantified using a relationship between I.sub.Q and I.sub.limit as following: I.sub.Q=I.sub.limit/K. For the amplifier in FIG. 1 with no DC limiting circuit, K is infinitely large; in other words, I.sub.limit is infinitely larger than I.sub.Q, resulting in no effect on IP3 and P.sub.out.sub._.sub.cmpr. For the amplifier system with the constant current source in FIG. 4, K is equal to 1; in other words, I.sub.limit is set to be equal to I.sub.Q, resulting in considerable limiting of P.sub.out.sub._.sub.cmpr, but also a large adverse effect on IP3. The amplifier system according to the disclosure in FIG. 5, occupies the spectrum of K values larger than 1 and less than infinity, corresponding to the cases of the amplifiers in FIGS. 4 and 1 respectively. The larger is the K, the less is the limiting of P.sub.out.sub._.sub.cmpr and smaller is the reduction in IP3. Here, for example, for curve C1: K=1.14; and for curve C2: K=1.06.

(31) Referring to FIG. 14, here a DC bias limiting circuit 14′ is implemented as a FET with Connected Gate and Source Electrodes (FETSCGE). An FETCSGE is formed by placing two ohmic contacts on two opposite sides of a rectangular semiconductor active region with a Schottky contact in between the two ohmic contacts; the Schottky contact and one of the ohmic contacts are connected by a metal strip outside of the semiconductor active region. Its current-voltage relationship (FIG. 15) includes an ohmic (low-resistance) region where the voltage drop across the resistor is approximately proportional to the current through the resistor by coefficient of proportionality, Ohmic Region Resistance R.sub.ohm; and a saturation (high-resistance) region where the current is substantially independent of the voltage drop and equal to Saturation Region Saturation Current I.sub.dss. Both R.sub.ohm and I.sub.dss are defined by features of technology (mesa resistivity R.sub.mesa.sub._.sub.rho and saturation current normalized to a unit of width I.sub.dss[A/mm]) and physical dimensions (width W and length L). As shown in FIG. 15, to use FETSCGE as a DC bias limiting circuit 14′, it needs to be sized (i.e., L and W selected) in such a way that the amplifier's I.sub.Q falls in the FETSCGE's ohmic region while the I.sub.limit is set to be equal to the FETSCGE's I.sub.dss. Thus,

(32) $\mathrm{Ohmic}\mathrm{Region}\mathrm{Resistance}{R}_{\mathrm{ohm}}\left[\Omega \right]=\frac{\mathrm{dV}}{\mathrm{dI}}\approx 1.3*R_{\mathrm{Mesa}\_\mathrm{Rho}}\left[\frac{\Omega }{\mathrm{square}}\right]*\frac{L}{W}\mathrm{Saturation}\mathrm{Region}\mathrm{Saturation}\mathrm{Current}{I}_{\mathrm{dss}}\left[A\right]\approx I_{\mathrm{dss}}\left[\frac{A}{\mathrm{mm}}\right]*W\left[\mathrm{mm}\right]<I_{\max }\left[A\right]$
FIG. 15 also illustrates how FETSCGE can be sized to operate as a Constant Current Source (Active Load), representative of prior art performance shown in curves labeled B in FIGS. 5 and 12. It is noted that here, for purposes of comparison: W.sub.NR>W.sub.CCS R.sub.ohm.sub._.sub.NR<R.sub.ohm.sub._.sub.CCS and I.sub.dss.sub._.sub.NR>I.sub.dss.sub._.sub.CCS I.sub.limit.sub._.sub.NR>I.sub.limit.sub._.sub.CCS where I.sub.dss.sub._.sub.NR is the drain current for the amplifier 12 (FIG. 5) and I.sub.dss.sub._.sub.CCS is the drain current for the system of FIG. 4.

(33) A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, the amplifier may be a bipolar transistor amplifier, and other forms and technology may be used to form the DC current limiting circuit. Further, while the FET described above was a AlGaAs/InGaAs/AlGaAs pHEMT, which is a depletion-mode n-channel FET technology requiring positive quiescent drain-source voltage and negative quiescent gate-source voltage; the disclosure is applicable to other FET (n- or p-channel, depletion- or enhancement-mode, elemental semiconductor (Si) or compound semiconductor (GaAs, SiGe), homogeneous (GaAs) or heterogeneous (AlGaAs/InGaAs/AlGaAs)) and BJT (npn or pnp) technologies with modifications in the quiescent voltages' polarities. It should be further understood that the terms source and drain may be interchanged depending on the technology used. Accordingly, other embodiments are within the scope of the following claims.