System and method of noise correcting PLL frequency synthesizers

Abstract

An improved noise-corrected phase-locked loop frequency synthesizer configured to reduce noise, such as phase noise and spurious signals, without the use of switching circuits. The synthesizer uses a phase shifter device configured to accept a noise containing frequency signal from a voltage controlled oscillator (VCO) circuit, such as an integer-N single loop PLL synthesizer, as well as noise reducing control signals from a noise detecting sensor or circuit, and output a noise reduced VCO frequency signal. In some embodiments, the noise reducing sensor may be formed from a second, lower noise, phase locked loop circuit. The frequency synthesizer circuit, noise detecting sensor, and the phase shifter device are configured to all run continuously, with the noise reducing sensor and frequency shifter continually acting to reduce noise, produced by higher noise integer-N PLL frequency synthesizer.

Claims

1. A noise-corrected phase-locked loop frequency synthesizer device comprising: a phase shifter configured to simultaneously accept a noise-uncorrected VCO frequency signal from a VCO, and noise reducing control signals from a noise detecting sensor, and output a noise-corrected VCO frequency signal; wherein said noise detecting sensor is configured to compare a difference between said noise-corrected VCO frequency signal, and a lower noise reference at a same VCO frequency, and to use said difference to produce said noise correcting control signals for said phase shifter; and wherein said noise detecting sensor comprises a second phase detector, second low pass filter, second amplifier, and a plurality of series connected mixer stages; each said mixer stage comprising a mixer and a corresponding local oscillator circuit; wherein said plurality of series connected mixer-stages and said second phase detector are configured to compare said noise-corrected VCO frequency signal with a low-phase-noise reference frequency signal, producing phase noise difference signals; said second low pass filter and said second amplifier configured to use said phase noise difference signals to provide said noise reducing control signals to said phase shifter.

2. The device of claim 1, wherein said VCO is driven by a frequency divider, first phase detector, first low pass filter, and first amplifier; and wherein said frequency divider is configured to frequency divide said noise-uncorrected VCO frequency signal, and provide a frequency divided noise-uncorrected VCO frequency signal as input to said first phase detector; said first phase detector, first low pass filter, and said first amplifier configured to use said frequency divided said noise-uncorrected VCO frequency signal, and a step-size reference frequency (F.sub.0), to drive said VCO to oscillate at a desired frequency that is a multiple of said step-sized reference frequency F.sub.0.

3. The device of claim 2, further comprising a power splitter configured to provide said noise-uncorrected VCO frequency signal to said frequency divider; and wherein said frequency divider is a programmable frequency divider with a programmable division coefficient N.

4. The device of claim 1, further comprising a power splitter configured to provide said noise-corrected VCO frequency signal.

5. The device of claim 1, further comprising a low-phase-noise reference frequency generator.

6. The device of claim 1, wherein said plurality of series connected mixer stages are configured to compare said noise-corrected VCO frequency signal with a low-phase-noise reference frequency signal by converting said noise-corrected VCO frequency signal, through a plurality of intermediate frequencies I.sub.f, into a comparison frequency F.sub.0′, provided as input into said second phase detector, as said noise-corrected VCO frequency signal, that is a function of a step-size reference frequency (F.sub.0) and a noise component.

7. The device of claim 6, wherein said plurality of series connected mixer stages are configured to produce each said plurality of intermediate frequencies I.sub.f by a difference between a mixer input frequency, and a local oscillator signal produced by a corresponding local oscillator circuit comprising a multiplier acting on a local oscillator frequency divided input frequency from either a low phase noise reference frequency or a previous local oscillator frequency divided version of said low phase noise reference frequency.

8. A noise-corrected phase-locked loop frequency synthesizer device comprising: a phase shifter configured to simultaneously accept a noise-uncorrected VCO frequency signal from a VCO, and noise reducing control signals from a noise detecting sensor, and output a noise-corrected VCO frequency signal; wherein said VCO is driven by a frequency divider, power splitter, first phase detector, first low pass filter, and first amplifier; and wherein said frequency divider is a programmable frequency divider with a programmable division coefficient N, said frequency divider configured to frequency divide said noise-uncorrected VCO frequency signal provided by said power splitter, and provide a frequency divided noise-uncorrected VCO frequency signal as input to said first phase detector; said first phase detector, first low pass filter, and said first amplifier configured to use said frequency divided noise-uncorrected VCO frequency signal, and a step-size reference frequency (F.sub.0), to drive said VCO to oscillate at a desired frequency that is a multiple of said step-sized reference frequency F.sub.0; wherein said noise detecting sensor is configured to compare a difference between at least a portion of said noise-corrected VCO frequency signal, and a lower noise reference at a same VCO frequency, and to use said difference to produce said noise correcting control signals for said phase shifter.

9. The device of claim 8, wherein said noise detecting sensor comprises a second phase detector, second low pass filter, second amplifier, and a plurality of series connected mixer stages; each said mixer stage comprising a mixer and a corresponding local oscillator circuit; wherein said plurality of series connected mixer stages and said second phase detector are configured to compare said noise-corrected VCO frequency signal provided by said power splitter, with a low-phase-noise reference frequency signal, producing phase noise difference signals; said second low pass filter and said second amplifier configured to use said phase noise difference signals to provide said noise reducing control signals to said phase shifter.

10. The device of claim 9, wherein said plurality of series connected mixer stages are configured to compare said noise-corrected VCO frequency signal with a low-phase-noise reference frequency by converting said noise-corrected VCO frequency signal, through a plurality of intermediate frequencies I.sub.f, into a comparison frequency F.sub.0′ provided as input into said second phase detector, as said noise-corrected VCO frequency signal, that is a function of a step-size reference frequency (F.sub.0) and a noise component.

11. The device of claim 10, wherein said plurality of series connected mixer stages are configured to produce each said plurality of intermediate frequencies I.sub.f by a difference between a mixer input frequency, and a local oscillator signal produced by a corresponding local oscillator circuit comprising a multiplier acting on a local oscillator frequency divided input frequency from either a low phase noise reference frequency or a previous local oscillator frequency divided version of said low phase noise reference frequency.

12. The device of claim 9, wherein a sum of each said mixer and said corresponding local oscillator circuit over said plurality of series connected mixer stages is selected to have a combined phase noise that is substantially less than a phase noise produced by a frequency divider-driven phase lock loop driven by said frequency divider.

13. The device of claim 9, wherein at least some of said corresponding local oscillator circuits further comprises a local oscillator divider device.

14. A method of noise-correcting a phase-locked loop frequency synthesizer, said method comprising: obtaining a phase locked loop frequency synthesizer comprising a VCO, a noise detecting sensor, and a phase shifter; using said phase shifter to simultaneously accept a noise-uncorrected VCO frequency signal from said VCO, and noise reducing control signals from said noise detecting sensor, and output a noise-corrected VCO frequency signal; further using said noise detecting sensor to compare a difference between at least a portion of said noise-corrected VCO frequency signal, and a lower noise reference signal at a same VCO frequency, and to use said difference to produce said noise correcting control signals for said phase shifter; and wherein said noise detecting sensor comprises a second phase detector, second low pass filter, second amplifier, and a plurality of series connected mixer stages; each said mixer stage comprising a mixer and a corresponding local oscillator circuit; using said plurality of series connected mixer stages and said second phase detector to compare said noise-corrected VCO frequency signal with a low-phase-noise reference frequency signal, and to produce phase noise difference signals; and using second low pass filter, said second amplifier and said phase noise difference signals to provide said noise reducing control signals to said phase shifter.

15. The method of claim 14, further using a frequency divider, first phase detector, first low pass filter, and first amplifier to drive said VCO by: using said frequency divider to frequency divide said noise-uncorrected VCO frequency signal, and to provide a frequency divided noise uncorrected VCO frequency signal as input to said first phase detector; using said first phase detector, first low pass filter, said first amplifier, said frequency divided noise uncorrected VCO frequency signal, and a step-size reference frequency (F.sub.0), to drive said VCO at a desired frequency that is a multiple of said step-sized reference frequency F.sub.0.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a simplified block diagram of a prior art PLL synthesizer.

(2) FIG. 2 shows a simplified block diagram of a prior art synthesizer employing a frequency conversion.

(3) FIG. 3 shows an example of the spurious frequency signals (spurious products generated by mixers) that can occur in some prior art synthesizers.

(4) FIG. 4 shows a simplified block diagram for the prior art synthesizer of U.S. Pat. No. 7,701,299, which employed multiple frequency conversions in the synthesizer feedback loop.

(5) FIG. 5 shows an example of the output frequencies generated by a conventional synthesizer with multiple frequency conversions in the synthesizer feedback loop.

(6) FIG. 6 shows a simplified diagram of the invention's noise correcting frequency synthesizer.

(7) FIG. 7 shows an alternate diagram of the invention's noise correcting frequency synthesizer.

(8) FIG. 8 shows one method of providing local oscillator signals to a plurality of series connected mixers.

DETAILED DESCRIPTION OF THE INVENTION

(9) FIG. 6 shows a simplified diagram of the invention's noise correcting phase-locked loop frequency synthesizer. In this embodiment, the invention may comprise a phase shifter (600) configured to simultaneously accept an uncorrected frequency from a VCO (602) (in some embodiments by way of an optional power splitter 603), and noise reducing control signals (604) from a noise detecting sensor (606), and output a noise-corrected VCO frequency signal.

(10) In some embodiments of the present invention, the VCO (602) may be driven by a frequency divider (FD, 610), a first phase detector (PD1, 612), first low pass filter (LPF, 614), and first amplifier (A1, 616). Here this frequency divider (FD, 610) may be configured to frequency divide a first portion (618) of the noise uncorrected VCO frequency signal (618), (in some embodiments by way of an optional power splitter 603) and provide a frequency divided noise uncorrected VCO frequency signal (F.sub.0″, 620) as input to the first phase detector (PD1, 612).

(11) This first phase detector (PD1, 612), first low pass filter (LPF1, 614), and the first amplifier (A1, 616) may be configured to use the frequency divided noise uncorrected VCO frequency signal (F.sub.0″, 620), and a step-size reference frequency (F.sub.0), to drive the VCO (602) to oscillate at a desired frequency that is a multiple of the step-sized reference frequency F.sub.0.

(12) This configuration also can be viewed as forming a phase locked loop PLL1, alternatively referred to as an integer-N single-loop PLL synthesizer.

(13) In a preferred embodiment, the frequency divider (FD, 610) can be a programmable frequency divider with a programmable division coefficient N, where N is typically a positive integer, often a high multiple positive integer with values of magnitude 10, 100, 1000, 10,000 or more. Thus frequency divider (FD, 610) can also be viewed as a divider having a high, integer-N division coefficient or ratio, often with a division coefficient greater than 100, 1000, 10,000 or more.

(14) In some embodiments, the noise detecting sensor (606) is configured to compare a difference between at least a portion (this can be a converted portion) of the noise-corrected VCO frequency signal (626), and a lower noise reference at a same VCO frequency (such as F.sub.0 or F.sub.REF), and to use this difference to produce the noise correcting control signals (604) for the phase shifter (600). In other configurations, the noise detecting sensor (606) may be configured to directly sample (such as by way of optional first power splitter 603) the uncorrected VCO frequency signal (628) before the phase shifter (600) either as an alternative to signal (626), or in addition to signal (625).

(15) Here F.sub.REF can be a fixed-frequency, high-stability, low phase noise oscillator, such as an ovenized (oven-controlled) crystal oscillator (OCXO).

(16) FIG. 7 shows an alternate diagram of the invention's noise correcting frequency synthesizer.

(17) In this embodiment, the noise detecting sensor (706) comprises a second phase detector (PD2, 712), second low pass filter (LPF2, 714), second amplifier (A2, 716), and a plurality of series connected mixer stages (730). Here each mixer stage typically comprises a mixer (M.sub.x, 732) and a corresponding local oscillator circuit (LO.sub.x, 734) for that particular mixer.

(18) In this embodiment, this plurality of series connected mixer stages (730), and the second phase detector (PD2, 712) are configured to compare the noise-corrected VCO frequency signal (626) with a low-phase-noise reference frequency signal (such as the LO.sub.x, 734), producing phase noise difference signals (704). The second low pass filter (LPF2, 714) and second amplifier (A2, 716) are configured to use these phase noise difference (704) signals to provide the noise reducing control signals (604) to the phase shifter (600).

(19) This invention may often also further comprise a low-phase-noise reference frequency generator (736), used to generate F.sub.REF (also referred to as F.sub.0).

(20) This plurality of series connected mixer stages (730, 732) are, in some embodiments, configured to compare a second portion of the noise-corrected VCO frequency signal (626) with at least one low-phase-noise reference frequency signal (often provided by the local oscillators LO.sub.1 . . . LO.sub.j). This can be done by, for example, converting the second portion (626) of the noise-corrected VCO frequency, through a plurality of intermediate frequencies I.sub.fx, into a comparison frequency F.sub.0′ that is a function of a step-size reference frequency (F.sub.0) provided by F.sub.REF (736) and a noise component (here this noise component will vary depending on how much noise is detected). This comparison frequency F.sub.0′ is then provided as input into the second phase detector (712), essentially as a modified (frequency down-converted) version of the second portion of the noise-corrected VCO frequency signal (626).

(21) More specifically, FIG. 7 shows that the improved frequency synthesizer can include a tunable voltage controlled oscillator VCO (602) (followed in some embodiments by way of optional first power splitter 603), followed by a phase shifter (600) and another (e.g. second) power splitter PS (624). A first portion (618) of the VCO output signal f (in some embodiments provided by way of an optional first power splitter 603) is divided by frequency divider FD (610), (preferably with a programmable division coefficient N) and this signal (620, F.sub.0″) goes to the phase detector PD1 (612). The phase detector PD1 compares the signals (F.sub.0, and F.sub.0″) at both inputs and generates an error voltage (613) which, following filtering in low-pass loop filter LPF1 (614) and amplification by operational amplifier A1 (616) respectively, slews the frequency of the VCO (602) to a lock frequency given by
f=F.sub.0×N

(22) Thus, the first phase lock loop (PLL1) with the programmable divider (610) provides a simple and reliable mechanism to pre-tune the VCO (602) to the desired frequency. However the phase noise of the generated signal is degraded by the division coefficient N at 20 log N rate, so this creates some undesired phase noise.

(23) In this embodiment, the noise sensor (606) can comprise a second phase lock loop PLL2 that detects the phase noise produced by the first phase lock loop, and sends correcting signals to the phase shifter (600) to compensate and reduce this noise, while, at the same time, PLL1 continues to operate. Note that in contrast to U.S. Pat. No. 7,701,299, PLL1 has not been switched out of the circuit. This avoids the various switching issues associated with U.S. Pat. No. 7,701,299.

(24) In this embodiment, the VCO output signal f (626) is converted in mixers M.sub.1-M.sub.i to a compassion frequency F.sub.0′ that is substantially equal to the synthesizer step size (resolution). This is provided as one input to the second phase detector (PD2, 712).

(25) The other phase detector (PD2, 712) comparison frequency input F.sub.0, as well as the various mixer LO.sub.x signals, can be produced from a common high-stable, low phase noise reference signal F.sub.REF, and or a multiple of F.sub.REF which may in some embodiments be produced by frequency multiplier (806).

(26) Here, an important aspect of this embodiment, as well as the embodiment discussed in FIG. 8, is that this portion of the circuit is designed so that the total amount (e.g. sum) of the noise contributed by each mixer and it's corresponding local oscillator circuit, over the various of series connected mixer stages, is configured or selected to have a combined phase noise that is substantially less than a phase noise produced by first loop PLL1 containing the frequency divider (610). This constraint is needed so that the noise detector circuit, by virtue of being less noisy than the noise produced by the PLL1 circuit employing frequency divider (610), thus can, by use of phase detector 2 (PD2, 712) detect noise and ultimately send noise correction signals to the phase shifter (600).

(27) FIG. 8 shows a diagram of one method of providing local oscillator signals to a plurality of mixer stages.

(28) In some embodiments, the plurality of series connected mixer stages (730) may be configured to produce the various intermediate frequencies I.sub.f by configuring the mixer stages to produce a difference between a mixer input frequency (e.g. an intermediate frequency I.sub.f produced by the previous mixer in the series), and that mixer's particular local oscillator signal (LO.sub.x).

(29) These local oscillator signals LO.sub.x can be produced by various schemes. In one scheme, the various local oscillator signals (734) may be produced by a multiplier xC.sub.x (800, 802) acting on a frequency divided (using local oscillator frequency dividers :Dx, 804) input frequency from either a low phase noise reference frequency (which can be provided by F.sub.REF or a multiplied N×F.sub.REF source 806) or a previous local oscillator frequency divided (804) version of this low phase noise reference frequency. These local oscillator frequency dividers :Dx (804) are also occasionally designated as local oscillator divider devices, which are a component of the various corresponding local oscillator circuits used to provide the various corresponding local oscillator signals.

(30) Thus in one embodiment, the various local oscillator signals can be produced using a circuit similar to that previously taught in U.S. Pat. No. 7,701,299. As a result, in this particular case, the resulting local oscillator frequency calculations can also be similar.

(31) More specifically, the comparison frequency F.sub.0′, as well as the various mixer LO signals (734) may be produced from a common high-stable, low phase noise reference signal F.sub.REF (736) using local oscillator frequency dividers (804) with frequency division ratios D.sub.1-D.sub.1 as well as frequency multipliers (800, 802) with multiplication factors C.sub.1-C.sub.i respectively. In some embodiments, these multipliers can be comb generators, with a frequency output signal that contains a large number of harmonics.