LED lamp arrangement adapted to replace fluorescent lamp in luminaire with ballast

Abstract

An LED lamp arrangement is disclosed to replace a fluorescent lamp in a luminaire with a ballast. The LED lamp arrangement has a rectifier, LEDs, a LED driver, an impedance balance circuit, a line-voltage controller. The rectifier has two inputs connected to the ballast to provide a rectified power line and a ground power line. The LEDs and a LED driver are connected in series between the rectified power line and the ground power line, and the LED driver regulates a LED driving current through the LEDs. The impedance balance circuit is coupled between the inputs. The line-voltage controller controls the impedance balance circuit in response to a line voltage at the rectified power line, so as to tune an impedance between the inputs and make the line voltage approach to a predetermined target voltage.

Claims

1. A light emitting diode (LED) lamp arrangement adapted to replace a fluorescent lamp in a luminaire having a ballast for supplying power to the fluorescent lamp, the LED lamp arrangement comprising: a rectifier having two inputs configured to be connected to the ballast, the rectifier providing a rectified power line and a ground power line; a plurality of LEDs and a LED driver connected in series between the rectified power line and the ground power line, wherein the LED driver regulates a LED driving current through the LEDs; an impedance balance circuit configured to be coupled between the inputs; a line-voltage controller for controlling the impedance balance circuit in response to a line voltage at the rectified power line, so as to tune an impedance between the inputs and make the line voltage approach to a predetermined target voltage; and a timer for delaying start of operation of the line-voltage controller by a predetermined period after the line voltage reaches a predetermined value; wherein the LEDs have a forward voltage less than the predetermined target voltage.

2. The LED lamp arrangement of claim 1, wherein the impedance balance circuit includes two capacitors connected in series between the inputs, a joint connects the two capacitors, and the line-voltage controller controls a connection between the joint and the ground power line to tune the impedance between the inputs.

3. The LED lamp arrangement of claim 1, wherein the impedance balance circuit includes a redundant resistor connected to the rectified power line, and the line-voltage controller controls a connection between the redundant resistor and the ground power line to tune the impedance between the inputs.

4. The LED lamp arrangement of claim 1, further comprising: a voltage detector; and a detection resistor connected between the rectified power line and the voltage detector, wherein the voltage detector detects the line voltage via the detection resistor; wherein the line-voltage controller is connected to the voltage detector for comparing the line voltage with the predetermined target voltage to control the impedance balance circuit.

5. The LED lamp arrangement of claim 1, wherein the LED driver comprises: a first constant-current driver for controlling a LED driving current through the LEDs, wherein the first constant-current driver is configured to regulate the LED driving current at a first constant value; and a second constant-current driver for controlling the LED driving current, wherein the second constant-current driver is configured to regulate the LED driving current at a second constant value larger than the first constant value; wherein the second constant-current driver is connected between the LEDs and the first constant-current driver.

6. The LED lamp arrangement of claim 1, further comprising: a current-limiting resistor; a direct-current regulator connected to the rectified power line through the current-limiting resistor; a first capacitor, wherein the direct-current regulator regulates a first operational voltage on the first capacitor, wherein the timer is powered by the first operational voltage, for timing the predetermined period after operational voltage has reached a first reference voltage; a second capacitor; and an auxiliary controller for charging the second capacitor after the predetermined period elapses; wherein the second capacitor provides a second operational voltage to power the line-voltage controller and the LED driver.

7. The LED lamp arrangement of claim 6, wherein the line-voltage controller, the direct-current regulator, the timer, and the auxiliary controller are integrated in an integrated circuit on a chip.

8. The LED lamp arrangement of claim 6, further comprising: an initial condition checker, for comparing the line voltage with an initial voltage; wherein the initial condition checker signals the timer to start timing the predetermined period when the line voltage exceeds the initial voltage.

9. The LED lamp arrangement of claim 1, wherein the LEDs has a forward voltage less than the predetermined target voltage.

10. A control method for lighting light emitting diodes (LEDs) in a LED lamp arrangement adapted to replace a fluorescent lamp in a luminaire having a ballast for supplying power to the fluorescent lamp, wherein the LED lamp arrangement has two inputs configured to be connected to the ballast, the control method comprising: rectifying an alternating-current voltage between the inputs to provide a rectified power line and a ground power line; regulating a LED driving current through the LEDs, wherein the LEDs is connected between the rectified power line and the ground power line; detecting a line voltage at the rectified power line; and utilizing a timer to constrain consumption current of the LED lamp arrangement to be within a predetermined range for a predetermined period after the line voltage reaches a predetermined value before tuning an impedance between the inputs to make the line voltage approach to a predetermined target voltage.

11. The control method of claim 10, comprising: providing two capacitors connected in series between the inputs, wherein a joint connects the two capacitors; and controlling a connection between the joint and the ground power line to tune the impedance between the inputs.

12. The control method of claim 10, comprising: providing a redundant resistor connected to the rectified power line; and controlling a connection between the redundant resistor and the ground power line to tune the impedance between the inputs.

13. The control method of claim 10, further comprising: comparing a line voltage at the rectified power line with an initial voltage; and timing a predetermined period when the line voltage exceeds the initial voltage; wherein the steps of regulating and tuning start after the predetermined period has elapsed.

14. The control method of claim 13, wherein the step of rectifying employs a rectifier outputting a consumption current, the control method further comprising: constraining the consumption current in a predetermined range before the steps of regulating and tuning starts.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

(2) FIGS. 1A and 1B demonstrate two configurations when an LED lamp arrangement according to embodiments of the invention is inserted in the luminaires with magnetic and electronic ballasts respectively;

(3) FIG. 2 demonstrates a schematic circuit of an LED lamp arrangement according to embodiments of the invention;

(4) FIG. 3 demonstrates a voltage detector in connection with a detection resistor;

(5) FIG. 4 demonstrates a current regulator, together with a power transistor and a current-sense resistor;

(6) FIG. 5 demonstrates a line-voltage controller in connection with an impedance balance circuit;

(7) FIG. 6 demonstrates a sequence controller; and

(8) FIG. 7 shows a control method used by the LED lamp arrangement in FIGS. 1A and 1B.

DETAILED DESCRIPTION

(9) The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments would be evident based on the present disclosure, and that improves or mechanical changes may be made without departing from the scope of the present invention.

(10) In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known configurations and process steps are not disclosed in detail.

(11) FIGS. 1A and 1B demonstrate possible configurations when an LED lamp arrangement 100 according to embodiments of the invention is inserted in the luminaires with magnetic and electronic ballasts respectively. In FIG. 1A, a magnetic ballast 22 is placed in series with a mains power supply 20 to the LED lamp arrangement 100. In FIG. 1B, an electronic ballast 24 converts AC power from a mains power supply 20 to power the LED lamp arrangement 100. The LED lamp arrangement 100 might have the same exterior of a conventional fluorescent lamp, and each double-pined end cap 26 in FIGS. 1A and 1B has its two pins shorted to each other inside a tube 28. Therefore, these two double-pined end caps 26 are deemed to provide two inputs BSTN and BSTP inside the tube 28 respectively.

(12) FIG. 2 demonstrates a schematic circuit of the LED lamp arrangement 100 according to embodiments of the invention. The devices shown in FIG. 2 might be all sealed inside the tube 28 to avoid users from touch and electric shock. The LED lamp arrangement 100 has a rectifier 110, an integrated circuit 102 possibly formed on a packaged chip, LEDs 104, a power transistor 106, current-sense resistor 108, detection resistor R.sub.DET, current-limiting resistor R.sub.IN, capacitors C.sub.DC and C.sub.CTRL and impedance balance circuit 119 with redundant resistor R.sub.IB and capacitors C.sub.IBP and C.sub.IBN.

(13) The rectifier 110 could be a full-bridge or half-bridge rectifier, providing rectified power line LEDP and a ground power line. When the inputs BSTP and BSTN are connected to the outputs of a well-powered ballast, the rectifier 110 rectifies the AC voltage between inputs BSTP and BSTN and generates a DC line voltage V.sub.LEDP and a ground voltage at the rectified power line LEDP and the ground power line respectively. To facilitate explanation, the ground voltage is deemed to be 0V and the line voltage V.sub.LEDP is positive in this specification. If the rectifier 110 receives an AC voltage from a magnetic ballast, the AC voltage between inputs BSTP and BSTN could be of a frequency as low as 100 hz. Otherwise, if generated from an electronic ballast, the AC voltage could be of a high frequency ranging from 30,000 hz to 50,000 hz. It is preferable that the rectifier 110 employs diodes with reverse recovery time shorter than 1u second.

(14) The integrated circuit 102 includes a current regulator 114, a voltage detector 112, a sequence controller 116, and a line-voltage controller 118, all integrated on a chip. Through pins, the integrated circuit 102 is connected to external devices and power lines, such as the power transistor 106, the resistor 108, and the ground power line, as demonstrated in FIG. 2.

(15) FIG. 3 demonstrates the voltage detector 112 and the detection resistor R.sub.DET connected to each other via the pin SENS. The voltage detector 112 is in configuration of a current mirror. Shown in FIG. 3, the voltage detector 112 has an N-type MOS transistor MN.sub.0 configured as a MOS diode to detect current I.sub.DET flowing from the rectified power line LEDP through the detection resistor R.sub.DET. Accordingly the voltage detector 112 generates mapping currents I.sub.S1, I.sub.S2, I.sub.S3 . . . in proportion to the current I.sub.DET. The magnitude IDET of the current I.sub.DET can be roughly derived by the following equation, “IDET=(V.sub.LEDP−V.sub.TH-MN0)/RDET”, where V.sub.TH-MN0 is the threshold voltage of N-type MOS transistor MN.sub.0, and RDET the resistance of the detection resistor R.sub.DET. The mapping current I.sub.S1, for example, could be K.sub.S1*IDET, where K.sub.S1 is the weighting factor of the mapping current I.sub.S1 over the current I.sub.DET. In other words, the voltage detector 112 detects the line voltage V.sub.LEDP via the detection resistor R.sub.DET to generate the mapping currents I.sub.S1, I.sub.S2 and I.sub.S3.

(16) FIG. 4 demonstrates the current regulator 114, together with power transistor 106 and current-sense resistor 108, acting in a whole as a LED driver DRV to provide and regulate a LED driving current I.sub.LED through the LEDs 104. The current regulator 114 has operational MN.sub.LED amplifiers OP1 and OP2, connected to control power transistors and 106 respectively, in response to the voltage across the current-sense resistor 108. Shown in FIG. 4, the current regulator 114 is powered by an operational voltage V.sub.CTL, which will be detailed later. An offset resistor R.sub.OS and a current source IS.sub.OS are connected to provide an offset voltage V.sub.OS between the non-inverted input of the operational amplifier OP1 and the non-inverted input of the operational amplifier OP2, as shown in FIG. 4, where a setting voltage V.sub.SET is provided to the operational amplifier OP1. It is derivable from FIG. 4 that the operational amplifier OP1 and the power transistor MN.sub.LED perform in combination as a constant-current driver DR1, configured to regulate the LED driving current I.sub.LED at a constant IC1 equal to the setting voltage V.sub.SET divided by the resistance of current-sense resistor 108. Similarly, the operational amplifier OP2 and the power transistor 106 are deemed together as another constant-current driver DR2 configured to regulate the LED driving current I.sub.LED at another constant IC2, which however is slightly larger than the constant IC1 due to the existence of the offset voltage V.sub.OS. The constant-current driver DR1 has a wider closed-loop bandwidth in comparison with the constant-current driver DR2, or the constant-current driver DR1 responses quicker than the constant-current driver DR2. The constant-current driver DR1 will dominate the current control to the LED driving current I.sub.LED since the constant IC1 is less than the constant IC2. The constant-current driver DR2, connected between the LEDs 104 and the constant-current driver DR1, could nevertheless prevent any rush current short through to the downstream power transistor MN.sub.LED during a startup or when the line voltage V.sub.LEDP varies violently.

(17) FIG. 5 demonstrates the line-voltage controller 118 in connection with the impedance balance circuit 119. Shown in FIG. 5, the impedance balance circuit 119 has the capacitors C.sub.IBP and C.sub.IBN, and the redundant resistor R.sub.IB. The capacitors C.sub.IBP and C.sub.IBN are connected to each other by the joint ND.sub.J and in series between the inputs BSTP and BSTN, while the redundant resistor R.sub.IB is connected between the rectified power line LEDP and the joint ND.sub.J. The line-voltage controller 118 provides and controls a connection between the joint ND.sub.J and the ground power line. The line-voltage controller 118 has a current source IS powered by the operational voltage V.sub.CTL, and the current source IS is connected to the transistor MN.sub.1 in FIG. 3 that drains the mapping current I.sub.S1. An inverter buffer 123 is connected between a NMOS transistor MN.sub.D and the current source IS. If the current provided by the current source IS exceeds the mapping current I.sub.S1, the voltage at the control node of the NMOS transistor MN.sub.D ramps down over time. In the opposite, if the current provided by the current source IS is less than the mapping current I.sub.S1, the voltage at the control node of transistor MN.sub.D rises over time. The line-voltage controller 118 compares the mapping current I.sub.S1 with the current output from the current source IS to control the impedance balance circuit 119.

(18) As aforementioned, the mapping currents I.sub.S1 is K.sub.S1*IDET, and IDET is (V.sub.LEDP−V.sub.TH-MN0)/RDET. If the mapping current I.sub.S1 is equal to the current source IS, the line voltage V.sub.LEDP must meet the following equation, “K.sub.S1*(V.sub.LEDP−V.sub.TH-MN0)/RDET=IS”. The line-voltage controller 118 seemingly detects the line voltage V.sub.LEDP by way of the voltage detector 112, and compares it with a predetermined target voltage, “IS*RDET/K.sub.S1+V.sub.TH-MN0”, so as to control the impedance balance circuit 119.

(19) The transistor MN.sub.D provides a connection between the ground power line and the joint ND.sub.J, and the voltage at the control node of the transistor MN.sub.D tunes the impedance of the connection. Supposed that the line voltage V.sub.LEDP exceeds the predetermined target voltage, the voltage at the control node of the transistor MN1 ramps up, so the impedance between the joint ND.sub.J and the ground power line decreases, the impedance between the inputs BSTP and BSTN reduces, the amplitude of the AC voltage between the inputs BSTP and BSTN ramps down, the line voltage V.sub.LEDP at the rectified power line LEDP goes downward. Only when the line voltage V.sub.LEDP becomes less than the predetermined target voltage does the inverter buffer 123 start reducing the voltage at the control node of the NMOS transistor MN.sub.D. Overtime, the line voltage V.sub.LEDP will converge at the predetermined target voltage. Therefore, the line-voltage controller 118 controls the impedance balance circuit 119 in response to the line voltage V.sub.LEDP, so as to tune an impedance between the inputs BSTP and BSTN and make the line voltage V.sub.LEDP approach to the predetermined target voltage.

(20) Shown in FIG. 5, the impedance balance circuit 119 has the capacitors C.sub.IBP and C.sub.IBN and the redundant resistor R.sub.IB. This invention is not limited however. In one embodiment of the invention, the impedance balance circuit 119 could have the capacitors C.sub.IBP and C.sub.IBN, but lacks the redundant resistor R.sub.IB. In another embodiment of the invention, the impedance balance circuit 119 could have the redundant resistor R.sub.IB, but lacks the capacitors C.sub.IBP and C.sub.IBN.

(21) FIG. 6 demonstrates the sequence controller 116 including an initial condition checker 131, a bias-setting circuit 136, a direct-current (DC) regulator 130 connected between the current-limiting resistor R.sub.IN and the capacitor C.sub.DC, an auxiliary controller 132 connected between the capacitors C.sub.DC and C.sub.CTRL, and a timer 135.

(22) The DC regulator 130 drains current from the rectified power line LEDP through the current-limiting resistor R.sub.IN to charge the capacitor C.sub.DC and to regulate an operational voltage V.sub.DC on the capacitor C.sub.DC. For example, the DC regulator 130 has a depletion-mode NMOS transistor, whose gate is initially shorted to the ground power line, so the depletion-mode NMOS transistor is automatically turned OFF when the operational voltage V.sub.DC rises to about 5V. The operational voltage V.sub.DC is the power source for the initial condition checker 131, the timer 135 and the bias-setting circuit 136.

(23) The bias-setting circuit 136 might include a bandgap reference circuit to provide predetermined reference voltages and currents used for setting bias conditions in some internal circuits when the operational voltage V.sub.DC is stable at 5V.

(24) The initial condition checker 131 is coupled to the voltage detector 112, for comparing the line voltage V.sub.LEDP with an initial voltage, which might be determined by the detection resistor R.sub.DET and a reference current from the bias-setting circuit 136. For example, the initial condition checker 131 compares the line voltage V.sub.LEDP with 50V, and if the line voltage V.sub.LEDP has exceeded 50V, it signals the timer 135.

(25) The timer 135 has an oscillator 133 and a counter 134, for timing a predetermined period as a delay. After signaled by the initial condition checker 131, the oscillator 133 starts oscillating, and the counter 134 counts accordingly to determine whether the predetermined period elapses. If the predetermined period has passed, the timer 135 signals the auxiliary controller 132. This predetermined period could be 0.5 s, for example.

(26) The auxiliary controller 132 controls the connection between the capacitors C.sub.DC and C.sub.CTRL, and is capable of controlling the ramp-up rate of the operational voltage V.sub.CTRL on the capacitor C.sub.CTRL, where the operational voltage V.sub.CTRL powers the current regulator 114 (a part of the LED driver DRV) and the line-voltage controller 118. Initially, the operational voltage V.sub.CTRL is 0V. After signaled by the timer 135, the auxiliary controller 132 starts charging the capacitor C.sub.CTRL by turning ON a switch between the capacitors C.sub.DC and C.sub.CTRL, and the operational voltage V.sub.CTRL ramps up accordingly while the ramp-up rate is under control. In one embodiment, it takes 1 sec for the operational voltage V.sub.CTRL to reach 5V from 0V, and the LED driver DRV in FIG. 4 and the line-voltage controller 118 in FIG. 5 starts their normal operations when the operational voltage V.sub.CTRL is about 5V.

(27) FIG. 7 shows a control method 180 used by the LED lamp arrangement 100 in FIGS. 1A and 1B. Please also take reference to FIGS. 1A, 1B, and 2-6.

(28) Step 140 starts powering a luminaire with the LED lamp arrangement 100 and a ballast, electronic or magnetic, by connecting the luminaire to mains power supply 20, which provides an AC voltage between inputs BSTP and BSTN.

(29) In step 141, the rectifier 110 rectifies to generate a DC line voltage V.sub.LEDP and a ground voltage at the rectified power line LEDP and the ground power line respectively. Meanwhile, the integrated circuit 102 keeps the power transistor 106 OFF, and operational voltages V.sub.DC and V.sub.CTRL are about 0V.

(30) In step 142, the DC regulator 130 starts draining current from the rectified power line LEDP to charge the capacitor C.sub.DC and to regulate the operational voltage V.sub.DC at 5V.

(31) When the operational voltage is about 5V, the bias-setting circuit 136 starts providing predetermined reference voltages and currents used for setting bias conditions in step 144.

(32) In step 146, as bias conditions has been set up, the initial condition checker 131 compares the line voltage V.sub.LEDP, with an initial voltage, which is 50V for example in the following embodiments. A properly-powered ballast, whether it is electronic or magnetic, should provide an AC voltage with an amplitude over 100V to the inputs BSTN and BSTP of the rectifier 110, so step 146 confirms whether the ballast has started powering the LED lamp arrangement 100. Step 146 repeats if the line voltage V.sub.LEDP is below 50V. Otherwise the initial condition checker 131 signals the timer 135, proceeding step 148.

(33) Please note that in steps 140, 141, 142, 144 and 146, the LEDs do not light, and the integrated circuit 102 preferably limits the consumption current I.sub.LEDP output from the rectifier 110 no more than 50 uA.

(34) After signaled by the initial condition checker 131, step 148 starts the oscillator 133 oscillating, and step 150 starts the counter 134 counting to time a predetermined period, which is a 0.5 s for example in the following description. Steps 148 and 150 provide a delay of 0.5 s, in other words.

(35) Steps 148 and 150 keep the consumption current I.sub.LEDP in a range of 70 uA to 200 uA while the LEDs 104 do not light. In other words, the LED lamp arrangement 100 consumes more than 50 uA but less than 200 uA within the 0.5 s after the line voltage V.sub.LEDP reaches 50V. This constraint in current consumption could help avoiding the triggering of short or open circuit protection provided by some advanced electronic ballasts. An electronic ballast might check in the beginning whether its output current is too small, and shut down its output voltage and current if the answer is positive, so as to provide open circuit protection. Similar with the open circuit protection, short circuit protection means shutting down the output voltage and current of an electronic ballast when finding in the beginning its output current too much. It is believed that most electronic ballasts verify their output current within 0.5 s after power-up, to determine whether to trigger open or short circuit protection, and that the consumption current I.sub.LEDP, if limited between 70 uA to 200 uA, will not trigger open or short circuit protection of most electronic ballasts. In some other embodiments, this delay of 0.5 s and the range of 70 uA to 200 uA might change to be other values.

(36) In step 162, the auxiliary controller 132 starts connecting capacitor C.sub.CTRL with capacitor C.sub.DC, and limiting the ramp-up rate of the operational voltage V.sub.CTRL. For example, it takes at least several milliseconds for the operational voltage V.sub.CTRL to reach 5V from 0V.

(37) In step 164, the LED driver DRV in FIG. 4 and the line-voltage controller 118 in FIG. 5 starts operating.

(38) Soft startup could be introduced into the operation of the LED driver DRV in FIG. 4. For example, the setting voltage V.sub.SET in FIG. 4 might take 1 sec to rise from 0V to its target value, 0.5V for example, while the operational amplifiers OP1 and OP2 well control the power transistors 106 and MN LED respectively. The LEDs 104, as a result, is slowly turned ON because the LED driving current I.sub.LED is 0 A in the beginning and increases gradually to reach its default value one second after the operational voltage V.sub.CTRL is 5V.

(39) As the operational voltage V.sub.CTRL reaches 5V, the line-voltage controller 118 starts controlling the impedance balance circuit 119 to make the line voltage V.sub.LEDP the predetermined target voltage. For example, in one embodiment, the forward voltage of the LEDs 104 is 140V, and the predetermined target voltage 130V, meaning the line voltage V.sub.LEDP is regulated by the line-voltage controller 118 to be about 130V. Without the line-voltage controller 118 and the impedance balance circuit 119, the line voltage V.sub.LEDP could be as high as 200V or more, and much wasted heat and energy will be generated by the power transistors 106 and due to the high voltage drop MN.sub.LED across them. When the line voltage V.sub.LEDP is regulated by the line-voltage controller 118 and the impedance balance circuit 119 to be slightly above the forward voltage of the LEDs 104, the power transistors 106 and MN.sub.LED produce less heat, and the LEDs 104 is driven efficiently.

(40) The LED lamp arrangement 100 according to the embodiments of the invention is suitable to replace a fluorescent lamp in a luminaire having a ballast for supplying power to the fluorescent lamp, no matter whether the ballast is electronic or magnetic. The constraint on the consumption current V.sub.LEDP during the delay of 0.5 sec provided by the timer 135 helps avoid triggering the short or open circuit protection of an electronic ballast. The line voltage V.sub.LEDP could be regulated at a voltage slightly higher than the forward voltage of the LEDs 104, so the LEDs 104 is driven efficiently.

(41) While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

(42) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.