System on chip comprising a plurality of master resources

Abstract

This system on chip comprises a plurality of master resources, a plurality of slave resources, a plurality of arbitration levels, each arbitration level being able to control the access of at least one master resource to at least one slave resource, each master resource being able to send requests to at least one slave resource according to a bandwidth associated with this slave resource and this master resource. The system is characterized by further comprising control means configured to control each bandwidth associated with each slave resource as a function of the capacity of this slave resource to process the requests originating from the master resource corresponding to this bandwidth.

Claims

1. A system on chip comprising: a plurality of master resources for aeronautical applications; a plurality of slave resources for aeronautical applications; a plurality of arbitration levels, each arbitration level being able to control access of at least one master resource to at least one slave resource; wherein each master resource is configured to send requests to at least one slave resource of the plurality of slave resources according to a bandwidth associated with a slave resource and a master resource, each request transmitting digital data or interrogating the slave resource, and being transmitted via at least one arbitration level; and a controller configured to control each bandwidth associated with each slave resource based on a processing capacity of the slave resource allocated to process requests received from the master resource, and to control the request of each master resource to the corresponding slave resource based on the bandwidth control; wherein the controller forms a separated unit from each master resource and each slave resource.

2. The system according to claim 1, wherein each slave resource comprises a buffer memory capable of storing requests to be processed by this slave resource and defining a total capacity for processing requests; each slave resource being able to allocate for each master resource a capacity for processing requests from this master resource as a function of its total capacity for processing requests.

3. The system according to claim 2, wherein the processing capacity allocated to each master resource by a slave resource is obtained by dividing the total capacity for processing requests by this slave resource, by a number of master resources capable to use this slave resource.

4. The system according to claim 2, wherein each slave resource is able to send to the controller a full signal when the processing capacity allocated to a master resource is full.

5. The system according to claim 4, wherein, upon reception of a full signal, the controller is capable of inhibiting an emission of new requests by the master resource corresponding to this full signal.

6. The system according to claim 1, wherein the controller is capable of defining for each master resource a maximum rate of emission of the requests intended for each slave resource.

7. The system according to claim 1, further comprising a synchronizer capable of detecting an output of each request from a master resource and intended for a slave resource, through all of the corresponding arbitration levels.

8. The system according to claim 7, wherein the controller is able to authorize an emission of a new request by a master resource only when the synchronizer detects the output of a previous request from this master resource, through all of the corresponding arbitration levels.

9. The system according to claim 1, wherein each master resource is chosen from a group comprising: a computing core; a graphics processor; a direct memory access unit.

10. The system according to claim 1, wherein the slave resource is a peripheral.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) These characteristics and advantages of the invention will become apparent upon reading the description which follows, given solely by way of non-limiting example, and made with reference to the appended drawings, in which:

(2) FIG. 1 is a schematic view of a system on chip according to a first mode and a second embodiment of the invention; and

(3) FIG. 2 is a schematic view of a system on chip according to a third embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

(4) FIG. 1 shows a system on chip 10 according to a first and a second embodiment of the invention.

(5) This system 10 comprises M resources R.sub.1, . . . , R.sub.M and N arbitration levels A.sub.1, . . . , A.sub.N, the numbers M and N being strictly greater than 1.

(6) At least two of the resources R.sub.1, . . . , R.sub.M, called master resources, are capable of interrogating at least two other resources R.sub.1, . . . , R.sub.M, then called slave resources, by sending them requests. The slave resources are therefore able to process the requests received from the corresponding master resources.

(7) The sending of requests is carried out according to a bandwidth associated with the slave resource receiving this request and the master resource sending this request.

(8) A resource R.sub.1, . . . , R.sub.M may simultaneously present both a master resource for certain resources R.sub.1, . . . , R.sub.M or a slave resource for certain other resources R.sub.1, . . . , R.sub.M, as will be explained in detail below.

(9) Thus, for example, a resource R.sub.1, . . . , R.sub.M corresponding to a computing core or to a graphics processor is always considered to be a master resource.

(10) On the other hand, a resource R.sub.1, . . . , R.sub.M corresponding to a peripheral or to a Direct Memory Access (DMA) unit may present a master resource for at least some of the resources R.sub.1, . . . , R.sub.M and a slave resource for certain other resources R.sub.1, . . . , R.sub.M.

(11) Each resource R.sub.1, . . . , R.sub.M is identified within the system on chip 10 by a unique identifier.

(12) Furthermore, each resource R.sub.1, . . . , R.sub.M includes a buffer memory capable of storing requests to be processed and/or requests to be sent.

(13) This buffer memory defines a total capacity for processing requests by the corresponding resource and is implemented based on the First In First Out (FIFO) principle.

(14) All of the arbitration levels A.sub.1, . . . , A.sub.N form a component referred to as “InterConnect” in the prior art.

(15) In particular, each arbitration level A.sub.1, . . . , A.sub.N may be, for example, in the form of one or more access buses making it possible to control the access rights of a master resource to a slave resource.

(16) In other words, the transmission of requests from a master resource to a slave resource is always carried out via n arbitration levels where the number n is greater than or equal to 1 and less than or equal to N.

(17) In addition, the arbitration levels A.sub.1, . . . , A.sub.N are distributed hierarchically between them.

(18) Just like the resources R.sub.1, . . . , R.sub.M, each arbitration level A.sub.1, . . . , A.sub.N comprises a buffer memory per link capable of storing requests to be transmitted to the higher arbitration level and/or to the lower arbitration level and/or associated slave resources.

(19) Each resource R.sub.1, . . . , R.sub.M is associated with one of the arbitration levels A.sub.1, . . . , A.sub.N and is able to receive requests transmitted by this arbitration level and/or to send requests to this arbitration level.

(20) In particular, each arbitration level A.sub.1, . . . , A.sub.N is able to transmit a request to a resource R.sub.1, . . . , R.sub.M associated with this arbitration level A.sub.1, . . . , A.sub.N when this request comes from a resource R.sub.1, . . . , R.sub.M associated with this same arbitration level A.sub.1, . . . , A.sub.N or with a higher arbitration level A.sub.1, . . . , A.sub.N.

(21) Thus, the arbitration levels A.sub.1, . . . , A.sub.N define the hierarchy between the resources R.sub.1, . . . , R.sub.M and in particular, the capacity of each resource R.sub.1, . . . , R.sub.M to be a master resource or a slave resource with respect to each other resource R.sub.1, . . . , R.sub.M of the system 10.

(22) In the example of FIG. 1, the resources R.sub.1 to R.sub.4 are associated with the arbitration level A.sub.1 and have computing cores. These resources are therefore always master resources.

(23) The resource R.sub.5 also associated with the arbitration level A.sub.1 has a cache memory for example of level 2. It is therefore capable of processing requests originating from resources R.sub.1 to R.sub.4 and is considered by these resources R.sub.1 to R.sub.4 to be a slave resource.

(24) Similarly, the resource R.sub.M associated with the arbitration level A.sub.N and having a DMA unit, is considered to be a master resource by the resource R.sub.7 associated with the same arbitration level A.sub.N and presenting a peripheral.

(25) Throughout the text, when a master resource is mentioned, it is understood that this resource is considered to be a master resource by at least one other resource. Similarly, when mention is made of a slave resource, it is understood that this resource is considered to be a slave resource by at least one other resource.

(26) According to the invention, the system 10 further comprises control means 20 configured to control each bandwidth associated with each slave resource as a function of the capacity of this slave resource to process requests from the master resource corresponding to this bandwidth.

(27) In other words, the control means 20 make it possible to control the bandwidth to each slave resource from each master resource.

(28) To do this, these control means 20 are in the form of a controller integrated into the system on chip 10, connected to each master resource and configured to control the transmission of requests by each master resource using one of the techniques described below. Such a controller can be formed by a software or, for example, by programmable circuits.

(29) In particular, according to the first embodiment of the invention, each slave resource is configured to allocate for each master resource a capacity for processing requests originating from this master resource as a function of its total capacity for processing requests.

(30) This allocation is, for example, carried out at the design stage of the system 10 and is, for example, frozen during the operation of the system 10. It may be, for example, kept within each slave resource in the form of a table comprising the identifier of each master resource with the processing capacity allocated to this master resource.

(31) The processing capacity allocated to each master resource by a slave resource is obtained, for example, by dividing the total processing capacity of requests by this slave resource, by the number of master resources capable of using this slave resource.

(32) In this case, each slave resource is able to send to the control means 20 a full signal when the processing capacity allocated to a master resource is full.

(33) Upon receipt of a full signal, the control means 20 are able to inhibit the transmission of new requests by the master resource corresponding to this full signal.

(34) In other words, according to the first embodiment, the control means 20 inhibit the transmission of each new request by a master resource to a slave resource when the processing capacity allocated by the slave resource to this master resource is full.

(35) When this processing capacity is restored to normal, the slave resource is able, for example, to send a corresponding signal to the control means 20 which lift the ban on the transmission of requests by the corresponding master resource.

(36) According to a second embodiment, the control means 20 are able to define for each master resource, a maximum rate of transmission of the requests intended for each slave resource.

(37) These maximum transmission rates are defined, for example, at the design stage of the system 10 as a function of the bandwidths of the various arbitration levels and of the master resources, of the processing capacities by the slave resources, as well as of the number of these elements.

(38) Thus, the maximum emission rates for each master resource with regard to each slave resource are, for example, kept in the form of a table by the control means 20 and are, for example, frozen during the operation of the system 10.

(39) According to this embodiment, the control means 20 inhibit the transmission of requests by a master resource to a slave resource when the rate of their transmission exceeds the maximum rate of transmission defined for this master resource and this slave resource.

(40) FIG. 2 shows a system on chip 110 according to a third embodiment.

(41) This system 110 is analogous to the system 10 described with reference to FIG. 1 and comprises, as in the previous case, M resources R.sub.1, . . . , R.sub.M and N arbitration levels A.sub.1, . . . , A.sub.N analogous to those described above.

(42) This system 110 also comprises control means 120 configured to control each bandwidth associated with each slave resource as a function of the capacity of this slave resource to process the requests originating from the master resource corresponding to this bandwidth.

(43) The system 110 according to the third embodiment further comprises synchronization means 130, called also synchronizer. Such a synchronizer can be formed by a software or physical programmable circuits.

(44) These synchronization means 130 are able to detect the output of all the arbitration levels A.sub.1, . . . , A.sub.N corresponding to each request from a master resource and intended for a slave resource.

(45) To do this, the synchronization means 130 define, for example, an input observer at each input of each of the arbitration levels A.sub.1, . . . , A.sub.N and an output observer at each output of each of the arbitration levels A.sub.1, . . . , A.sub.N.

(46) When an output observer detects a request detected beforehand by an input observer, the synchronization means 130 conclude that the corresponding request has left all the arbitration levels A.sub.1, . . . , A.sub.N and is therefore consumed by the destination slave resource.

(47) In this case, the control means 120 are able to authorize the transmission of a new request by a master resource to a slave resource only when the synchronization means 130 detect the output of all the arbitration levels A.sub.1, . . . , A.sub.N corresponding to a previous request from this master resource and intended for this slave resource.

(48) It should therefore be understood that the present invention offers a number of advantages.

(49) In particular, the control of the transmission of requests by each master resource to a slave resource according to the first embodiment of the invention makes it possible to avoid saturation at the input of this slave resource. This thus decreases the probability of saturation of the arbitration levels leading to this slave resource.

(50) In the second embodiment, the probability of saturation of the arbitration levels is reduced because the maximum rates defined for each master resource take into account the bandwidths of each of the elements used to transmit the requests as well as the processing capacities of these requests by slave resources.

(51) Finally, in the third embodiment, the saturation of the arbitration levels is practically excluded by synchronizing the inputs and outputs of the requests.

(52) Thus, each of these embodiments makes it possible to solve the problems linked to the temporal non-determinism of execution of systems on chip in the multi-master context.

(53) Of course, it is also possible to provide other embodiments.

(54) In particular, some of these embodiments may correspond to combinations of the embodiments described above.