Method and circuit for integrating a programmable matrix in the field of reconfigurable logic gates employing a non-lineal system and an efficient programmable rewiring

Abstract

The present invention relates to the field of reconfigurable computing also known as dynamic computing and, more particularly, to reconfigurable architectures logic gates and programmable wiring connections between them and the input interfaces and output interfaces. There is growing interest in developing new hardware architectures to complement or replace existing static architectures, and recently, there has been a theoretical direction to explore the richness of nonlinear dynamical systems to implement reconfigurable hardware (dynamic). The present invention is to use a nonlinear to emulate different logic gates dynamic system that are the basis of general-purpose computing, and after obtaining the logic gates, integrate these elements into a programmable device by the user, ie for create a field programmable array of reconfigurable logic gates.

Claims

1. A programmable array field matrix of reconfigurable logic gates, the matrix comprising: at least two reconfigurable logic gates connected to each other using a programmable rewiring, wherein a plot of each logic gate directs an output of the reconfigurable logic gates to at least one input interface block or towards an output interface block, wherein blocks inlet and outlet are placed on a periphery of the matrix; wherein each reconfigurable logic gate of the matrix forming the field programmable reconfigurable logic gates employs a circuit having three blocks: a) an input block, b) an adder block, and c) an output window detector block; wherein each reconfigurable logic gate forming the field programmable matrix of reconfigurable logic gates is characterized in that the input block has at least two signal inputs for the operation of the reconfigurable logic gate; and two comparators one for each input of the logic gate, in order to receive two logic signals respectively through inputs; the two logic signals are received, then a decision tree starts where: i) If the input signal is greater than the reference voltage, then the output signal of the first comparator is set to a predefined voltage; ii) If the input signal is less than the reference voltage, then the output signal of the first comparator is zero volts; iii) If the input signal is greater than the reference voltage, then the output signal of the second comparator is set to a predefined voltage; iv) If the input signal is less than the reference voltage, then the output signal of the second comparator is zero volts; wherein the adder block receives the output signals of the comparators respectively in the input blocks and a compensation signal, the compensation signal is a control parameter for programming of logical operation of the reconfigurable logic gate and gets the different logical operations; the output of the adder block is a result of adding the signals from the comparators and the compensation signal, and wherein said sum is performed by an adder in the adder block; and the output window detector block comprises a comparator block defining a logical level at the output as follows: d) if the absolute value of the sum obtained by the adder block is less than the window detector block reference; then a “high” logic level is obtained at the output; and e) if the absolute value of the sum obtained by the adder block is greater than the window detector block reference; then a logic “low” is obtained at the output.

2. The matrix according to claim 1, wherein the reconfigurable logic gates forming the field programmable matrix of reconfigurable logic gates change their behavior to get a different logical operation when the control parameter is varied by defining voltage values for each logical operation; each reconfigurable logic gate performs up to five different operations in the following list: a. AND gate, if the associated voltage is −4.0V b. OR gate, if the associated voltage is −3.0V c. XOR gate, if the associated voltage is −2.0V d. NAND gate, if the associated voltage is −1.0V e. NOR gate, if the associated voltage is 0.0V.

3. The matrix according to claim 1, wherein each reconfigurable logic gate forming the field programmable matrix of reconfigurable logic gates has its own control parameter to define their behavior, and each can perform any of the five logical operations by varying the control parameter; characterized in that the five voltage values necessary to achieve the multi-functionality are delivered by a voltage source; the voltage values are introduced to the inputs of at least two analog multiplexers; to choose the desired output of each analog multiplexer that is delivered to the same number of signals that are identified as control parameters, a control word is used to program each voltage analog multiplexer; wherein a control word has three bits for each of the analog multiplexers.

4. The matrix according to claim 3, wherein the programmable rewiring between each of the reconfigurable logic gates is characterized in that the input block receives the total amount of external signals passing at least a first pair of digital multiplexers M1 and M2; then a container block stores all outputs of different reconfigurable logic gates; and these outputs are connected to at least a second pair of multiplexers M3 and M4; then, the output of multiplexer M1 along with the output of multiplexer M3 are connected to a fifth multiplexer M5, while the output of multiplexer M3 together with the output of multiplexer M4 are connected to a sixth multiplexer M6; a first controller is used to send a control word of m bits multiplexers M1 and M3, and also sends an additional bit multiplexer M5; then a second controller is used to send a control word of m bits to the M2 and M4 multiplexers, and also sends an additional bit multiplexer M6; the output of multiplexer M5 is connected to the first input of the reconfigurable logic gate and the output of multiplexer M6 is connected to the second input of reconfigurable logic gate; in order to observe the outputs of the reconfigurable logic gates, these signals are output to the block that provides the user the ability to track.

5. A control system for a matrix as described in claim 3, wherein the reconfigurable logic gates are independent.

6. The control system in accordance with claim 5, wherein a control word is used to control an analog multiplexer where a selectable voltage signal required.

7. The control system according to claim 5, wherein the programmable rewiring between each of the reconfigurable logic gates comprises the input block that receives the total amount of external signals passing at least a first pair of digital multiplexers M1 and M2; then a container block stores all outputs of different reconfigurable logic gates; and these outputs are connected to at least a second pair of multiplexers M3 and M4; then, the output of multiplexer M1 along with the output of multiplexer M3 are connected to a fifth multiplexer M5, while the output of multiplexer M3 together with the output of multiplexer M4 are connected to a sixth multiplexer M6; a first controller is used to send a control word of m bits multiplexers M1 and M3, and also sends an additional bit multiplexer M5; then a second controller is used to send a control word of m bits to the M2 and M4 multiplexers, and also sends an additional bit multiplexer M6; the output of multiplexer M5 is connected to the first input of the reconfigurable logic gate and the output of multiplexer M6 is connected to the second input of reconfigurable logic gate; in order to observe the outputs of the reconfigurable logic gates, these signals are output to the block that provides the user the ability to track, and wherein the reconfigurable logic gates are independent.

8. The control system for programming the rewiring between reconfigurable logic gates in accordance with claim 7, wherein said control system employs at least one pair of control words to control digital multiplexers that define the signals coming to the inputs of the logic gates reconfigurable.

9. A programmable array field matrix of reconfigurable logic gates, the matrix comprising: at least two reconfigurable logic gates connected to each other using a programmable rewiring, wherein a plot of each logic gate directs an output of the reconfigurable logic gates to at least one input interface block or towards an output interface block, wherein blocks inlet and outlet are placed on a periphery of the matrix; wherein each reconfigurable logic gate of the matrix forming the field programmable reconfigurable logic gates employs a circuit having three blocks: a) an input block, b) an adder block, and c) an output window detector block; wherein in order to rewire the outputs of the reconfigurable logic gates at the entrance of the configurable logic gates the input block receives the total amount of external signals passing at least a first pair of digital multiplexers M1 and M2; then a container block stores all outputs of different reconfigurable logic gates; and the outputs are connected to at least a second pair of multiplexers M3 and M4; then, the output of multiplexer M1 along with the output of multiplexer M3 are connected to a fifth multiplexer M5, while the output of multiplexer M3 together with the output of multiplexer M4 are connected to a sixth multiplexer M6; a first controller is used to send a control word of m bits multiplexers M1 and M3, and also sends an additional bit multiplexer M5; then a second controller is used to send a control word of m bits to the M2 and M4 multiplexers, and also sends an additional bit multiplexer M6; the output of multiplexer M5 is connected to the first input of the reconfigurable logic gate and the output of multiplexer M6 is connected to the second input of reconfigurable logic gate; in order to observe the outputs of the reconfigurable logic gates, the signals are output to the block that provides the user the ability to track.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) FIG. 1 is a diagram of the architecture of the reconfigurable logic gate array employing a nonlinear system and an effective programmable rewiring;

(2) FIG. 2 is a block diagram of a reconfigurable logic gate within the matrix of reconfigurable logic gates which employs a nonlinear system and an effective programmable rewiring;

(3) FIG. 3 is a block diagram showing the implementation of the selection of the control parameter for a reconfigurable logic gate within the matrix of reconfigurable logic gates which employs a nonlinear system and an effective programmable rewiring;

(4) FIG. 4 is the experimental response of a reconfigurable logic gate taking the logical AND within the matrix of reconfigurable logic gates which employs a nonlinear system and an effective programmable rewiring. The upper trace represents the input signal x.sub.1. The middle line represents the input signal x.sub.2. The bottom line represents the output;

(5) FIG. 5 is the response of a reconfigurable experimental logic gate taking the logical OR within the matrix of reconfigurable logic gates which employs a nonlinear system and an effective programmable rewiring. The upper trace represents the input signal x.sub.1. The middle line represents the input signal x.sub.2. The bottom line represents the output;

(6) FIG. 6 is the response of a reconfigurable experimental logic gate taking the logical XOR within the matrix of reconfigurable logic gates which employs a nonlinear system and an effective programmable rewiring. The upper trace represents the input signal x.sub.1. The middle line represents the input signal x.sub.2. The bottom line represents the output;

(7) FIG. 7 is the response of a reconfigurable experimental logic gate taking the logical NAND within the matrix of reconfigurable logic gates which employs a nonlinear system and an effective programmable rewiring. The upper trace represents the input signal x.sub.1. The middle line represents the input signal x.sub.2. The bottom line represents the output;

(8) FIG. 8 is the response of a reconfigurable experimental logic gate taking the logical NOR within the matrix of reconfigurable logic gates which employs a nonlinear system and an effective programmable rewiring. The upper trace represents the input signal x.sub.1. The middle line represents the input signal x.sub.2. The bottom line represents the output; and

(9) FIG. 9 is a block diagram representing the implementation of programmable rewiring block used in the reconfigurable logic gates matrix employing a nonlinear system and an effective programmable rewiring.

(10) Based on the above figures, the matrix of reconfigurable logic gates that employs a nonlinear system and an efficient programmable rewiring comprises a set of reconfigurable logic gates with reconfigurable interconnections between them and with external signals. That is, this matrix allows a double programming generally described as:

(11) First Programming:

(12) Cada compuerta lógica reconfigurable se puede programar para implementar varias operaciones lógicas después de que un parámetro de control se ha establecido. El diseño de cada compuerta lógica reconfigurable comprende tres bloques: a) an input block of reprogrammable logic gate, b) an adder block accompanied by a compensation signal (defined as control signal) to determine the behavior of the reconfigurable logic gate. c) a output window detector block with a threshold reference signal defining the logical level at the output.

(13) Where the input block of the reconfigurable logic gate has a pair of comparators that determine whether the input voltages are signal “high” or signal “low”, ie, determine whether it is logic one or a logic zero, respectively;

(14) Said first summing block sums the output signals from the input block and a voltage compensation and then inverts that sum. Said detector block output window determines whether the output of adder block falls in a range defined by a voltage set by the user, generating a “high” level when the signal received from adder block is in the range; by setting a compensation voltage (control signal) can be obtained from the following logical operations: An AND gate (see FIG. 4); An OR gate (see FIG. 5); An XOR gate (see FIG. 6); A NAND gate (See FIG. 7); A NOR gate (see FIG. 8); A NOT gate.

(15) Second Programming:

(16) The complete set of reconfigurable logic gates described above can be configured to interconnect the reconfigurable logic gates with each other, or to the input and output blocks. This process of rewiring programmable provides the ability to implement complex logic function and allows the user to interact with external signals. This allows different functions such as: a) acquire data from the array of reconfigurable logic gates; b) introducing a signal from a function generator.

(17) OBSERVATION. In order to clearly present the elements of this application; examples are only declarative more Nonlimiting be described, since both conducting and operation of the invention, are achievable in different ways and, since the structural details should be interpreted as the justification for the technical effects obtained to support the claims so which they are merely representative of the technical feature and novel implications comprising.

(18) The matrix consists of reconfigurable logic gates (each can be programmed to perform logic functions: AND, OR, NAND, NOR, XOR o NOT); a block of reconfigurable rewiring; a block of input interface; a block output interface; the latter two are used to communicate the device with external devices and vice versa, so that may be considered conventional.

(19) As shown in FIG. 1, this general representation is a block diagram showing the architecture of the programmable array field of reconfigurable logic gates 100, wherein the matrix comprises at least two reconfigurable logic gates 101 (this first embodiment comprises four, arranged in arrays of two rows by two columns) connected to each other using a programmable rewiring 102 which directs the outputs frame reconfigurable logic gates 101, to at least one input interface block 103 to a block or output interface 104. The input block 103 and outlet block 104 are preferably placed on the periphery of the array 100.

(20) Now in a first approach to the operation of the array 100, it uses a circuit for the logic gate reconfigurable 101 (see FIG. 2) which consists of three blocks: a first identified as input block 200 of the logic gate block reconfigurable 101, a second adder block called block 216, and a third block called output window detector block 217. the input block 200, has at least two input signals 203 and 205 entering the reconfigurable logic gate 101; also it has two comparators 201 and 202 in order to receive two logic signals through inputs 203 and 205, respectively; once you received the latter a decision tree starts where: a) If the input signal 203 is greater than the reference voltage 204, then the output signal 208 of comparator 201 is set to the voltage 206; b) If the input signal 203 is less than the reference voltage 204, then the output signal 208 obtained is zero volts; c) If the input signal 205 is greater than the reference voltage 204, then the output signal 209 of comparator 202 is set to the voltage 207; d) If the input signal 205 is less than the reference voltage 204, then the output signal 209 obtained is zero volts;

(21) Now the summing block 216 receives signals 208 and 209 output of the comparator blocks 201 and 202 respectively in one of its inputs and a third, the compensation signal 211 is received; This compensation signal is the control parameter allows you to program the logic operation of the reconfigurable logic gate 101, ie, it is possible to obtain different logical operations only by adjusting the control parameter (see FIG. 4 to FIG. 8). The output of summing block 212 is the result of adding the respective signals 208, 209 and 211. This sum is performed by the adder 210 in the summing block 216. Finally, the third block, identified as output window detector 217, It comprises a comparator 213 which defines a logical level at the output 215 as follows: a) if the absolute value of the sum obtained by the adder block 216 represented by the output signal 212 is less than the reference 214, of the window detector block 217; then a “high” logic level is obtained at the output 215; b) if the absolute value of the sum obtained by the adder block 216 represented by the output signal 212 is above the reference 214, of the window detector block 217; then a logic “low” is obtained at the output 215;

EXAMPLE 1

(22) An example for implementing reconfigurable circuit logic gate 101 shown in FIG. 2, since it is a detail view of the reconfigurable logic gate 101 consisting of three blocks: a) input block 200 of the reconfigurable logic gate 101, b) summing block 216, and c) output window detector block 217.

(23) Among them, the signal inputs 203 and 205 which enter the reconfigurable logic gate 101 through the input block are appreciated. The input block includes the two comparators 201 and 202 which are connected to each input of the reconfigurable logic gate 101 for receiving the two logic input signals, which are denoted by 203 and 205.

(24) Each reconfigurable logic gate 101 can change their behavior to make a different logic operation when the control parameter 211 is varied; to achieve this purpose voltage values for each logical operation are defined; thus, each reconfigurable logic gate 101 can perform up to five different operations depending on the voltage 211, which is selected according to Table 1.

(25) TABLE-US-00001 TABLA 1 Tabla de voltajes definidos correspondientes a cada operación lógica. Associated V.sub.AND V.sub.OR V.sub.XOR V.sub.NAND V.sub.NOR logic operation Corresponding −4.0 V −3.0 V −2.0 V −1.0 V 0.0 V voltage

(26) The programmable array of field reconfigurable logic gates (FPRGA) 100 consists of a set of reconfigurable logic gates 101, where each 101.sub.i can act independently to adjust their own control parameter 211.sub.i (Hereinafter, the subscript i ranges from 1 to n).

(27) Embodiment of the “n” Logic Gates.

(28) Reconfigurable logic gates have similar characteristics, so that only the preferred will be described.

(29) Each logic gate reconfigurable 101; has its own control parameter 211.sub.i, then each of them can perform any of the five logical operations (AND, OR, XOR, NAND, NOR) simply by varying the control parameter 211.sub.i according to voltage values shown in Table 1. to achieve this multifunctionality, the five voltage values required are delivered by a voltage source 301; these voltage values to the inputs of at least two analog multiplexers 302.sub.i (remember the subscript i ranges from 1 to n) are introduced. To choose the desired output voltage, each analog multiplexer 302.sub.i delivers the same number of signals that are identified as control parameters 211.sub.i, a control word 303 is used to program each analog multiplexers 302.sub.i; in this embodiment, a control word 303 consists of three bits for each of the analogue multiplexers 302.sub.i.

(30) A set of experimental responses reconfigurable logic gates 101, shown in FIGS. 4, 5, 6, 7 and 8. For each different logical operations that can be implemented, in the figures we can see that each reconfigurable logic gate 101 has two inputs x.sub.1 and x.sub.2, which for purposes of description are identified as 203 and 205. If it is considered an array of “n” reconfigurable logic gates 101, each with inputs x.sub.1 and x.sub.2, then to “n” gates 2n reconfigurable logic inputs are taken. For the interpretation of the signals, the top line is identified as the x.sub.1 input (denoted as 203), the middle line corresponds to the input x.sub.2 (denoted as 205) and the bottom line (identified as 215) corresponds to the output signal of the reconfigurable logic gate 101.

(31) Using the voltage values defined in Table 1, it can then note that: FIG. 4 if the voltage V.sub.AND is used, then the output signal 215 corresponds to the operation AND. FIG. 5 if the voltage V.sub.OR is used, then the output signal 215 corresponds to the operation OR. FIG. 6 if the voltage V.sub.XOR is used, then the output signal 215 corresponds to the operation XOR. FIG. 7 if the voltage V.sub.NAND is used, then the output signal 215 corresponds to the operation NAND. FIG. 8 if the voltage V.sub.NOR is used, then the output signal 215 corresponds to the operation NOR.

(32) Finally, the rewiring programmable array 102 for field programmable reconfigurable logic gates 100 (FPRGA type) shown in FIG. 9 as a declarative, but not limited choice, below it is presented specifically for one of the reconfigurable logic gates 101.sub.i, but it should be noted that it can be implemented for n reconfigurable logic gates.

(33) First, the input block 103 receives the total 2n external signals, they pass through at least a first pair of digital multiplexers 502a.sub.i and 502b.sub.i; then a container block 501 stores all n outputs 215.sub.i of the n different reconfigurable logic gates 101.sub.i; the n outputs 215.sub.i are connected to at least a second pair of digital multiplexers 503a; y 503b.sub.i; then, the outputs of the multiplexers 502a.sub.i y 503a.sub.i are connected to a fifth digital multiplexer 504a.sub.i, while the outputs of the multiplexers 502b.sub.i y 503b.sub.i are connected to a sixth digital multiplexer 504b.sub.i; a first controller 505a.sub.i is used to send a control word of m bits to the multiplexers 502a.sub.i y 503a.sub.i but also an additional bit is sent to multiplexer 504a.sub.i; a second controller 505b.sub.i is used to send a control word of m bits to the multiplexers 502b.sub.i y 503b.sub.i, but also an additional bit is sent to the multiplexer 504b.sub.i; the output of the multiplexer 504a.sub.i is connected to the input 203.sub.i of reconfigurable logic gate 101.sub.i and the output of the multiplexer 504b.sub.i is connected to the input 205.sub.i of the reconfigurable logic gate 101.sub.i; finally, in order to observe the 215.sub.i n outputs of the n reconfigurable logic gates 101.sub.i, these signals are sent to the output block 104 which provides the user the ability for tracking.