Stress mitigating amorphous SiO2 interlayer

Abstract

A method of forming a REO dielectric layer and a layer of a-Si between a III-N layer and a silicon substrate. The method includes depositing single crystal REO on the substrate. The single crystal REO has a lattice constant adjacent the substrate matching the lattice constant of the substrate and a lattice constant matching a selected III-N material adjacent an upper surface. A uniform layer of a-Si is formed on the REO. A second layer of REO is deposited on the layer of a-Si with the temperature required for epitaxial growth crystallizing the layer of a-Si and the crystallized silicon being transformed to amorphous silicon after transferring the lattice constant of the selected III-N material of the first layer of REO to the second layer of REO, and a single crystal layer of the selected III-N material deposited on the second layer of REO.

Claims

1. A method of forming REO dielectric layers and a layer of amorphous silicon oxide between a layer of semiconductor material and a silicon substrate, the method comprising the steps of: providing a crystalline silicon substrate; depositing a first layer of single crystal rare earth oxide on the silicon substrate; depositing a uniform layer of amorphous silicon on the first layer of rare earth oxide; depositing a second layer of rare earth oxide on the layer of amorphous silicon, the step of depositing the second layer of rare earth oxide including ramping the temperature of the substrate to a temperature required for epitaxial growth and epitaxially growing the second layer of rare earth oxide, the temperature required for epitaxial growth crystallizing the layer of amorphous silicon to form a layer of crystallized silicon; and oxidizing the crystalline silicon to transform the crystalline silicon to amorphous silicon oxide.

2. A method as claimed in claim 1 further including a step of epitaxially growing a single crystal layer of the semiconductor material on the second layer of rare earth oxide.

3. A method as claimed in claim 1 wherein the step of oxidizing the crystalline silicon includes epitaxially growing a single crystal layer of the semiconductor material on the second layer of rare earth oxide.

4. A method as claimed in claim 1 wherein the step of oxidizing the crystalline silicon includes raising the temperature of the substrate to a temperature above the temperature required for epitaxial growth and performing the raising in an oxygen atmosphere.

5. A method as claimed in claim 1 wherein the step of depositing the uniform layer of amorphous silicon includes depositing the uniform layer at a temperature in the range of 20° C. to 100° C.

6. A method as claimed in claim 1 wherein the step of depositing the uniform layer of amorphous silicon includes depositing the uniform layer with a thickness in a range of 1 nm to 10 nm.

7. A method as claimed in claim 1 wherein the step of depositing the first layer of single crystal rare earth oxide includes depositing a layer of single crystal rare-earth oxide having a first lattice constant adjacent the silicon substrate approximately matching the lattice constant of the silicon substrate.

8. A method as claimed in claim 1 wherein the step of depositing the second layer of single crystal rare earth oxide includes depositing a layer of single crystal rare-earth oxide having a second lattice constant at an upper surface approximately matching a lattice constant of the semiconductor material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The foregoing and further and more specific objects and advantages of the instant invention will become readily apparent to those skilled in the art from the following detailed description of a preferred embodiment thereof taken in conjunction with the drawings, in which:

(2) FIGS. 1-6 are simplified layer diagrams illustrating several sequential steps in a process of the formation of amorphous silicon oxide between layers of single-crystal rare earth oxide for the growth of III-N semiconductor material in accordance with the present invention;

(3) FIGS. 7 and 8 illustrate steps in another method of the formation of amorphous silicon oxide between layers of single-crystal rare earth oxide, in accordance with the present invention; and

(4) FIGS. 9 and 10 illustrate steps in another method of the formation of amorphous silicon oxide between layers of single-crystal rare earth oxide, in accordance with the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

(5) In view of the need for stress mitigation in a process of forming III-N semiconductor layers on silicon substrates some effort and study has gone into the formation of an amorphous layer of silicon oxide (SiO.sub.2) between the silicon substrate and the III-N layer or layers. However, to date various proposed methods for the formation of the amorphous layer all have several drawbacks or problems that substantially reduce the efficiency or effectiveness of the process and results. Also, a rare earth dielectric layer between the III-N layer and the silicon substrate improves electric break-down characteristics of electronic devices formed in the III-N layer. Accordingly, a new method for the formation of an amorphous layer of silicon oxide (SiO.sub.2) between layers of single crystal rare earth oxide is herein disclosed. The new method is greatly improved and results in the formation of a structure including an amorphous silicon oxide layer between layers of single crystal rare earth oxide that can be accurately controlled and which substantially absorbs or reduces stress between the silicon substrate and the III-N semiconductor layer.

(6) Turning now to FIG. 1, a silicon substrate 10 is illustrated which is, as understood in the art, a single-crystal material including silicon and may in some applications include other materials all of which are included in the general term “silicon” substrate. Also, the substrate may be for example a silicon wafer or some part thereof and is referred to herein by the general term “substrate”. While silicon substrate 10 is illustrated as having a (111) crystal orientation, it will be understood, is not limited to any specific crystal orientation but could include (111) silicon, (110) silicon, (100) silicon, various off cuts or offsets of these, or any other orientation or variation known and used in the art.

(7) An insulator layer 12 of single crystal rare earth oxide (REO) is epitaxially deposited on the surface of silicon substrate 10. Rare earth oxide layer 12 is grown directly on the surface of substrate 10 using any of the well-known growth methods, such as MBE, MOCVD, PLD (pulsed laser deposition), sputtering, ALD (atomic layer deposition), or any other known growth method for thin films. Throughout this disclosure whenever rare earth materials are mentioned it will be understood that “rare earth” materials are generally defined as any of the lanthanides as well as scandium and yttrium. While layer 12 is referred to herein as a “layer” for convenience of understanding, it should be understood that it can be a single layer with crystal lattice constant grading from the lower interface with substrate 10, designated a.sub.i1, to the upper surface or interface, designated a.sub.i2, as illustrated in FIG. 1. Layer 12 could alternatively include multiple REO layers with gradually changing crystal lattice constant a.sub.1>a.sub.2> . . . >a.sub.n, as illustrated in FIG. 2. For purposes of this disclosure the term “layer” is defined to include either single or multiple layers or sub-layers.

(8) In this example, layer 12 not only serves as a rare earth dielectric layer between the III-N layer and silicon substrate 10, to improve electric break-down characteristics of electronic devices formed in the III-N layer, but also acts as a buffer to adjust the lattice constant between silicon substrate 10 and the III-N layer. Thus, in this example, the lattice constant a.sub.i1 at the substrate interface is selected to be approximately the lattice constant of single crystal silicon while the lattice constant a.sub.i2 or a.sub.n is adjusted to be approximately the lattice constant of III-V semiconductor material which will be grown on top of the structure.

(9) Turning to FIG. 3, a smooth layer 14 of amorphous silicon is deposited on the surface of REO layer 12 at a temperature close to room temperature, or approximately 20° C. to approximately 100° C. In this specific embodiment, the term “smooth” is defined to mean that the layer has a substantially uniform thickness throughout. The thickness of layer 14 is preferably between 1 nm and 10 nm. In this example low temperature deposition of amorphous silicon is used in order to keep amorphous Si layer 14 smooth because Si surface energy is higher than that of REO and therefore the Si forms islands at temperatures typical for epitaxial growth.

(10) Referring to FIG. 4, a second rare earth oxide layer 16 is formed on the surface of amorphous Si layer 14. Growth of second REO layer 16 is started during substrate temperature ramp (i.e. ramping the temperature of the substrate to a temperature required for epitaxial growth) before full crystallization of amorphous Si layer 14 occurs. Second REO layer 16 also serves as a surfactant to suppress mobility of Si atoms and prevent formation of Si islands. Thus, second REO layer 16 aids in retaining Si layer 14 smooth. During the REO deposition forming REO layer 16, Si layer 14 fully crystallizes and transfers crystal structure register of REO layer 12 to REO layer 16, which grows epitaxially thereafter. In the preferred embodiment, REO layer 16 is approximately 10 nm or less.

(11) Once REO layer 16 is completed the crystal structure is fixed and the lattice constant a.sub.i2 or a.sub.n is approximately the lattice constant of III-V semiconductor material which will be grown on top of the structure. Referring now to FIG. 5, the next step in this process is to perform oxidation of the structure, designated 17. Oxidation is performed in this process in an oxygen atmosphere at a temperature above the epitaxial growth temperature of REO layer 16 in order to oxidize crystalline Si layer 14. The oxidation transforms crystalline Si interlayer 14 to an amorphous SiO.sub.2 layer. Because crystalline Si layer 14 has a definite thickness (i.e. is not simply an interface) and is positioned between and restricted by REO layers 12 and 16 oxidation can occur rapidly through the entire layer. Further, since crystalline Si layer 14 is a smooth layer with a substantially uniform thickness the final layer of amorphous silicon is completely controlled and remains uniform.

(12) Amorphous SiO.sub.2 layer 14 serves as a stress mitigation layer so that REO layer 16 can be increased in thickness if desired. Also, as illustrated in FIG. 6, a layer 18 of III-N material is grown on REO layer 16. Electronic or photonic devices can be formed directly in/on III-N layer 18 or additional layers of III-V semiconductor material can be epitaxially grown on layer 18. It should be understood that because of the crystal constant matching of layer 12, and the stress mitigating of amorphous SiO.sub.2 layer 14 all of the layers 12, 16 and 18 are single crystal material and REO layer 12 forms a rare earth dielectric layer between the III-N layer and the silicon substrate to improve electric break-down characteristics of electronic devices formed in/on III-N layer 18.

(13) Referring specifically to FIGS. 7 and 8, another method of the formation of amorphous silicon oxide between layers of single-crystal rare earth oxide, in accordance with the present invention, is illustrated. In this process the silicon in layer 14 is crystalline as explained in conjunction with FIG. 4 above. Oxidation of crystalline silicon layer 14 is possible in accordance with this method during growth of III-N semiconductor layer 18 on REO layer 16 because of high substrate temperature (up to 1100° C.) during the III-N growth process (e.g. MOCVD). During growth of III-N semiconductor layer 18 on REO layer 16, because of the high temperatures used in the process, diffusion of oxygen into Si layer 14 (from REO material above and below Si Layer 14) takes place. As a result of this oxygen diffusion the crystalline Si interlayer transforms into amorphous silicon dioxide. One advantage of this process is that it allows uninterrupted growth of REO layer 16 until the desired thickness is reached.

(14) Referring additionally to FIGS. 9 and 10, one additional feature should be understood. During growth of III-N semiconductor layer 18 on REO layer 16, because of the high processing temperatures, it is possible that part of the amorphous SiO.sub.2 layer 14 of the first method or part of the crystalline Si of the second method will transform to a silicate (RESiO.sub.x). This is illustrated in FIG. 9 where some of the Si of layer 14 combines with some of the rare earth in layer 12 to form a thin layer 20 of silicate (RESiO.sub.x) and some of the Si of layer 14 combines with some of the rare earth in layer 16 to form a thin layer 22 of silicate (RESiO.sub.x).

(15) Thus, a first layer of single crystal rare earth oxide is grown on a crystalline silicon substrate to serve as a REO dielectric layer to improve electric break-down characteristics of electronic or photonic device formed in/on a final III-N layer of the structure. The first layer of single crystal rare earth oxide also serves stress management purposes between the silicon substrate and the final III-N layer. A smooth layer of silicon is deposited at low temperature and converted to crystalline silicon during the deposition of a second layer of rare earth material so that the second REO layer is epitaxially deposited and the crystalline structure of the first REO layer, is transferred to the second REO layer. The crystalline silicon is then converted to a uniform layer of amorphous silicon through either an oxidation process or the high temperature deposition of a layer of single crystal III-N semiconductor material. The amorphous silicon layer helps to relieve stress between the III-N semiconductor layer and the silicon substrate.

(16) Various changes and modifications to the embodiments herein chosen for purposes of illustration will readily occur to those skilled in the art. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof which is assessed only by a fair interpretation of the following claims.