A PROCESS FOR PREPARING PASSIVATED EMITTER REAR CONTACT (PERC) SOLAR CELLS

Abstract

A process for preparing a passivated emitter rear contact solar cell, which includes the steps as follows: removing the damaged layer on the surface of the silicon wafer and at the same time polishing both surfaces, texturing, forming PN junction, etching, removing the glass impurity, depositing a passivation film on the back surface, depositing a passivating antireflective layer on the front surface, making local openings on the back surface, screen printing of metal paste on both the front surface and the back surface and sintering, in which the texturing step employs a catalytic metal etching approach, and the textured structure is a nanometer-level textured structure. The present invention has combined removing the damaged layer on the surface of the silicon wafer and polishing both the front and back surfaces into one single step, and thus has simplified the production process and reduced the production cost.

Claims

1. A process for preparing a passivated emitter rear contact, wherein the following steps: removing a damaged layer on the surface of a silicon wafer and at the same time polishing both surfaces thereof, texturing, forming PN junction, etching, removing the glass impurity, depositing a passivation film on a back surface thereof, depositing a passivating antireflective layer on a front surface thereof, making local openings on the back surface, screen printing of metal paste on both the front surface and the back surface and firing; wherein the step of texturing employs a catalytic metal etching approach, and the textured surface structure is a nanometer-level structure with textured surface.

2. The preparation process as set forth in claim 1, wherein the step of removing a damaged layer on the surface of a silicon wafer and at the same time polishing both surfaces thereof is carried out in an acidic liquid or in an alkali liquid, and the operating time thereof is from 2 to 20 minutes, the acidic liquid is a mixture of HNO3 and HF, or a mixture of H2CrO4 and HF; the temperature is from 5 to 45° C.; in a mixture of HNO3 and HF, the ratio by volume of HNO3 (69%)/HF (49%) or of H2CrO4 (60%)/HF (49%) is greater than 4:1; and the alkali liquid is selected from a NaOH solution, a KOH solution or a tetramethylammonium hydroxide (TMAH) solution, an operating temperature is within a range of from 5 to 95° C., and a volumetric concentration of the alkali liquid is higher than 1%.

3. The preparation process as set forth in claim 2, wherein an operating time of the step of removing a damaged layer on the surface of a silicon wafer and at the same time polishing both surfaces thereof is from 2 to 10 minutes.

4. The preparation process as set forth in claim 1, wherein the step of texturing is carried out as follows: first placing the silicon wafer into a solution containing metal ions for soaking, so as to allow surfaces of the silicon wafer to be covered with a layer of nanometer metal particles; and then using a chemical etching liquid to treat each of the surfaces of the silicon wafer, so as to form the nanometer-level textured structure, wherein the chemical etching liquid is a solution of hydrofluoric acid that contains an oxidant.

5. The preparation process as set forth in claim 4, wherein the solution containing metal ions is a metal salt solution that contains hydrofluoric acid.

6. The preparation process as set forth in claim 1, wherein the texturing step is carried out as follows: placing the silicon wafer into a solution of hydrofluoric acid that contains both an oxidant and a metal salt, so as to form the nanometer-level textured structure on surfaces of the silicon wafer.

7. The preparation process as set forth in claim 4, wherein the metal ion concentration in the solution is higher than 6E-5 mol/L.

8. The preparation process as set forth in claim 1, wherein between the texturing step and the PN junction forming step, there is a step of modification etching of the textured surface microstructure, and the specific procedure thereof is as follows: placing the silicon wafer with the textured surface into a chemical etching liquid for modification etching of the microstructure; the chemical etching liquid is selected from the group consisting of NaOH solution, KOH solution, tetramethylammonium hydroxide (TMAH) solution or a mixed solution of an acidic oxidant and HF acid.

9. The preparation process as set forth in claim 8, wherein either prior to or following the foregoing modification etching on the textured surface microstructure, a metal particle removing step needs to take place, and the specific procedure thereof is as follows: using an acidic liquid and then deionized water to wash the obtained silicon wafer, so as to remove the metal particles.

10. The preparation process as set forth in claim 6, wherein the metal ion concentration in the solution is higher than 6E-5 mol/L.

Description

DESCRIPTION OF THE EMBODIMENTS

[0036] The present invention will be further described in detail in reference to certain exemplary embodiments,

EXEMPLARY EMBODIMENT 1

[0037] A process for preparing polycrystalline silicon PERC solar cells, comprising t following steps:

[0038] First, using a KOH solution of 2% mass concentration to remove a damaged layer on the surface of a polycrystalline silicon wafer and at the same time polishing both surfaces at a temperature of 70° C. for a time period of 6 minutes;

[0039] then carrying out a catalytic metal etching treatment on the polished silicon wafer to form a nanometer-level textured surface, wherein the size of the nanometer-level textured surface is within a range of from 300 to 500 nm, and the reflectivity thereof is 17%; the specific procedure of preparing the textured surface is as follows: placing the silicon wafer in a chemical etching liquid that contains metal ions, so as to form the nanometer-level textured surface on a surface of the silicon wafer, wherein the chemical etching liquid is a mixed solution of H.sub.2O.sub.2 containing silver ions and hydrofluoric acid, in which the metal ion concentration is higher than 6E.sup.5 mol/L; the concertation of 11.sub.20.sub.2 is 0.5 mol/L and the concentration of HF is 10 mol/I.;

[0040] next, the silicon wafer with textured surface is placed in a diffusion oven for diffusion, wherein the diffusion temperature is from 800° C. to 810° C., the operating time period is from 60 to 90 minutes, and the block resistance is from 60 to 120 Ω/sq.;

[0041] next, carrying out back surface and edge etching on the diffused silicon wafer and removing a surface PSG layer;

[0042] next, carrying out an ALD deposition of Al.sub.2O.sub.3 passivation layer on the back surface of the etched silicon wafer, as well as an annealing treatment,

[0043] next, carrying out a PECVD deposition of a SiNx film on top of the Al.sub.2O.sub.3 passivation layer;

[0044] next, carrying out a PECVD deposition of a silicon nitride antireflective layer on the front surface of the silicon wafer;

[0045] next, cutting local openings on the back surface using a laser;

[0046] finally, forming electrodes by way of screen printing and forming an Ohmic contact.

COMPARATIVE EXAMPLE 1

[0047] In the comparative example, the same starting materials have been used to make the passivated emitter rear contact solar cells, and the preparation method mainly comprises the following steps: removing the damaged layer on the surface of the silicon wafer, texturing, diffusion, back polishing, etching, removing the glass impurity, back surface depositing of alumina or silica film, depositing of silicon nitride protection film, front surface depositing of silicon nitride antireflective layer, making local openings on the back surface, screen printing of metal paste on both the front surface and the back surface and sintering, so as to prepare the solar cell.

[0048] The solar cell made in the foregoing exemplary embodiment and the solar cell made in the comparative example have been further tested and the test results are as follows:

TABLE-US-00001 Uoc Jsc FF (mV) (mA/cm.sup.2) (%) EFF Conventional polycrystalline 633.3 36.02 78.46 17.90% silicon solar cell Exemplary embodiment 1 641.4 36.80 77.82 18.37% Comparative example 1 644.2 37.22 78.58 18.84%

[0049] As shown in the table above, in comparison to comparative example 1, the efficiency of the polycrystalline silicon PER.0 solar cell prepared according to the present invention has been increased by about 0.47%, and thus an unexpected result has been achieved. In addition, it not only increases open circuit voltage, but also improves the fill factor (FP). It has indicated that the PN junction formed following diffusion is smoother, which can allow better metal contact.