ELECTRICAL CONDUCTIVE VIAS IN A SEMICONDUCTOR SUBSTRATE AND A CORRESPONDING MANUFACTURING METHOD

Abstract

A method is provided for producing at least one electrical via in a substrate, the method comprising: producing a protective layer over a component structure which has been produced or is present on a front side of the substrate; forming at least one contact hole which extends from a surface of a backside of the substrate to a contact surface of the component structure; forming a metal-containing and thus conductive lining in the at least one contact hole creating a hollow electrically conductive structure in the at least one contact hole; and applying a passivation layer over the backside of the substrate, the passivation layer spanning over the hollow electrically conductive structure for forming the at least one electrical via. Also provided is a micro-technical component comprising at least one electrical via.

Claims

1. A method of or for producing at least one electrical via (150, 150′) in a substrate (3), the method comprising the following steps: producing a protective layer (4) over a component structure (5) which has been produced or is present on a front side (2) of the substrate (3); forming at least one contact hole (14, 14′) which extends from a surface of a backside (1) of the substrate (3) to a contact surface (5a) of the component structure (5); forming a metal-containing and thus conductive lining (8, 9, 10) in the at least one contact hole (14, 14′) creating a hollow electrically conductive structure (110) in the at least one contact hole (14, 14′); and applying a passivation layer (11) over the backside (1) of the substrate (3), the passivation layer (11) spanning over the hollow electrically conductive structure (110) for forming the at least one electrical via (150, 150′).

2. The method according to claim 1, wherein forming a metal-containing lining in the at least one contact hole comprises: applying a first metal-containing layer (8) as one of a barrier layer or an adhesive layer; and applying a second metal-containing layer (9) differing from the first metal-containing layer (8) as a seed layer for a third metal-containing layer (10), which is electro-deposited on the second metal-containing layer (9), wherein the first and the second metal-containing layers (8, 9) are applied under vacuum, and maintaining the vacuum without interruption at least during application.

3. The method according to claim 2, wherein at least the second metal-containing layer (9) is applied by a metal-organic chemical vapor atmosphere.

4. The method according to claim 3, wherein the first metal-containing layer (8) is applied by a metal-organic chemical vapor phase.

5. The method according to claim 1, wherein a backside wiring level is produced on the backside (1) of the substrate (3) when forming the metal-containing lining (8, 9, 10), said metal-containing lining (8, 9, 10) forming the electrically conductive structure (110).

6. The method according to claim 2, wherein a surface wetting with a fluid is carried out under vacuum conditions prior to the electro-deposition of the third metal-containing layer (10).

7. The method according to claim 2, wherein a resist mask including negative resist for defining positions for metal deposition is produced prior to the deposition of the third metal-containing layer (10).

8. The method according to claim 1, wherein a maximum process temperature occurring in the production of the at least one electrical via (150) is less than 501° C.

9. The method according to claim 1, wherein the metal-containing lining (8, 9, 10) is baked out in a non-corrosive atmosphere prior to applying the passivation layer (11).

10. The method according to claim 1, wherein the component structure (5) is produced as an integral part of a specific structure prior to the production of the respective associated at least one contact hole (14, 14′).

11. The method according to claim 1, wherein the substrate (3) is provided as a stack of a plurality of carrier materials connected to each other.

12. The method according to claim 1, wherein the component structure (5) is one of shielded, mechanically decoupled, or electrically decoupled from a further component structure by producing at least one further hollow conductive structure (110) as a via (150) including a conductively lined contact hole (14, 14′) laterally between the component structure (5) and the further component structure.

13. The method according to claim 10, wherein the specific structure is one of a microelectronic structure, a micromechanical structure, an optical structure, an electrical structure, or a microfluidic structure.

14. The method according to claim 1, wherein the passivation layer (11) is applied which includes apertures or a local structuring adapted for a later coating with further metal layers (12) or suitable for placing solder bumps (13, 13′) over the backside (1) of the substrate (3), which passivation layer (11) spans the hollow electrically conductive structure (110).

15. The method according to claim 14, wherein placing solder bumps comprises fusing the solder bumps (13, 13′) and wherein fusing the solder bumps (13, 13′) is performed and configured for a later mechanical and electrical connection of the substrate (3) or a finished chip (100) to a printed circuit board (17).

16. The method according to claim 1, wherein forming the at least one contact hole (14, 14′) is followed by forming an insulation layer on the backside (1) of the substrate (3), which insulation layer completely lines the at least one contact hole (14, 14′) and is locally remote from the contact surface (5a).

17. The method according to claim 1, wherein the at least one contact hole (14, 14′) is a deep or elongate contact hole.

18. The method according to claim 17, wherein an aspect ratio of the at least one electrical via (150, 150′) is greater than or equal to eight, or is 8 to 1.

19. The method according to claim 1, wherein a plurality of contact holes (14, 14′) or vias (150, 150′) are formed in the substrate (3) spaced from each other.

20. A micro-technical component comprising a substrate (3) and having a front side (2) and a backside (1), wherein a component structure (5) including at least some structural elements with lateral dimensions of less than 10 μm is formed on the front side (2); at least one electrically conductive via (150, 150′) extending from a surface of the backside (1) to a connection surface (5a) of the component structure (5) is provided; and the at least one electrically conductive via (150, 150′) comprises a metal-containing lining (110), thereby forming a hollow conductive structure.

21. The micro-technical component according to claim 20, comprising an insulating cover (11) over the at least one electrically conductive via (150, 150′) on the backside (1) so that the hollow conductive structure is covered.

22. The micro-technical component according to claim 20, wherein a diameter of a non-filled area of the at least one hollow conductive structure as the at least one electrically conductive via (150, 150′) is greater than one layer thickness of the metal-containing lining (110) of the at least one electrically conductive via (150, 150′).

23. The micro-technical component according to claim 20, wherein an aspect ratio of the at least one electrically conductive via (150, 150′) is greater than or equal to eight (or 8 to 1).

24. The micro-technical component according to claim 20, wherein an aspect ratio of the at least one electrically conductive via (150, 150′) is less than eight.

25. The micro-technical component according to claim 20, comprising two or more electrically conductive vias (150, 150′) provided laterally adjacent to the component structure (5) as one of shielding elements, elements for electrically decoupling, or elements for mechanically decoupling the component structure (5) from a further component structure.

26. The micro-technical component according to claim 20, wherein a plurality of electrically conducting or conductive vias (150, 150′) are provided, each of which comprises a respective metal-containing lining (110), thereby forming a plurality of hollow conductive structures.

27. The method according to claim 15, wherein the solder bumps (13, 13′) dock to contact points (16, 16′) of the printed circuit point (17) in a spatial-geometrically fitting manner in order to produce conductive contacts to the printed circuit board (17).

28. The micro-technical component according to claim 22, wherein the diameter is greater than two layer thicknesses of the metal-containing lining (110).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Embodiments will now be described in greater detail with reference to the accompanying drawings. Embodiments of the invention are illustrated by one or more examples and not in a way that transfers or incorporates limitations from the Figures into the patent claims, even if “especially”, “for example”, or “e.g.” is not mentioned in all places. Same reference numerals in the Figures indicate similar elements.

[0059] FIG. 1 is a functional flow diagram of an example of a method according to the invention for producing an electrical via, in which some optional steps are also shown.

[0060] FIG. 2 is a cross-sectional view of a substrate 3 including an electrical via 150 according to an example of the invention.

[0061] FIG. 3 is a top view of the surface of the backside 1 of the substrate 3 including an electrical via 150 and a wiring structure for interconnecting the via to a solder bump structure 13.

[0062] FIG. 4 is a cross-sectional view of a substrate 100 including a plurality of electrical vias (contact holes 14, 14′), a backside wiring layer and a printed circuit board 17 connected to the backside wiring layer via solder bumps 13, 13′ in electrically conductive manner.

DETAILED DESCRIPTION OF THE INVENTION

[0063] These—and further—embodiments will be described in detail. Initially we alternately refer to FIG. 1 and FIG. 2.

[0064] FIG. 1 schematically shows an exemplary process flow for producing a component structure including a subsequent production of an electrical via. As shown, a complete front-side process cycle 200 is initially performed, in which the desired component structure, for example, a CMOS structure, a MEMS structure is produced in combination with electronic components, etc. For this purpose, the process technologies required for this are employed, as described above, without having to consider the subsequent production of the via(s).

[0065] FIG. 2 shows a cross-sectional view of a component 100 in this regard, which component is referred to as a micro-technical component in order to thus describe that at least some sizes of structural elements, e.g. semiconductor devices or the like, include dimensions of 10 μm or less. The term “micro-technical” component thus includes any component carrying component structures which have a micromechanical, microelectronic, optoelectronic, optical, and/or electrical function, or microfluidic function, and dimensions within the range specified above. The micro-technical component 100 comprises a substrate 3, e.g. a semiconductor substrate, or any other substrate having a front side 2 and a backside 1.

[0066] The substrate 3 has a suitable thickness, such as in the range of several 100 μm, as is typical for the production of, for example, microelectronic component structures.

[0067] As explained above with reference to FIG. 1, the production of a component structure 5 or 5′ has already been completed, which component structure is represented merely as a contact surface 5a in the drawing of FIG. 2, wherein it is to be noted that, in addition to the contact or connection surface 5a, further structural elements may typically form even a highly complex component structure. The process technologies employed for this purpose are dependent on the component structure to be produced which is also supposed to be indicated by reference numeral 5 or 5′ in FIG. 4.

[0068] In the shown embodiment, for example, an insulation layer 6 is provided in connection with the contact surface 5a which is thus supposed to be representative for other component structures.

[0069] Again referring to FIG. 1, the second step describes the production 202 of a protective layer 4 on the front side, wherein this procedure may still be considered as a part of the process flow 200 for the production if required. For example, a corresponding protective layer is produced as an integral part of a CMOS process flow. The protective layer 4 is thus deposited over the entire front side of the substrate 3 and prevents that the already produced component structure 5 is damaged by the further production processes 300 to 400 for the electrical via.

[0070] In other embodiments, the deposition of the protective layer 4 can also be performed at any other time prior to the further processes for the production of the via(s).

[0071] Regardless of whether the deposition of the protective layer 4 is considered an integral part of the production process 202 or as an integral part of the method for the production of the via, the flow continues by processing the backside 1 of the substrate 3 according to one embodiment. For this purpose, the backside 1 is ground to the desired thickness, step 302, and smoothed, step 303, which can be achieved by a spin-etching method.

[0072] Then, a mask layer is produced on the backside 1 (on the surface of the backside) which is composed of a suitable material in order to withstand the subsequent procedure for forming a contact hole 14. Usually, materials, such as silicon dioxide, silicon nitride, a mixture thereof, or the like, are used for this purpose, wherein these materials are typically referred to as hard mask. Then, a contact hole 14 is formed from the (top side of the) backside 1 of the substrate 3 by deep reactive ion etching (DRIE), step 314, wherein the etching can typically be performed in a plurality of stages and results in flank angles of 90°±5° in some embodiments. This anisotropic etching is selectively performed such that it stops, for example, at and in the insulation layer 6 below the contact surface 5a of the component structure 5 produced on the front side 2.

[0073] In a further reactive ion etching process, the residual portion of the insulation layer 6 exposed in the contact hole 14 is removed from the bottom of the contact hole so that the contact surface 5a is exposed there or becomes electrically accessible from the contact hole.

[0074] FIG. 2 schematically shows a contact hole 14 which extends through the backside 1 of the substrate 3 to the front side 2 and is formed through the insulation layer 6 and is thus in contact with the contact surface 5a of the component structure 5.

[0075] Furthermore, the side wall of the contact hole 14 and the top side of the backside 1 are covered by an insulation layer 7, step 316, which is made of an oxide based on an ethyl ester, called tetraethyl orthosilicate or tetraethoxysilane (TEOS).

[0076] The production can be carried out on the basis of common deposition processes, wherein—as explained above—especially process temperatures are selected such that they are compatible with the already produced component structures 5 or 5′ on the front side 2. In advantageous embodiments, a maximum process temperature is kept at less than approx. 500° C. (i.e. less than 501° C. in order to avoid the term “substantially”) during the entire process flow for producing the via 150 including the contact hole 14.

[0077] The (inner) insulation layer 7 is then removed from the bottom of the contact hole 14, e.g. by an reactive ion etching so that preferably material is removed from the bottom of the contact hole 14 without needlessly removing material from the side walls of the contact holes. Thus, the contact surface 5a of each component structure is re-exposed so that a conductive connection to the respective contact surface 5a is enabled while ensuring a reliable insulation of the side walls (the surfaces thereof) from the substrate 3 and also from other structures which may be present on the backside 1. Due to the insulation layer 7, certain properties of the via can be set, e.g. the breakover voltage or the leakage current.

[0078] FIG. 2 further shows a first metal-containing layer 8 which, when applied in step 318, lines the contact hole 14 and which is also present on the surface of the backside 1. In one embodiment, the first metal-containing layer 8 is composed of titanium nitride having a thickness of several nm to several 10 nm depending on the desired layer structure for the via 150.

[0079] In the illustrative embodiment, the first layer 8 serves as a barrier and adhesive layer which, on the one hand, prevents undesired diffusion of metal ions of a subsequently applied metal layer into adjacent areas and, on the other hand, ensures excellent adhesion of the subsequently applied metallic material.

[0080] A second metal-containing layer 9 is shown in the example, which is applied on top of the metal-containing layer 8 and has a suitable thickness which, as a “seed layer”, enables a reliable subsequent electrodeposition process. In one embodiment, the second layer 9 includes copper in case a layer to be deposited subsequently also contains copper. Depending on the desired material structure, other metal-containing materials can also be used as the seed layer 9.

[0081] In an advantageous embodiment, the two layers 8 and 9 are produced in an in-situ process flow, wherein the process flow is executed without interruption of the vacuum conditions in a process plant so that the efforts for handling the substrate and for cleaning the process plant between the individual deposition processes are minimized.

[0082] In an illustrative embodiment, the first layer 8 is deposited by means of a metal-organic chemical vapor phase (MOCVD 1) so that a conformal thin material layer is formed which forms a reliable barrier against migration of metal to adjacent areas. Furthermore, due to the application of metal-organic chemical vapor deposition, excellent adhesion of layer 8 to metal can be achieved, for example, for enabling sufficient stability and adhesion of the second layer 9 which serves as a seed layer for the subsequent electrodeposition.

[0083] In an advantageous embodiment, a metal-organic chemical vapor phase (MOCVD 2) is used also for the deposition of the second layer 9 which, when applied in step 320, lines the contact hole 14 so that also in this case a conformal thin layer is achieved even for great aspect ratios of the contact hole 14. This seed layer 9 is useful for the growth and epitaxial growth of the metal layer 10 to be electro-deposited subsequently. In alternative embodiments, physical vapor deposition (PVD) can be used instead of MOCVD.

[0084] Especially when applying MOCVD, the process parameters for the deposition of layer 8 and/or layer 9 can be selected such that the desired surface properties are maintained and a reliable covering even of irregularities of the side walls is achieved, wherein typically a layer thickness of less than 100 nm is sufficient for each layer.

[0085] FIG. 2 further shows a third metal-containing layer 10 which is formed on the side walls and the bottom of the contact hole 14 as well as in defined areas on the surface of the backside 1. The third metal-containing layer 10 is composed of a well-conducting material so that the substantial conductivity of the lining 110 of the contact hole 14, which is formed of layers 8, 9 and 10, is determined thereby. The via 150 thus has a hollow conductive structure 110, i.e. formed in the contact hole 14 by layers 8, 9 and 10, which structure has an electrical connection to the contact surface 5a and thus to the corresponding component structure 5.

[0086] As further shown in FIG. 2, layers 8, 9 and 10 are also formed in other areas of the top side of the backside 1 so that this layer system concurrently also forms the basis for a wiring layer on the (top side of the) backside 1 of the substrate 3.

[0087] As also illustrated by FIG. 1, the third metal-containing layer 10 is produced by initially applying a mask layer (not shown) to the structure, wherein those positions are exposed in which the material layer 10 is to be deposited. A corresponding mask layer can be produced, for example, as a resist mask.

[0088] In an advantageous embodiment, the resist mask is made of negative resist in order to define the corresponding positions for the deposition of the well-conducting metal-containing material. The resist mask is produced such that the contact hole 14 is not filled but spanned. Thus, only very little residual resist has to be removed from the contact hole 14 after exposure of the resist, thereby reducing the respective efforts in removing the resist mask and the subsequent cleaning.

[0089] In a further illustrative embodiment, the backside 1 of the substrate 3 and thus also the side walls and the bottom of the contact hole 14 are subjected to a vacuum treatment and a wetting with a fluid, e.g. water, so that a homogeneous wetting by the electrolyte is achieved for a subsequent electrodeposition.

[0090] The electrodeposition can be performed, for example, as a current-guided plating in step 330, wherein the previously deposited layer 9 serves as a current distribution layer. In this way, the material of layer 10 is reliably deposited within the contact hole 14 and on horizontal areas in the desired positions, thereby creating a hollow conductive structure in depth which is represented by the contact hole 14, the conductivity of which is substantially determined by the material of layer 10.

[0091] When the contact hole 14 has a substantially round cross-sectional shape, i.e. when sectioned in the plane perpendicular to the plane of the drawing of FIG. 2, substantially a hollow cylinder is thus created. However, it is to be noted that, depending on criteria to be met, the contact hole 14 may have corresponding flank angles, especially during anisotropic etching through the substrate 3, or corresponding cross-sectional shapes of the contact hole 14 can be set. For example, bulged cross-sections or the like can be realized when this is considered advantageous for the general function of the via 150. Especially the conformal deposition methods based on the afore described metal-organic chemical vapor deposition of layers 8 and 9 achieve a reliable covering of the side wall of each contact hole 14 (two of which in the example).

[0092] In advantageous embodiments, the material of layer 10 galvanically deposited in a current-guided manner forms the structure for the entire backside wiring levels 10a and 10b of the component 100 so that no additional deposition steps are required for providing a suitable contact structure on the surface of the backside.

[0093] As described by FIG. 1 and shown in FIG. 2 and FIG. 3, corresponding wiring levels 10a and 10b are represented on the surface of the backside 1 in the illustrated embodiment.

[0094] These wiring levels are supplemented with a permanent passivation layer 11 which, on the one hand, covers the via 150, i.e. contact hole 14 and the hollow conductive structure 110, respectively, without completely filling the same and, on the other hand, passivates the other areas especially those of the wiring levels 10a and, in part, 10b produced concurrently with the via 150.

[0095] In the further steps for producing the structure illustrated in FIG. 2, as also shown by FIG. 1, the resist mask used for electrodeposition of the material of layer 10 is removed, wherein resist removal processes known (common) per se can be applied, thereby re-exposing layers 8 and 9 on the backside 1. This procedure for removing material of layers 8 and 9 can be performed without a mask, where appropriate, since the layer thickness of layers 8, 9 is very low as compared to the thickness of layer 10 which serves as a mask in the illustrated embodiment. In other embodiments, a further resist mask can be produced prior to the etching of layers 8 and 9, if required.

[0096] After a corresponding structuring or insulation of the metal structures on the backside by etching the barrier and adhesive layer 8 and the seed layer 9 in step 340 in combination with optional cleaning steps, a baking-out process for stabilizing the metal layer 10 is performed in a non-corrosive vapor atmosphere in illustrative embodiments, wherein the process temperature is less than 501° C., as already explained above.

[0097] In a further embodiment, the passivation layer 11 is applied in step 350, wherein one or more suitable materials are deposited by processes known per se. The process parameters are defined such that merely a covering of the via 150 without or without substantial introduction of material into the contact hole 14 is carried out so that the contact hole 14 and the hollow conductive structure 110 of the via 150, respectively, are spanned.

[0098] Apertures are produced by masking steps at the corresponding positions, for example, at the position of the solder bump 13 in the passivation layer 11, whereupon an “under metallization” 12 is deposited in step 355. For example, a nickel/gold material can be applied in a desired thickness by using an electroless electrodeposition in order to produce the under metallization 12 of the solder bump 13.

[0099] The selection of materials for the under metallization 12 and the number of partial layers for the under metallization 12 may vary depending on design criteria or the like. Then, the material for the solder bump 13 is applied in step 360, which is performed on the basis of a mask or even without a mask, followed by fusing in order to obtain the desired shape of the solder bump(s) 13.

[0100] Thus, the procedure of producing the wiring levels and the via 150 is completed in step 400.

[0101] As explained with reference to FIG. 1, further processes 500 for processing the component 100 will now follow, if required.

[0102] FIG. 3 schematically shows a top view of the backside 1, wherein the via 150 including the hollow conductive structure 110 in the contact hole 14 is electrically connected to the solder bump 13 by means of the third metal-containing layer 10 and the non-visible layers 8, 9. In the Figure, this connection is illustrated as a conductive path 10a. As explained above, the corresponding conductive paths 10a can desirably be produced as a part of the electrodeposition for the lining of the contact hole 14 for the via 150 in order to thus form the wiring level(s) on the backside.

[0103] It should be noted that not each via 150 is necessarily connected to a corresponding solder bump.

[0104] For example, a plurality of vias 150 can be provided in suitable positions so that, for example, a shielding of sensitive areas in and on the substrate 3, a mechanical decoupling of certain substrate areas, and/or a thermal coupling to possible heat sinks, and/or an electrical decoupling etc. is/are achieved.

[0105] In particular, the compact design and the relative independence of process technologies applied for producing the component structures enable a selection of the positions of the vias 150 with and without electrical interconnection to a corresponding contact surface 5a on the front side, and/or an electrical connection to a contact point, e.g. a solder bump 13, on the backside.

[0106] FIG. 4 schematically shows a cross-sectional view, in which the component 100 comprises vias 150, 150′ which include the hollow conductive structures 110 in the contact holes 14, 14′, and which are provided in a manner connected to a component structure 5 or 5′ and/or are arranged in the vicinity thereof in order to fulfill a corresponding function, e.g. an electrical interconnection, a mechanical interconnection, a shielding or the like. One or more vias 150, 150′ can be connected to one or more solder bumps 13, 13′, as specified by the design rules.

[0107] A printed circuit board 17 has suitable contact points 16, 16′ which are connected to the correspondingly associated solder bumps 13 or 13′ in an electrically conductive manner, wherein a passivation 15 of the printed circuit board 17 is provided (on the side of the solder bumps). Connecting the printed circuit board 17 to the at least one component 100 (also called chip) can be accomplished by reflow soldering or other contacting methods. The “suitable” contact points 16 are to be understood such that they enable a spatial-geometrically fitting docking to the solder bumps in order to produce conductive contact(s) to the printed circuit board 17.

[0108] The examples of the invention thus provide methods and components in which a via is produced on the basis of a process flow which is not specifically tailored to production technologies for semiconductor devices.

[0109] Thus, the corresponding components in the form of mechanical, electrical, optoelectronic, and/or optical components are completely processed before starting actual production of the via. Due to a suitable selection of process parameters, especially with respect to the maximum process temperature occurring in the production of the via, a high degree of flexibility is achieved in terms of the process technologies to be applied previously.

[0110] In particular, a well-conducting material in the form of a lining of a contact hole is provided for the via so that, in total, at least one hollow conductive structure is produced, which is much less subject to the problems of plastic-elastic deformation, as is known, for example, for completely or almost completely filled copper vias. At the same time, a high degree of material saving is achieved.

[0111] In advantageous embodiments, especially several layers of the conductive lining are produced by means of a metal-organic vapor phase in an in-situ process so that a high degree of reliability is achieved in the processing and in the production of a thin, but yet covering material layer as a basis for the subsequent deposition of the actual conductive material.