Method for the creation of an electronic signal box replacing an existing signal box

Abstract

According to one aspect of the invention, the circuit logic of an existing relay interlocking system is mapped onto a functionally equivalent circuit of electronic components. Semiconductor components that are functionally identical to the components of the relay circuit are thus preferably used. The circuit logic is created, for example, by transforming an interlocking table or track diagram into a logic circuit by means of an automatic compiler according to predefined rules.

Claims

1. A method for setting up an electronic signal box as a replacement for an existing signal box, comprising the steps of: providing the existing signal box, the existing signal box being connected to components to be actuated for the rail transportation and to actuate said components, the existing signal box having a switching logic, providing the switching logic of the existing signal box in an electronically readable form, mapping, by means of a transformation, the switching logic onto a logic function that corresponds to the electronic representation of a logic circuit, that is functionally equivalent with the switching logic, using the representation to physically configure a configurable logic circuit being a circuit of electronic semiconductor parts, whereby the switching logic of the existing signal box is physically mapped onto the functionally equivalent configurable logic circuit by means of the transformation, and connecting outputs of said configurable logic circuit to at least some of the existing components to be actuated; and whereby the configurable logic circuit actuates the components to be actuated without the use of a processor.

2. The method as claimed in claim 1, wherein the configurable logic circuit comprises at least one Field Programmable Gate Array (FPGA).

3. The method as claimed in claim 1, wherein the outputs of said circuit are connected to the components to be actuated via component-specific input and/or output units without integrated logic or with integrated logic.

4. The method as claimed in claim 1, wherein the signal box to be replaced is a relay signal box.

5. The method according to claim 1, wherein the electronically readable form comprises an interlocking plan or a track plan for the relay signal box.

6. The method as claimed in claim 5, comprising the further steps of translating the logic circuit back into a comparison plan, by applying inverted rules, and of comparing the interlocking plan (V) or track plan (S) with the comparison plan.

7. The method as claimed in claim 6, comprising the further step of producing related metadata and wherein the step of translating back involves the metadata being used in order to present the comparison plan so as to be able to be compared with the interlocking plan.

8. The method as claimed in claim 1, wherein the logic circuit has a logic unit and a plurality of input and/or output units, wherein the logic circuit is connected to the input and/or output units in a star shape.

9. The method as claimed in claim 1, wherein the circuit has a logic unit and a plurality of input and/or output units, wherein the logic circuit is connected to the input and/or output units in a ring architecture, with communication taking place simultaneously in both directions along the ring.

10. The method as claimed in claim 9, wherein the communication takes place in data packets which each represent the overall state of the system, wherein the communication takes place periodically.

11. The method as claimed in claim 10, wherein comprising the further step of recording the communication by an observer unit.

12. The method as claimed in claim 1, wherein the logic circuit has two redundant logic units which both execute the same logic function and output the results, respectively, wherein, if the results do not match, a safe state is entered and/or an alarm is triggered.

13. An electronic signal box as a replacement for an existing signal box for a rail transportation, wherein the existing signal box is connected to components to be actuated for the rail transportation before the existing signal box is replaced by the electronic signal box and includes a switching logic physically mapped onto hardware, the electronic signal box comprising an electronic logic unit comprising a configurable logic circuit and a plurality of input and/or output units for actuating the components, the input and/or output units connected to at least some of the components, wherein the configurable logic circuit is a circuit of electronic semiconductor parts functionally equivalent to the switching logic of the existing signal box, and whereby the configurable logic circuit actuates the components to be actuated without the use of a processor.

14. The signal box as claimed in claim 13, wherein the at least one configurable logic circuit is a Field Programmable Gate Array (FPGA).

15. The signal box as claimed in claim 13, wherein the logic unit is free of microprocessors.

16. The signal box as claimed in claim 13, further comprising a second logic unit which is functionally equivalent to the logic unit, wherein the logic unit and the second logic unit both output control signals to the input and/or output units, respectively.

17. The signal box as claimed in claim 16, wherein the second logic unit has at least one property different from a corresponding property of the first logic unit.

18. The method as claimed in claim 1, wherein physically configuring the configurable logic circuit comprises at least one of: activating particular switch positions in the configurable logic circuit; de-activating particular switch positions in the configurable logic circuit.

19. The signal box as claimed in claim 13, wherein the switching logic is stored in a memory.

Description

(1) Embodiments of the invention are described in more detail below with reference to schematic drawings, in which identical reference symbols (identification letters) denote the same or similar elements and in which:

(2) FIG. 1 shows a method according to the first aspect of the invention for building an electronic signal box;

(3) FIG. 2 shows a method according to the second aspect of the invention for designing a logic circuit for an electronic signal box;

(4) FIG. 3 shows a first embodiment of the architecture of the electronic circuit;

(5) FIG. 3a shows a variant of the embodiment shown in FIG. 3;

(6) FIG. 4 shows a further, alternative embodiment of the architecture of the electronic circuit;

(7) FIG. 5 shows a variant of the embodiment shown in FIG. 4, with two logic units; and

(8) FIG. 6 takes the embodiment shown in FIG. 4 as a basis for schematically showing the connection to elements of the external installation; and

(9) FIG. 7 shows an example of a signal box architecture of the type according to the invention.

(10) As FIG. 1 shows, an interlocking plan V (or a track plan S, not shown) is captured by a computer Comp, for which a special input unit I may optionally be provided. The input unit may, if appropriate, be attuned to the format of the interlocking plan and may have a scanner and also an appropriate piece of software for recognizing and capturing the symbols in the interlocking plan, for example. It goes without saying that the interlocking plan may also already have been in electronically readable form from the outset. From the captured interlocking plan, the computer Comp produces a logic function L#. The logic function corresponds to the electronic representation of a logic circuit. It is mapped onto a physical logic circuit which is implemented in a programmable logic chip (FPGA).

(11) The method for producing the logic function L# from the interlocking plan V (or a track plan S) is shown schematically in FIG. 2 in a specific embodiment which allows verification. From the interlocking plan V or the track plan S, a suitable translation program T will ascertain the logic function L#. In the embodiment shown here, the translation program also creates a file M containing metadata, which are not safety-related and, by way of example, contain information relating to the presentation of the interlocking plan. In order to allow verification, a reverse translation program T.sup.−1 produces a comparison plan V′/S′ from the logic function L# using ‘Reverse Engineering’, said comparison plan being designed, on the basis of the metadata, such that, by way of example, a similar presentation is made or the same names are used when using names for variables or signals. The comparison C is performed by a checking person or can alternatively also be performed by the/a computer, in which case the metadata can also be made available to the comparing program instead of being used for producing the comparison plan V′/S′.

(12) In specific instances—for example in the event of a nonstandard signal location—a user can use an appropriate manually controllable input option (Man) to perform manual customization.

(13) The implementation of a logic function L# on an FPGA, which is then equipped as a logic unit, is known per se.

(14) As a variant of the method described above, it is also possible to reverse engineer the implemented logic unit L instead of the logic function L#.

(15) FIG. 3 shows a star-shaped connection between the logic unit L (on which the logic function L# is implemented) and the input/output units IO.sub.1 . . . IO.sub.n. As mentioned, in all embodiments, the input/output units preferably have similar dimensions to the original relay units and also have similar connecting structures to the external installations, which means that only minor changes or no changes at all need to be made to the external installations.

(16) The reference symbol S denotes a communication input for the communication with an input unit and/or with a superordinate system.

(17) In a variant which is shown in FIG. 3a, the logic unit L is likewise connected to the input/output units in a star shape; however, this is done via a switch X.

(18) The architecture shown in FIG. 4 is a ring-shaped architecture. The logic unit L is connected to the input/output units IO.sub.1 . . . IO.sub.n in a ring shape. Whereas the wiring in a star-shaped architecture is designed to be parallel (even a parallel architecture allows the optional use of serial protocol), it may be of either parallel or serial design in the case of a ring-shaped architecture. In the exemplary embodiment shown, the communication is serial, i.e. the data packet transmitted by the logic unit, for example periodically, contains data which contain the overall system state (switching state of each component to be actuated). Each input/output unit is addressed and takes the information it requires from the data packet. Since each data packet contains all the information, it is also suitable for monitoring the system and/or logging. For this purpose, the signal is also forwarded to a “black box” B via the communication system CB. There, the successively arriving data packets are stored and/or analyzed, usefully during operation.

(19) A further interface allows the communicated state to be reliably transmitted to management systems or, for operation under ETCS, to the ‘Radio Block Center’ (RBC). The same path can be used to transmit routes which are requested by the management system or by an automation element to the digital signal box.

(20) Besides the logic unit L, the embodiment shown in FIG. 5 has a second, functionally equivalent and possibly identical, logic unit L*. The control inputs S, S* of the logic units are also identical and are actuated in identical fashion. The control signals from L and L* are forwarded to the input/output units IO.sub.0 . . . IO.sub.n. by the communication system CB. In the normal operating situation, the signals from L and L* should be identical. If they are not identical, there is an error in one of the logic units L or L*, or in one of the superordinate systems S or S*. In this case, the input/output units IO.sub.0 . . . IO.sub.n can enter a “safe state” (e.g. change signal to red) and trigger an alarm. The alarm can naturally also be triggered by the “black box” B.

(21) Embodiments having two logic units which ensure redundancy can, per se, also be used for star architectures or mixed architectures.

(22) As a special safety feature of embodiments which are preferred in many cases, it is possible to use a different make, which is not of identical design to the logic unit L, sometimes from a different supplier, for the logic unit L* than for the logic unit L. This results in diversitary redundancy.

(23) It is a great advantage of the course of action according to the invention based on all aspects of the invention that the logic unit can be implemented by a comparatively simple means on account of the approach according to the invention. This provides the first opportunity to have the approach to two logic units operating in parallel totally independently of one another, which would be virtually impossible in the case of electronic signal boxes, for example. This in turn allows the diversitary redundancy which is often very desirable in safety engineering.

(24) By way of example, the independence of the two logic units can mean that the logic units do not exchange interim results, or even that no signals at all from one control unit are processed by the other control unit.

(25) FIG. 6 uses the example from FIG. 4 to schematically show the connection to the external installation. The black line printed in bold symbolizes the boundary between the building which contains the signal box and the “outside”. The input and/or output units are each associated with an actuating element of the external installation, for example the unit IO.sub.B1 is associated with the block B1, the unit IO.sub.W1 is associated with the points W1, the unit IO.sub.S11 is associated with the signal S11, etc. The interface between the existing cabling of the external installation and that of the replaced signal box forms a cable distributor V, which is likewise preferably inside the building.

(26) FIG. 7 shows an example involving a simple external installation with the rail progression shown at the bottom of the figure. The boxes B1 and B2 in the lower half of the figure denote the route blocks 1 and 2, W1 and W2 denote points, Sij are signals, and GFM1 and GMF2 are track release units. In the upper half of the figure (in the internal installation), the correspondingly labeled boxes denote the input and/or output units associated with the respective elements.

(27) In the example shown here, the cabling of the logic unit (FPGA) in a ring architecture with the input and/or output units is of serial design as an Ethernet bus. The external cabling running away from the cable distributor to the outside can be adopted in unaltered form from the relay signal box.