Method for creating a connection between metallic moulded bodies and a power semiconductor which is used to bond to thick wires or strips

Abstract

The invention relates to a method for connecting a power semi-conductor chip having upper-sided potential surfaces to thick wires or strips, consisting of the following steps: Providing a metal molded body corresponding to the shape of the upper-sided potential surfaces, applying a connecting layer to the upper-sided potential surfaces or to the metal molded bodies, and applying the metal molded bodies and adding a material fit, electrically conductive compound to the potential surfaces prior to the joining of the thick wire bonds to the non-added upper side of the molded body.

Claims

1. A method for creating a connection of a power semiconductor chip having upper side potential faces with thick wires or strips, comprising: providing a carrying sheet with a plurality of metallic moulded bodies corresponding to the shape of the upper side potential faces, wherein the carrying sheet has a plurality of windows provided above central partial faces of the plurality of metallic moulded bodies, applying a bonding layer on the upper side potential faces or the plurality of metallic moulded bodies, placing the plurality of metallic moulded bodies and creating a cohesive, electrically conducting connection to the upper side potential faces, and removing the carrying sheet after bonding the plurality of metallic moulded bodies to the upper side potential faces.

2. The method for creating a connection of a power semiconductor chip according to claim 1, wherein the moulded bodies provided comprise at least one metal of the group of Cu, Ag, Au, Mo, Al, W or their alloys, the alloys comprising one or more of the metals of the group mentioned.

3. The method for creating a connection of a power semiconductor chip according to claim 1, wherein by means of the bonding layer, moulded bodies and potential faces are bonded by means of sintering, diffusion soldering or gluing to the power semiconductor chip.

4. The method for creating a connection of a power semiconductor chip according to claim 1, wherein the carrying sheet is an organic carrying sheet.

5. The method for creating a connection of a power semiconductor chip according to claim 1, wherein an additional moulded body having the shape of a bottom side of the power semiconductor chip is provided to be cohesively connected with a bonding layer on the bottom side of the power semiconductor chip lying opposite to the upper side potential faces.

6. The method for creating a connection of a power semiconductor chip according to claim 1, wherein an electrically insulating material that can resist the thermal load of the bonding is used for the carrying sheet.

7. The method for creating a connection of a power semiconductor chip according to claim 1, wherein the carrying sheet with a number of moulded bodies corresponding to the number of potential faces is applied on two or more unseparated power semiconductor chips before bonding.

8. The method for creating a connection of a power semiconductor chip according to claim 1, wherein the carrying sheet is removed while the power semiconductor chip is unseparated.

9. The method for creating a connection of a power semiconductor chip according to claim 1, wherein above the central partial faces of the moulded bodies meant for bonding, the carrying sheet is not provided with adhesive.

10. The method for creating a connection of a power semiconductor chip according to claim 2, wherein by means of the bonding layer, moulded bodies and potential faces are bonded by means of sintering, diffusion soldering or gluing to the power semiconductor chip.

11. The method for creating a connection of a power semiconductor chip according to claim 2, wherein the carrying sheet is an organic carrying sheet.

12. The method for creating a connection of a power semiconductor chip according to claim 3, wherein the carrying sheet is an organic carrying sheet.

13. The method for creating a connection of a power semiconductor chip according to claim 2, wherein an additional moulded body having the shape of a bottom side of the power semiconductor chip is provided to be cohesively connected with a bonding layer on the bottom side of the power semiconductor chip lying opposite to the upper side potential faces.

14. The method for creating a connection of a power semiconductor chip according to claim 3, wherein an additional moulded body having the shape of a bottom side of the power semiconductor chip is provided to be cohesively connected with a bonding layer on the bottom side of the power semiconductor chip lying opposite to the upper side potential faces.

15. The method for creating a connection of a power semiconductor chip according to claim 4, wherein an additional moulded body having the shape of a bottom side of the power semiconductor chip is provided to be cohesively connected with a bonding layer on the bottom side of the power semiconductor chip lying opposite to the upper side potential faces.

16. The method for creating a connection of a power semiconductor chip according to claim 2, wherein an electrically insulating material that can resist the thermal load of the bonding is used for the carrying sheet.

17. The method for creating a connection of a power semiconductor chip according to claim 3, wherein an electrically insulating material that can resist the thermal load of the bonding is used for the carrying sheet.

18. The method for creating a connection of a power semiconductor chip according to claim 4, wherein an electrically insulating material that can resist the thermal load of the bonding is used for the carrying sheet.

19. The method for creating a connection of a power semiconductor chip according to claim 5, wherein an electrically insulating material that can resist the thermal load of the bonding is used for the carrying sheet.

20. The method for creating a connection of a power semiconductor chip according to claim 2, wherein the carrying sheet with a number of moulded bodies corresponding to the number of potential faces is applied on two or more unseparated power semiconductor chips before bonding.

21. A method for creating a connection of a power semiconductor chip having upper side potential faces with thick wires or strips, comprising: providing a carrying sheet with a plurality of metallic moulded bodies corresponding to the shape of the upper side potential faces, wherein the carrying sheet does not have adhesive above central partial faces of the plurality of metallic moulded bodies meant for bonding, applying a bonding layer on the upper side potential faces or the plurality of metallic moulded bodies, placing the metallic moulded bodies and creating a cohesive, electrically conducting connection to the potential faces, wherein there is no thick-wire bonded on non-bonded upper sides of the plurality of metallic moulded bodies; and removing the carrying sheet after bonding the plurality of metallic moulded bodies to the upper side potential faces.

22. The method for creating a connection of a power semiconductor chip according to claim 1, further comprising the step of: thick-wire bonding on non-bonded upper sides of the plurality of metallic moulded bodies.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Further advantages and features of the invention occur from the following description of a preferred embodiment by means of the enclosed figures, showing:

(2) FIG. 1 a view of a carrying foil 1 with a fixing layer 2 on a metal foil 3,

(3) FIG. 2 a structuring of the metal foil into individual moulded bodies 4; 5,

(4) FIG. 3 the elements of FIG. 2 to be connected on a wafer assembly 6, on which bonding layers 7 of sintering metal on metallisation layers 8 have been applied,

(5) FIG. 4 the sintering step with pressure and, if required, heat,

(6) FIG. 5 the step of removing the carrying foil 1 and the fixing layer 2,

(7) FIG. 6 a rough sketch of the sawing process of the semiconductor components with moulded bodies fixed thereon by sintering,

(8) FIG. 7 a chip 12 with moulded body 4, and

(9) FIG. 8 the chip of FIG. 7 with an additional oxidation inhibiting layer 10.

DETAILED DESCRIPTION

(10) The advantages obtained by the method for creating a connection of a power semiconductor chip with upper side potential faces to thick wires or strips particularly include that neither during bonding nor by preceding or subsequent steps there is a risk of damaging the thin metallisation layers or structures of the semiconductor, and an improved current distribution is achieved. With copper thick wire bonding (for example up to 600 μm diameter of the wires), the current now runs from central fixing areas of the wires on the moulded bodies in a distributed manner through a moulded body to the corresponding potential faces of the substrate surface.

(11) In this connection, it is suggested that to perform the method described schematically in FIGS. 1 to 8 for connecting a power semiconductor chip 12 with upper side potential faces with thick wires by means of the following steps: Providing a metallic moulded body 4; 5 corresponding to the shape of the upper side potential faces, applying a bonding layer 7 on the upper side potential faces or on the metallic moulded bodies 4; 5, and creating a cohesive, electrically conductive connection with the potential faces before a thick wire bonding on the non-bonded upper side of the moulded body 4;5.

(12) Not shown, but being the scope of a preferred variant is that an additional moulded body in the shape of the chip is provided on the bottom side of the power semiconductor chip 12 and is connected cohesively to the bottom side of the power semiconductor chip 12 opposite to the upper side potential faces by means of a bonding layer.

(13) Materials for the moulded bodies 4; 5 are, for example, metals of the group Cu, Ag, Au, Mo, Al, W or their alloys, the alloys comprising one or more metals of the group mentioned.

(14) For the bonding layer for fixing the moulded bodies 4; 5 on the upper side potential faces, low-temperature sintering technology, diffusion soldering or gluing to the power semiconductor chip 12 is provided, and it is further suggested that that the moulded bodies 4; 5 provided with a sintering layer for joining are covered with silver or nickel-gold before applying the sintering material. The alternative is that the sintering material is applied on metallisation layers 8, for example, the upper side potential faces of, for example, a wafer assembly 6 (FIG. 3).

(15) As material, on which the moulded body 4; 5 is provided, a flexible organic carrying foil 1, for example of polyimide or polyamide, is suggested. A plurality of other materials, for example NOMEX foil, can be imagined to form an electrically isolating carrying sheet that can resist the thermal load of bonding, also for large areas, for example a wafer assembly 6 of carrying foil.

(16) The carrying sheet, provided with a number of moulded bodies 4; 5 corresponding to the number of potential faces, can then be placed on one or more, particularly not yet divided, power semiconductor chips 12 of a wafer assembly 6 before joining. An adhesive layer 2 keeps the moulded bodies 4; 5 on the carrying sheet. After bonding, the carrying sheet can be pulled off from the moulded bodies 4; 5, so that it does not prevent the thick wire bonding. An alternative embodiment, in which the carrying sheets have punched holes for the thick wire bonding, is also possible. Here, the carrying sheet would remain, at least as an edge that could, if required, have some sort of protective function.

(17) In an alternative embodiment, the detachable carrying foil has areas, on which no adhesive of a fixing layer 2 has been provided on partial faces, or even punched or otherwise opened areas (“windows”) created in the foil in the area of, for example, the centre of the upper side of the moulded unit.

(18) These windows, which are preferable provided above the central partial faces of the moulded bodies, which are prepared for bonding, make it easier to fulfil the requirement for undamaged surfaces, particularly surface areas without adhesive residues, for the subsequent thick wire bonding.

(19) Thus, the method according to the invention provides several advantages: The moulded bodies enables an upper side connection by means of thick copper wires and copper strips, also with thin semiconductor elements. The moulded bodies protect the sensitive thin metallised surfaces of the semiconductors (typically only around 3-4 μm) during the thick copper wire bonding. The moulded bodies ensure an improved current density distribution over the complete cross-section of the chip surface. The moulded bodies protect the sensitive surface structure of the semiconductor during frictional contacting by means of sprung contacts. This simplifies the non-destructive, electrical quality testing in the production lines. By means of a symmetrisation of the mechanical stresses, a bottom side layer prevents the dishing effect (deformation of the semiconductor element). Upper and lower side carrying foils form conducting face areas, which can cover a complete wafer, thus permitting, in a cost efficient and exact manner, the parallel contacting of all contact faces.

(20) Although various embodiments of the present invention have been described and shown, the invention is not restricted thereto, but may also be embodied in other ways within the scope of the subject-matter defined in the following claims.