Device for electrically testing the interconnections of a microelectronic device

Abstract

A simultaneous electrical testing device for TSV interconnection elements passing through a substrate and including one end connected to an integrated testing circuit and another end to a removable connection mechanism assembled to the substrate through an anisotropic conductive glue.

Claims

1. A device for electrically testing a microelectronic device, comprising: at least a first plurality of interconnection elements passing through a substrate and including a first end located at a first face of the substrate and a second end connected to a testing circuit, removable connection means, provided on the first face of the substrate, for enabling a temporary short-circuit to be set between plural interconnection elements, the first end of the interconnection elements being connected to the removable connection means, wherein the testing circuit comprises means for simultaneously applying through the interconnection elements at least one connectivity testing electrical signal, between plural interconnection elements of the first plurality of interconnection elements, and for sampling at an output of the testing circuit a signal in response to the connectivity testing signal, wherein the removable connection means comprises a handle carrier comprising distinct conductive areas assembled to the substrate through an anisotropic conductive glue, wherein the testing circuit comprises at least one logic gate connected to interconnection elements of the first plurality of interconnection elements and configured to allow a simultaneous connectivity test of the interconnection elements, and wherein respective different potentials are applied to the conductive areas of the handle carrier.

2. The electrical testing device according to claim 1, wherein the testing circuit is integrated into the substrate.

3. The electrical testing device according to claim 1, wherein the testing circuit further comprises charging means or pulling means at an output of the gate, to force the output of the gate at a given potential.

4. The electrical testing device according to claim 1, wherein the removable connection means is polarized and connected to the handle carrier.

5. The electrical testing device according to claim 1, wherein the microelectronic device includes a second plurality of interconnection elements passing through the substrate, the second plurality of interconnection elements being connected to another testing circuit, the second testing circuit being connected to the first testing circuit.

6. The electrical testing device according to claim 1, wherein the testing circuit comprises a DFT type circuit.

7. The electrical testing device according to claim 1, wherein the handle carrier is further covered with anti-adhesive areas.

8. A method for electrically testing interconnection elements using the device according to claim 1, comprising: carrying out at least one electrical testing of interconnection elements passing through the substrate by simultaneously applying at least one electrical signal through plural of the interconnection elements and by sampling, at the output of the testing circuit, a signal in response to the electrical signal applied; and removing the removable connection means from the first face of the substrate.

9. A device for electrically testing a microelectronic device, comprising: at least a first plurality of interconnection elements passing through a substrate and including a first end located at a first face of the substrate and a second end connected to a testing circuit, removable connection means, provided on the first face of the substrate, for enabling a temporary short-circuit to be set between plural interconnection elements, the first end of the interconnection elements being connected to the removable connection means, and means for simultaneously applying through the interconnection elements at least one connectivity testing electrical signal between plural interconnection elements of the first plurality of interconnection elements and for sampling at an output of the testing circuit a signal in response to the connectivity testing signal, wherein the removable connection means comprises a handle carrier comprising distinct conductive areas assembled to the substrate through an anisotropic conductive glue, and wherein respective different potentials are applied to the conductive areas of the handle carrier.

10. The electrical testing device according to claim 9, wherein the testing circuit is integrated to the substrate.

11. The electrical testing device according to claim 9, wherein the testing circuit further comprises charging means or pulling means at an output of the gate, to force the output of the gate at a given potential.

12. The electrical testing device according to claim 9, wherein the removable connection means is polarized and connected to the handle carrier.

13. The electrical testing device according to claim 9, wherein the microelectronic device includes a second plurality of interconnection elements passing through the substrate, the second plurality of interconnection elements being connected to another testing circuit, the second testing circuit being connected to the first testing circuit.

14. The electrical testing device according to claim 9, wherein the testing circuit comprises a DFT type circuit.

15. The electrical testing device according to claim 9, wherein the handle carrier is further covered with anti-adhesive areas.

16. The electrical testing device according to claim 9, wherein the testing circuit includes at least one logic gate connected to interconnection elements of the first plurality of interconnection elements and configured to allow a simultaneous connectivity test of these interconnection elements.

17. A method for electrically testing the interconnection elements using the device of claim 9, comprising: carrying out at least one electrical testing of interconnection elements passing through the substrate by simultaneously applying at least one electrical signal through plural of the interconnection elements and by sampling at the output of the testing circuit a signal in response to the electrical signal applied; and removing the removable connection means from the first face of the substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will be better understood upon reading the description of exemplary embodiments given by way of indicating and in no way limiting purposes, making reference to the appended drawings wherein:

(2) FIG. 1 represents a first example of a device for electrically testing interconnections formed by conductive elements passing through a substrate and provided with one end connected to an electrical testing circuit and another end connected to means temporarily carrying out an electrical connection of at least several of said conductive elements;

(3) FIG. 2 illustrates a second example of an electrical testing device, wherein chips formed on a substrate are provided with conductive elements passing through the substrate and connected through one of their ends to an electrical testing circuit, these conductive elements having another end connected to a removable connection island and temporarily provided against the substrate for the duration of an electrical test;

(4) FIG. 3 illustrates a third example of an electrical testing device, wherein several chips formed on a substrate are each provided with a plurality of conductive elements passing through the substrate and each associated with an electrical testing circuit, one or more of said testing circuits being connected to each other;

(5) FIG. 4 illustrates an example of an electrical testing device, for TSV type interconnection elements both connected to a temporary connection island and to an integrated electrical testing circuit, this testing circuit being associated with an evaluation circuit;

(6) FIGS. 5, 6, 7 illustrate different examples of electrical testing devices for TSV type interconnection elements connected to a testing circuit performing a logic function;

(7) FIG. 8 illustrates an example of an electrical testing device for series of testing TSV type interconnection elements performing a logic function;

(8) FIG. 9 illustrates an example of particular arrangement of an electrical testing device;

(9) FIG. 10 illustrates an arrangement of removable connection islands provided for implementing an electrical test on TSV type interconnection elements of a microelectronic device, the connection islands being provided to connect several TSV type interconnection elements during an electrical testing phase and being intended to be removed once this testing phase is completed;

(10) FIGS. 11A-11C illustrate an example of implementation of a method of manufacturing connection islands intended for the implementation of an electrical test on TSV type interconnection elements;

(11) FIG. 12 illustrates an example of an electrical testing device for interconnections wherein conductive interconnection elements passing through a substrate and provided with one end connected to an electrical testing circuit have another end connected to a conductive area of a handle carrier to make temporarily an electrical connection between at least several of said conductive interconnection elements, the handle carrier and substrate being assembled through an anisotropic conductive glue;

(12) FIG. 13 illustrates an example of device similar to that of FIG. 12, but wherein the handle carrier is covered with anti-adherent areas to facilitate the subsequent removal of the handle carrier.

(13) Identical, similar or equivalent parts of the different figures bear the same reference numerals so as to facilitate switching from one figure to the other.

(14) Different parts represented in the figures are not necessarily drawn at a uniform scale, for making the figures more understandable.

DETAILED DISCLOSURE OF PARTICULAR EMBODIMENTS

(15) A first example of device for implementing electrical test(s) on one or several TSV type interconnection elements provided in a chip, is given in FIG. 1.

(16) In this example, a chip 102 includes TSV type interconnection elements 107a, 107b, 107c passing at least partly through the thickness of a carrier. This carrier can in particular be a semi-conductor substrate, on which or from which the chip 102 is formed.

(17) These connection elements 107a, 107b, 107c include a conductive portion or conductive area passing through the thickness of the semi-conductor substrate.

(18) This conductive portion can for example be in the form of a post, possibly in contact with one or more so-called “redistribution” conductive layers and/or with one or more conductive beads. The conductive portion can be metallic and for example based on copper or aluminium, or comprise a silver, gold, titanium or tin based conductive material.

(19) The connection elements 107a, 107b, 107c can be each surrounded with an area of dielectric material enabling an insulation relative to the substrate to be made.

(20) The semi-conductor substrate 100 can have been thinned and have a thickness between for example 1 and 200 micrometers.

(21) On one side of the chip 102, for example on the side of a first face of the substrate which will be called “upper face”, a first end of the connection element(s) 107a, 107b, 107c is connected to a testing circuit 116.

(22) On the other side of the chip 102, for example on the side of a second face of the substrate opposite to the first face which will be called “lower face”, a second end of the connection element(s) 107a, 107b, 107c is in contact with a connection island 115.

(23) This connection island 115 enables an electrical contact to be set between the interconnection elements 107a, 107b, 107c or between several of the interconnection elements 107a, 107b, 107c.

(24) The connection island 115 is also removable, that is it can be dissociated or disassembled from the chip 102, and in particular without damaging the same. The connection island 115 can also be provided so as to be temporarily assembled with the chip 102, for the duration of one or more electrical tests performed on the TSV elements 107a, 107b, 107c.

(25) Thus, in FIG. 1, the device is represented in a testing phase, when the connection island 115 is connected to the TSV elements 107a, 107b, 107c. When this testing phase is completed, the connection island 115 is preferably removed.

(26) The testing circuit 116 can as for it be integrated to the chip 102 and formed by so-called “front-end-of-line” (FEOL) or “front end”, in particular transistors, as well as so-called “back-end-of-line” (BEOL) or “back end” elements, in particular metal interconnections.

(27) The testing circuit 116 can be provided to make a connection with each TSV type interconnection element 107a, 107b, 107c taken singly and/or to make a connection with a group of interconnection elements 107a-107b, or 107b-107c, or 107a-107c, or with the assembly 107a-107b-107c of all the TSV interconnection elements of the chip 102.

(28) Thus, an electrical test can be performed on a group of interconnection elements 107a-107b, or 107b-107c, or 107a-107c, or even on the assembly of all the TSV interconnection elements of the chip 102. This test can in particular be that of the electrical conductivity of the interconnection elements 107a, 107b, 107c.

(29) The testing circuit 116 can also be associated with DFT elements or at least one DFT (for “Design for Test” or “Design for Testability”) circuit, for example a DFT circuit using a testing technique such as described in document “Scan Chain Design for Test Time Reduction in Core-Based ICs” Joep Aerts and Erik Jan Marinissen, IEEE Test Conference, 1998.

(30) The DFT circuit can be formed by logic blocks temporarily connected during a testing phase, through which a data string passes which will be recovered at the output to ensure continuity and functionality of the logic blocks.

(31) A second example of an electrical testing device is illustrated in FIG. 2.

(32) In this example, a chip 202 is provided with a first assembly of connection elements 107a, 107b, 107c passing through at least one part of the thickness of a substrate on which this chip is formed, these interconnection elements 107a, 107b, 107c being connected on one side of the substrate to a first integrated testing circuit 116, and on another side of the substrate, to a first connection island 115 temporarily assembled with the chip 202.

(33) The chip 202 also includes a second assembly of connection elements 207a, 207b, 207c passing through at least one part of the thickness of the substrate and juxtaposed to the first assembly of connection elements 107a, 107b, 107c. The connection elements 207a, 207b, 207c include one end connected to a second testing circuit 216 and the other end to a second connection island 215 temporarily adjoining the chip 202.

(34) The first connection island 115 and the second connection island 215 are also removable and likely to be removed from the face of the substrate into which the connection elements 107a, 107b, 107c, 207a, 207b, 207c open.

(35) The first testing circuit 116 and the second testing circuit 216 are as for them connected to each other through an interconnection line 226, which can be for example one of the metal lines of the chip 202 which are parallel to the substrate 100 and belonging to the back-end area of the chip 202.

(36) The first testing circuit 116 and the second testing circuit 216 can be configured such that one or more elements of the first assembly of interconnection elements 107a, 107b, 107c are likely to be connected to one or more interconnection elements of the second assembly of interconnection elements 207a, 207b, 207c.

(37) The testing circuits 116 and 216 can be configured so as to select and connect several elements among the TSV type interconnection elements 107a, 107b, 107c of the first assembly with several elements among the TSV type interconnection elements 207a, 207b, 207c of the second assembly.

(38) A series chaining of pairs of TSV interconnection elements can thus be made.

(39) FIG. 3 illustrates an alternative of the example of device previously described, for which a logic circuit 228 or an assembly 228 of logic circuits is provided between the first testing circuit 116 and the second testing circuit 216 and connected to the same.

(40) The logic circuit 228 or the assembly 228 of logic circuits can be provided with a functional logic block of the type commonly called “intellectual property” or PI, possibly associated with one or more DFT type elements.

(41) FIG. 12 illustrates another alternative of either of the examples previously described, wherein a removable connection island 315 is in the form of a substrate or handle carrier 130, provided with a first conductive area 131, and a second conductive area 132, the first conductive area 131 enabling the elements 107a, 107b, 107c of the first assembly of interconnection elements to be electrically connected, whereas the second conductive area 131 enables the elements 207a, 207b, 207c of the second assembly of interconnection elements to be electrically connected respectively. The conductive areas 131, 133 have an arrangement which depends on that of the interconnection elements 107a, 107b, 107c, 207a, 207b, 207c in the chip 202.

(42) The assembly of the handle carrier 130 to the chip 202 is performed by means of an anisotropic conductive glue 341 which can be formed, for example according to a technique presented in document CN1821336, by mixing conductive particles with filling nanoparticles called “filler”, the mixture being combined with an epoxy type resin and a slow crosslinking agent. Because of the anisotropic conductivity of the glue 341, the conductive areas 131, 133 of the handle carrier are not electrically connected to each other.

(43) An electrical test can thus be performed on the first assembly of interconnection elements 107a, 107b, 107c, and then on the second assembly of interconnection elements 207a, 207b, 207c.

(44) In the example of embodiment of FIG. 13, the anisotropic conductive glue 341 is provided on a face of the handle carrier 130 on which conductive areas 131, 132 are arranged. Around the conductive areas 131, 132, anti-adherent areas 137 are provided to enable the subsequent disassembly between the chip 202 and the handle carrier 130 to be facilitated.

(45) The adherent areas 137 can correspond to regions of the glue 341 the adhesion properties of which have been reduced or removed. This can be performed by exposing regions of the glue to a chemical process which reduces its adhesion strength, such as described for example in the process published in “Ultrathin Wafer Handling in 3D Stacked IC Manufacturing Combining a Novel ZoneBOND™ Temporary Bonding Process with Room Temperature Peel Debonding<<, proceedings of 3DIC, 2011.”

(46) In FIG. 4, a block diagram of a testing device of the type of that previously described in connection with FIG. 1 is given.

(47) The testing circuit 116 can be provided to inject a current or apply a potential or measure the current or the potential at one or more end(s) of the TSV type connection elements 107.sub.1, . . . , 107.sub.N.

(48) A potential can possibly be applied to connection island 115 through 107N, for example enabling the other interconnection elements 1071 to 107N-1 to be connected to each other in order to polarise another end of the other TSV type connection elements 1071 to 107N-1.

(49) In this exemplary embodiment, the electrical testing device is also provided with an evaluation circuit 117 connected to one or more test input and/or output pad(s) 119.

(50) This evaluation circuit 117 is adapted to indicate a possible presence of functional or parametric errors. The circuit 117 can be provided to assess for example the electrical continuity of each TSV element through a current or electrical potential characterising each TSV.

(51) This evaluation circuit can for example be formed by a comparator which compares an output of the device of FIGS. 5, 6 and 7 to an expected value.

(52) In FIG. 5, an embodiment of a testing device including a testing circuit 116 provided with means 121 to make a connectivity test of the TSV type interconnection elements 107.sub.1, . . . , 107.sub.N is given.

(53) A potential V is applied on TSV type connection elements 107.sub.1, . . . , 107.sub.N-1 through a connection island 115 polarised through 107.sub.N.

(54) The means 121 implementing a connectivity testing function can be provided to indicate, for example, whether all the TSV connection elements 107 are placed at a same potential or not.

(55) Charging or pulling means 191 can be further connected at the output of the testing circuit 116, in order to force this output to a determined potential. The signal at the output of the testing circuit 116 can be delivered to an evaluation circuit.

(56) In this exemplary embodiment, multiplexing elements 111.sub.1, . . . , 111.sub.N respectively associated with the connection elements 107.sub.1, . . . , 107.sub.N are provided to enable one end of the connection elements 107.sub.1, . . . , 107.sub.N to be alternately connected to a testing circuit or to another stage, depending on whether the microelectronic device including the TSV connection elements 107.sub.1, . . . , 107.sub.N is in electrical testing mode or normal operating mode.

(57) According to a particular embodiment (FIG. 6), the means 121 performing the connectivity testing function, can comprise means 123 forming an “AND” logic gate as well as a polarisation pad 197.

(58) In this case, a potential V equivalent to a logic “1” is applied to the connection island 115 via the polarisation pad 197, and a result of this testing function is extracted at the output S of the testing circuit 116.

(59) In the case where this result at the output S is a logic “1”, then it can be deduced therefrom that all the TSV elements 107 are conductive.

(60) For this particular embodiment, pulling means 193 commonly called “pull up”, for example in the form of one or more transistors and/or resistors connected to a power supply, can be provided at the output of the testing circuit 116, and force this output to the “1” or high state.

(61) According to another embodiment (FIG. 7), the means 121 performing the connectivity testing function can comprise means 125 forming an “OR” logic gate as well as a polarisation pad 197. In this case, a potential V equivalent to a logic “0” is applied, and a result of this testing function is extracted at the output S of the circuit 116. In the case where this result at the output S is a logic 0, it can then be deduced therefrom that all the TSV elements 107 are conductive. In the case where a floating signal is extracted at the output, then at least one of the TSV elements 107 is not conductive.

(62) For this particular embodiment, pulling means 195 of the type commonly called “pull down”, for example in the form of one or several “pull down” transistors and/or resistors connected to the ground, can be provided at the output of the testing circuit 116, and force this output to a low or “0” state.

(63) According to another possible embodiment, an arrangement including logic gates in cascade with sandwiched DFT testing logic circuits can be implemented.

(64) In the exemplary device of FIG. 8, the TSV connection elements 107a, . . . , 107.sub.N, 207a, 207.sub.N are placed in series and tested through scan chain control means 118, 218 commonly called “scan chain”.

(65) In such a configuration, a first series of TSV elements 107a, . . . , 107.sub.N connected through a connection island 115 are connected to another series of TSV elements 207a, . . . , 207.sub.N connected to another connection island 215. At the input of each series of TSV elements, a multiplexer 126, 226 can be provided which connects this series to a scan chain or even to an electronic circuit, depending on the state of a logic selector (not represented).

(66) At the output of a series of TSV elements TSV 107a, . . . , 107.sub.N, a flip-flop 129 enabling a piece of information to be saved, can be connected to the multiplexer 226 provided at the input of a following series of TSV elements.

(67) When a sequence of signals is injected to one end of a scan chain, this sequence arrives at an opposite end of the chain after a certain time interval and is extracted.

(68) If this extracted sequence is correct, then it can be concluded that no TSV element is defective. If this sequence is modified or attenuated, for example with respect to the sequence injected at the input, it can be deduced therefrom that at least one TSV element is failing.

(69) Another exemplary embodiment is given in FIG. 9, with TSV interconnection elements not passing through the entire thickness of the substrate. An interconnection element 107a has one end opening into the lower face of the substrate 100 and another end provided in the thickness of the substrate 100, but connected through a horizontal conductive line 127 to a conductive pad 129 formed on the upper face of the substrate 100.

(70) In the exemplary embodiment of FIG. 10, a substrate 100 including several chips 102a, 102b each provided with a plurality of TSV interconnection elements (not represented) are connected to conductive areas 131, 132, 133, 134 provided on a temporary handle carrier 130.

(71) The handle carrier 130 can for example be a silicon or glass based plate, enabling a rigid maintenance of the testing device to be ensured and can also be provided with a size similar to that of the thinned semi-conductor substrate 100 on which the chips 102a, 102b are formed.

(72) An anisotropic conductive glue 141 is provided between the handle carrier 130 and the substrate 100 to ensure the assembling and anisotropic electrical conduction, that is in a preferential conduction direction which, in this example, makes a non-zero angle, in particular 90°, with a plane parallel to the main plane of the carrier 130 of the substrate 100 (the main planes of the carrier 130 and the substrate being planes respectively passing through the carrier and the substrate and which are parallel to the plane [O; {right arrow over (i)}; {right arrow over (j)}] of the reference frame [O; {right arrow over (i)}; {right arrow over (j)}; {right arrow over (k)}] given in FIG. 10).

(73) The anisotropic type conductive glue 141 can have been formed by an adhesive low conductive material to which conductive particles passing through the material, for example metal nanowires or nanoparticles or carbon nanotubes have been added.

(74) The example of assembly illustrated in FIG. 10 can be temporarily maintained, during one or more electrical testing phases of the interconnection elements provided in the chips 102a, 102b formed in the substrate 100.

(75) Once this testing phase(s) is (are) performed, the carrier 130 and the substrate 100 can be disassembled. The handle carrier 130 and the connection islands 115 can thus be detached from the substrate 100. This can be made by etching the conductive glue 141. The anisotropic conductive glue 141 can be based on a polymer which can be etched chemically or selectively through plasma with respect to the substrate 100 and the carrier 130.

(76) FIGS. 11A-11C illustrate an exemplary method of making connection islands and assembling these connection islands with a microelectronic device provided with TSV type interconnection elements.

(77) On a carrier 130 intended to act as a handle carrier, a metal layer is formed wherein patterns are made, for example using photolithography or screen-printing steps, in order to form metal areas 131-134. The metal areas 131-134 that are made have an arrangement which depends on that of TSV interconnection elements in a microelectronic device with which the handle carrier 130 is intended to be assembled (FIG. 11A).

(78) This microelectronic device is formed by a semi-conductor substrate 100 wherein the TSV interconnection elements are provided (the TSV interconnection elements being not represented in FIGS. 11A-11C).

(79) Then, the substrate 100 and the handle carrier 130 are assembled (FIG. 11B), such that a face of the substrate 100 into which one end of the interconnection elements opens, is covered with a layer of anisotropic conductive glue 141. The face of the substrate 100 which is covered with the anisotropic conductive glue 141 is then contacted with that of the carrier 130 on which the metal areas 131-134 are arranged.

(80) The anisotropic conductive glue 141 formed on the handle carrier 130 can have a thickness between for example several micrometers and several tens micrometers. This conductive glue 141 can be for example based on an insulating polymer mixed with metal nanoparticles or nanowires or nanotubes.

(81) In this example, connection islands 115 formed by a layer of anisotropic conductive glue 141 in contact with at least one metal area 131-134 are made (FIG. 11C). During the transfer of the substrate 100 onto the carrier 130, a mechanical or optical alignment is implemented to ensure alignment of the metal areas 131-134 with TSV elements.

(82) Following the testing operation, the carrier 130 is for example removed by a chemical attack of the glue 141. The substrate 100 is recovered and then can be glued on a thick adhesive ensuring a certain rigidity in spite of the small thickness of the substrate 100.

(83) Connection islands are provided on a handle carrier 130 which also acts to provide the assembly with a rigidity during the electrical test(s) intended to be subsequently performed on the microelectronic device.