Devices and methods of measuring gain of a voltage-controlled oscillator

Abstract

A voltage-controlled oscillator gain measurement system includes a voltage-controlled oscillator, a voltage detector, and a processor. The voltage-controlled oscillator, which is configured in a phase-locked loop circuit, generates an output signal with an output frequency according to a control signal. The control signal is generated according to the output signal divided by a scaling number. The voltage detector is configured to measure a voltage difference of the control signal. The processor adjusts the scaling number to generate an output frequency difference of the output signal, and obtains a reciprocal gain of the voltage-controlled oscillator by dividing the voltage difference by the output frequency difference.

Claims

1. A voltage-controlled oscillator gain measurement system, comprising: a voltage-controlled oscillator, configured in a phase-locked loop circuit, generating an output signal with an output frequency according to a control signal, wherein the control signal is generated according to the output signal divided by a scaling number; a voltage detector that is a differential analog-to-digital converter, configured to measure a voltage difference of the control signal; and a processor adjusting the scaling number to generate an output frequency difference of the output signal, and obtaining a reciprocal gain of the voltage-controlled oscillator by dividing the voltage difference by the output frequency difference.

2. The voltage-controlled oscillator gain measurement system of claim 1, wherein the phase-locked loop circuit further comprises: a frequency divider, coupled to the processor, generating a feedback signal with a feedback frequency according to the output signal, wherein the feedback frequency equals the output frequency divided by the scaling number.

3. The voltage-controlled oscillator gain measurement system of claim 2, wherein the phase-locked loop circuit further comprises: a phase detector, coupled to the frequency divider, generating an up/down signal by comparing a reference signal and the feedback signal; a charge pump, coupled to the phase detector, receiving the up/down signal to generate a current signal; and a filter, coupled to the charge pump, receiving the current signal to generate the control signal.

4. The voltage-controlled oscillator gain measurement system of claim 1, further comprising: a switch, switched by the processor, coupling the control signal to a first node of the voltage detector to measure a first voltage and coupling the control signal to a second node of the voltage detector to measure a second voltage, wherein the voltage difference is the difference between the first voltage and the second voltage.

5. A method of measuring a gain of a voltage-controlled oscillator configured in a phase-locked loop circuit, comprising: adjusting a scaling number to generate an output signal with a frequency of an output frequency plus an output frequency difference; measuring a first voltage of a control signal; adjusting the scaling number to generate the output signal with a frequency of the output frequency; measuring a second voltage of the control signal; and dividing a voltage difference that is measured by a differential analog-to-digital converter between the first voltage and the second voltage by the output frequency difference to obtain the reciprocal of the gain of the voltage-controlled oscillator, wherein the control signal is generated according to the output signal divided by the scaling number, wherein the output signal is generated according to the control signal.

6. The method of claim 5, further comprising: controlling, by a processor, a frequency divider of the phase-locked loop circuit to adjust the scaling number.

7. The method of claim 6, wherein the control signal is generated by a phase detector, a charge pump, and a filter, wherein an up/down signal is generated by the phase detector comparing a reference signal and a feedback signal, a current signal is generated by the charge pump according to the up/down signal, and the control signal is generated according to the current signal by the filter, and wherein the frequency divider generates the feedback signal by dividing the output signal by the scaling number.

8. The method of claim 5, further comprising: coupling, by a switch switched by a processor, the control signal to a first node of a voltage detector to measure the first voltage; and coupling, by the switch switched by the processor, the control signal to a second node of the voltage detector to measure the second voltage.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

(2) FIG. 1 is a block diagram of an embodiment of measuring the gain K.sub.VCO of the voltage-controlled oscillator in a phase-locked loop circuit; and

(3) FIG. 2 is a block diagram of the conventional device for measuring the gain K.sub.VCO of the voltage-controlled oscillator; and

(4) FIG. 3 is a flow chart of the embodiment in FIG. 1 of measuring the gain K.sub.VCO of the voltage-controlled oscillator in a phase-locked loop circuit.

DETAILED DESCRIPTION OF THE INVENTION

(5) The following description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

(6) FIG. 1 is a block diagram of an embodiment of measuring the gain K.sub.VCO of the voltage-controlled oscillator in a phase-locked loop circuit. As shown in FIG. 1, the phase-locked loop circuit 100 includes the phase detector 101, the charge pump 102, the filter 103, the voltage-controlled oscillator (VCO) 104, the frequency divider 105, the voltage detector 106, the switch 107, and the processor 108. The phase detector 101 receives the reference signal S.sub.R with the reference frequency F.sub.R and the feedback signal S.sub.F with the feedback frequency F.sub.F to generate the up/down signal S.sub.UD for the charge pump 102. The charge pump 102 receives the up/down signal S.sub.UD to generate the current signal I.sub.C with the current I. The filter 103 converts the current signal I.sub.C to the control signal S.sub.C.

(7) The VCO 104 receives the control signal S.sub.C to generate the output signal S.sub.O with the output frequency F.sub.O. The frequency divider 105 receives the output signal S.sub.O to generate the feedback signal S.sub.F, in which the frequency divider 105 divides the output frequency F.sub.O by the scaling number which is controlled by the processor 108 via the division signal S.sub.D. In spite of setting the scaling number of the frequency divider 105, the processor 108 further switches the control signal S.sub.C into the plus node or the minus node of the voltage detector 106, and the voltage detector 106 then sends the voltage difference between the plus node and the minus node V.sub.D back to the processor 108.

(8) According to an embodiment of the invention, when the phase detector 101 detects that the reference frequency F.sub.R is greater than the feedback frequency F.sub.F, the phase detector 101 sends the up/down signal S.sub.UD to the charge pump 102 for decreasing the current value of the current signal I.sub.C. When the phase detector 101 detects that the reference frequency F.sub.R is less than the feedback frequency F.sub.F, the phase detector 101 sends the up/down signal S.sub.UD to the charge pump 102 for increasing the current value of the current signal I.sub.C. In an embodiment of the invention, the filter includes a resistor which converts the current signal I.sub.C into the control signal S.sub.C with a voltage level when the current signal I.sub.C flows through. Namely, the purpose of the phase-locked loop circuit 100 is to keep the feedback frequency F.sub.F equal to the reference frequency F.sub.R, and the output frequency F.sub.O is the feedback frequency F.sub.F multiplied by the scaling number of the frequency divider 105, which is provided by the processor 108. Those skilled in the art may use well known PLL circuits for the phase detector 101, the charge pump 102, the filter 103, the VCO 104, and the frequency divider 105 in accordance with the principles of the present invention.

(9) When the processor 108 provides different scaling numbers, it results in a different control signal V.sub.C and a different output frequency F.sub.O. In order to precisely measure the gain K.sub.VCO of the VCO 104, the processor 108 provides a first scaling number of the frequency divider 105 by the division signal S.sub.D, and it results in the control signal S.sub.C with a first voltage V.sub.1 and the output frequency F.sub.O with a first output frequency F.sub.O1. After the phase-locked loop circuit 100 is stable (i.e., becomes locked at steady state), the processor 108 switches the switch 107 to pass the first voltage V.sub.1 of the control signal S.sub.C to the plus node of the voltage detector 106.

(10) Then, the processor 108 further provides a second scaling number of the frequency divider 105, and it results in the control signal S.sub.C with a second voltage V.sub.2 and the output frequency F.sub.O with a second output frequency F.sub.O2. After the phase-locked loop circuit 100 is stable, the processor 108 switches the switch 107 to pass the second voltage V.sub.2 of the control signal S.sub.C to the minus node of the voltage detector 106. The voltage detector 106 measures the voltage difference V.sub.D of the first voltage V.sub.1 and the second voltage V.sub.2 and sends the voltage difference V.sub.D to the processor 108. The second output frequency F.sub.O2 is designed to differ from the first output frequency F.sub.O1 by a predetermined frequency difference ΔF.sub.O which is determined according to the difference between the second scaling number and first scaling number. In one embodiment, the second output frequency F.sub.O2 may be designed to be the desired output frequency F.sub.O of the PLL, so that the PLL has steady-state output immediately after the gain measurement and does not require additional time to further lock to a desired output frequency.

(11) Because the output frequency F.sub.O varies according to the first and second scaling numbers of the frequency divider 105 which are controlled by the processor 108, the processor 108 can easily deduce the gain K.sub.VCO after the voltage difference V.sub.D is received.

(12) In an embodiment of the invention, the processor 108 deduces the reciprocal of the gain 1/K.sub.VCO (by V.sub.D/ΔF.sub.O) which would be easily used for the design of compensation filters for the PLL circuit. Since the measured value (the voltage difference V.sub.D) is in the numerator and the denominator is a predetermined value (the frequency difference ΔF.sub.O; the multiplication by 1/ΔF.sub.O is also a predetermined value), no additional efforts due to division operations on the measured value are required, which simplifies the system design. In an embodiment of the invention, the voltage detector 106 is a differential analog-to-digital converter (ADC). A common differential ADC differs from a regular single-ended ADC in that a differential ADC measures the voltage difference between two pins (the plus and minus node) while a regular single-ended ADC measures the voltage difference between one pin and ground (i.e., the minus node is coupled to ground). Those skilled in the art may use well known ADC circuits for the differential ADC circuit.

(13) FIG. 2 is a block diagram of the conventional device for measuring the gain K.sub.VCO of the voltage-controlled oscillator. As shown in FIG. 2, the conventional device 200 includes the digital-to-analog converter (DAC) 201, the measured voltage-controlled oscillator (VCO) 202, and the frequency counter 203.

(14) The DAC 201 is configured to set the control voltage V.sub.C. The VCO 202 generates the output signal S.sub.O with the output frequency F.sub.O responding to the received control voltage V.sub.C. The frequency counter 203 measures the output frequency F.sub.O by comparing with the reference frequency F.sub.R. The gain K.sub.VCO can be obtained by a processor with eq. 1, where V.sub.1 and V.sub.2 are given values of the control voltage V.sub.C and F.sub.1 and F.sub.2 are the measured frequencies corresponding to V.sub.1 and V.sub.2, respectively.

(15) $\begin{array}{cc}{K}_{\mathrm{VCO}}=\frac{F_2-F_1}{V_2-V_1}& \left(\mathrm{eq}.1\right)\end{array}$

(16) Since the measured values (F.sub.1 and F.sub.2) will be in the denominator when calculating the reciprocal of the gain 1/K.sub.VCO, additional circuits for performing division operations on the measured values are required, which are more complicated than multiplication circuits and are thus detrimental to the design of compensation filters for the PLL circuit. In addition, since the gain measurement is not in situ, the VCO is separated from the PLL circuit during measurement and thus not only the accuracy is compromised but also additional time is required to further lock to the desired output frequency of the PLL after gain measurement. In an embodiment of the invention, for example, the output frequency F.sub.O of the VCO 202 is at 3.6 GHz and the nominal K.sub.VCO is around 20 MHz/V (that is determined while designing the VCO), and that the variation of the control voltage V.sub.C should be sufficiently small to keep the K.sub.vco linear. When the voltage difference of the control voltage V.sub.C is 0.1V, the frequency difference is only 2 MHz compared with the 3600 MHz carrier. To achieve a K.sub.VCO measurement error within 1%, the frequency difference must thus be measured with 0.02 MHz accuracy. To achieve 0.02 MHz accuracy, the frequency counter 203 needs the reference frequency F.sub.R to be 3.6 GHz and takes at least 50 us to measure the output frequency F.sub.O. The measurement process would be: tuning the output frequency F.sub.O corresponding to the control voltage V.sub.1 (10 us), measuring the first output frequency F.sub.1 (50 us), and measuring the second output frequency F.sub.2 (50 us). That is, it takes more than 110 us to measure the K.sub.VCO of the VCO 202 in the conventional method. When the VCO 202 is operated in a PLL circuit, the VCO 202 must be isolated to measure the K.sub.VCO and then further wait for the PLL circuit to reach steady state after the measurement, which takes extra time.

(17) In addition, when we want to precisely control the voltage value of the control voltage V.sub.C, the output voltage of the DAC 201 must have high resolution since the variation of the control voltage V.sub.C should be sufficiently small. It is obvious that, for a given resolution, measuring a voltage difference as in FIG. 1 can be much more accurate than providing a voltage value by a DAC as in FIG. 2, especially when the voltage difference is more or less predictable. Therefore, the embodiment of FIG. 1 has the following benefits: (1) if the measurement is done in situ in the PLL, the results are more accurate and stable; (2) The measurement process is embedded in the PLL circuit and the locking is already achieved right after the second sampling, and thus no additional time is required for locking the PLL circuit to a desired output frequency; (3) The voltage detector 106 (e.g., a differential ADC) directly measures the voltage difference of the control signal S.sub.C of the two locked states, which greatly reduces the dynamic-range requirement of the ADC; and (4) The output data is proportional to the reciprocal of the K.sub.VCO, which is in a more convenient format to obtain the reciprocal of the gain of the PLL circuit when designing compensation filters. Namely, with the device and the method provided by the embodiment of FIG. 1, K.sub.VCO can be measured in a more stable, accurate, and time-saving way.

(18) FIG. 3 is a flow chart of the embodiment in FIG. 1 of measuring the gain K.sub.VCO of the voltage-controlled oscillator in a phase-locked loop circuit. FIG. 3 herein is illustrated according to FIG. 1. In the beginning, the scaling number of the frequency divider 105 is adjusted so that the output signal S.sub.O of the PLL is locked to a desired output frequency F.sub.O plus a predetermined frequency difference ΔF.sub.O (Step S31). The first voltage V.sub.1 of the control signal S.sub.C is measured (Step S32). The scaling number of the frequency divider 105 is adjusted so that the output signal S.sub.O of the PLL is locked to a desired output frequency F.sub.O (Step S33). The second voltage V.sub.2 of the control signal S.sub.C is measured (Step S34). The reciprocal of the K.sub.VCO value is obtained by dividing the voltage difference V.sub.2−V.sub.1 by the predetermined frequency difference ΔF.sub.O (i.e., multiplying by 1/ΔF.sub.O which is also a predetermined value) (Step S35). In an embodiment of the invention, the voltage difference V.sub.2−V.sub.1 is measured by a differential analog-to-digital converter (ADC).

(19) While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.