System and method for accumulating and measuring a slowly varying electrical charge

Abstract

A system for measuring electrical charge, comprising a capacitance detector (110) connected to a charge integrator (120) being an operational amplifier with capacitance (Cf) feedback (130), wherein the input stage (121) of the charge integrator (120) comprises a pair of symmetrically connected complementary JFET transistors (T.sub.1, T.sub.2), the gates of which are connected to the input of the charge integrator (120), characterized in that an n-type transistor (T.sub.1) of the complementary pair of transistors (T.sub.1, T.sub.2) has its drain connected to a voltage regulating system (122).

Claims

1. A system for measuring electrical charge, the system comprising: a charge integrator comprising an operational amplifier and a feedback capacitance connected between an input and output of the operational amplifier, a capacitance detector connected to an input of the charge integrator, wherein an input stage of the charge integrator comprises a pair of symmetrically connected complementary JFET transistors, wherein gates of each transistor of the pair of the symmetrically connected complementary JFET transistors are connected to the input of the charge integrator, and a voltage controlling system connected to a drain of an n-type transistor of the pair of the symmetrically connected complementary JFET transistors for equalizing a gate current of a p-type transistor of the pair of the symmetrically connected complementary JFET transistors with a gate current of the n-type transistor of the pair of the symmetrically connected complementary JFET transistors, wherein the voltage controlling system is a system adapted to automatically set a drain voltage of the n-type transistor of the pair of the symmetrically connected complementary JFET transistors to a value for which a DC component of an output voltage of the charge integrator does not change.

2. The system according to claim 1, wherein the voltage controlling system is a manually-controlled potentiometer.

3. The system according to claim 1, wherein for a particular quiescent voltage, the gate current of the n-type transistor is lower than the gate current of the p-type transistor.

4. The system according to claim 1, wherein the drain of the n-type transistor is powered by a power source whose current is independent of a voltage potential of the drain of the n-type transistor.

5. The system according to claim 1, further comprising a regulated power source connected to a drain of the p-type transistor.

6. A method for measuring an electrical charge by means of a system comprising: a charge integrator comprising an operational amplifier and a feedback capacitance connected between an input and output of the operational amplifier, a switch for short-circuiting the feedback capacitance, a capacitance detector connected to an input of the charge integrator, wherein an input stage of the charge integrator comprises a pair of symmetrically connected complementary JFET transistors, wherein gates of each transistor of the pair of the symmetrically connected complementary JFET transistors are connected to the input of the charge integrator, and a voltage controlling system connected to a drain of an n-type transistor of the pair of the symmetrically connected complementary JFET transistors, a regulated power source connected to a drain of the p-type transistor of the pair of the symmetrically connected complementary JFET transistors, the method comprising equalizing, by means of the voltage controlling system, a gate current of the p-type transistor of the pair of the symmetrically connected complementary JFET transistors with a gate current of the n-type transistor of the pair of the symmetrically connected complementary JFET transistors and setting the regulated power source so as to set a zero output voltage of the charge integrator when the switch is closed.

Description

BRIEF DESCRIPTION OF FIGURES

(1) The present invention is shown by means of exemplary embodiments on a drawing, in which:

(2) FIG. 1 shows a known system for measuring an electrical charge using a charge integrator;

(3) FIG. 2 shows a semiconductor detector known in the art;

(4) FIG. 3 shows a charge integrator known in the art;

(5) FIG. 4 shows an exemplary embodiment of the charge integrator according to the invention;

(6) FIG. 5 shows an avalanche effect;

(7) FIG. 6 shows a change in the potential of point P.sub.2 in the charge integrator;

(8) FIG. 7 shows a regulated current source.

DETAILED DESCRIPTION OF EMBODIMENTS

(9) FIG. 4 shows an exemplary embodiment of the charge integrator to be used as an element of the system for measuring electrical charge according to the present invention. The input stage 121 of the charge integrator 120 comprises a pair of symmetrically connected JFET transistors T.sub.1, T.sub.2, whose gates are connected to the input of the charge integrator. The structure of the input of the system, which is symmetrical due to the type of transistors used (pnp, npn), forces the symmetrical operation of the system and of the supply voltages, which define the operating point of the system. The transistor T.sub.1, together with the transistor T.sub.3 are powered from the current source I.sub.01, which is independent of the potential at point P.sub.1. The value of voltage at point P.sub.1 is a result of supplying the base of the transistor T.sub.3 by constant voltages (the emitter voltage is higher than this voltage approximately by a constant value of the base-emitter junction voltage) and can be changed in this way (i.e. selected so as to properly influence the gate current of the transistor T.sub.1, as will be discussed further in the description).

(10) Suppose that in case of a charge impulse, the current flowing through the transistor T.sub.1 decreases (and at the same time the current flowing through the transistor T.sub.2 increases). Because transistors T.sub.1 and T.sub.3 are powered by a common power source I.sub.01, a drop in the current flowing through the transistor T.sub.1 causes an identical (in amplitude) increase in the current flowing through the transistor T.sub.3. The transistor T.sub.3 may be treated as forming a common base amplifier. The transistor T.sub.4 constitutes both a load for the transistor T.sub.3, as well as it by itself constitutes symmetrically a part of the common-base amplifier OB, for which transistor T.sub.3 constitutes an active load. The principle of generation of the output impulse in the system is shown in FIG. 6, which shows a change in the potential of point P2 as a result of the intersection of the collector characteristics of transistors T.sub.3 and T.sub.4, wherein V.sub.EE is the voltage between the emitters of transistors T.sub.3 and T.sub.4.

(11) The source I.sub.01 constitutes a source generating a constant current, independent of the potential on the drain of transistor T.sub.1. This allows for changing the potential of the base of transistor T.sub.3 without changing the current flowing through this transistor. Transistor T.sub.1 can also be treated as a constant current source. Such configuration allows for operating with different voltages on the T.sub.1 transistor drain. In turn, the change of the potential in the drain of transistor T.sub.1 allows for controlling the gate current of transistor T.sub.1 as a result of the avalanche effect, which is shown in FIG. 5, showing a graph of the dependence of the gate current of the JFET transistor on the source-drain voltage.

(12) The input of the charge integrator is therefore constituted by two junctions of the JFET transistors. It can be thus assumed that they constitute two diodes connected in an anti-parallel manner, implementing a system protecting from the occurrence of excessive voltage impulse.

(13) Even though the system shown in FIGS. 3 and 4 has symmetry due to the type of the semiconductors used, some differences can appear, especially for the JFET transistors. In these transistors the gate current depends on the voltage on the drain (see. E.g. Paul Horowitz, Winfield Hill “The art of electronics”). Increasing this voltage, above a certain level, causes significant increase of the gate current as a result of the occurrence of the avalanche effect (FIG. 5). This effect will be much stronger for n-channel transistors. Because of this, in the system according to the invention, this type of transistor (transistor T.sub.1) is treated as an element with regulated (adjustable) gate current. In the system according to the invention, the type of the p-channel transistor T.sub.2 is selected and the voltage on its drain is set using a voltage divider formed by resistors R.sub.6, R.sub.8, so that this selection and this setting would allow the current of its gate to be balanced by the current gate selected in transistor T.sub.1 using the system 122 giving the voltage on its drain. As the effect of balancing of these currents, high input resistance of the system is achieved, as well as virtually lack of the charging current of the capacitance C.sub.f from the side of the gate currents of JFET transistors.

(14) For example, an n-channel transistor T.sub.1 is selected so as that its gate current is slightly smaller than the gate current of the p-channel transistor T.sub.2 for certain quiescent voltage. This gives a possibility to equalize the gate currents as a result of increasing the gate current of transistor T.sub.1. Such regulation is possible by regulating the voltage on the drain of the transistor T.sub.1 and causing in this way the avalanche effect on the junction of its gate.

(15) The system 122 setting the voltage can be in form of a manually controlled potentiometer. The potentiometer is set to a value that will cause the output voltage (observed e.g. using a meter) to remain unchanged in a predetermined time.

(16) Alternatively, the system 122 setting the voltage can be an automatic system, adapted to regulate the voltage of the drain of transistor T.sub.1 so that the constant component of the output voltage does not change.

(17) The system comprises also a regulated power source I.sub.02. The current of this source is selected so that during closing of a key K1 connected in parallel to the capacitance C.sub.r of the feedback, formed for example on the basis of miniature reed switch, the output voltage equal to zero is achieved. After selecting and storing this current in a suitable electronic circuit and opening this key K1, the system is ready to measure the induced charge.

(18) FIG. 7 shows an exemplary embodiment of the regulated power source I.sub.02. This source is constituted by a resistor R2 connected between the point P3 (constant potential) and the output of the operational amplifier. In this example, the amplifier with a high input resistance has been used. On the input of this amplifier, which functions as a voltage follower, there is a capacitance of several microfarads. After opening a key K2 (which can be a reed switch), the follower remembers (for even a couple of hours) the voltage on the capacitor C.sub.M and the constant flow of the current to point P.sub.3 is provided. The voltage on the capacitor C.sub.M is set with time constant of order of milliseconds (closed key K.sub.2) by the feedback circuit, implemented on the following operational amplifier. In this system, in the feedback loop (for closed keys K.sub.1, K.sub.2), the zero value of the output voltage is enforced by setting appropriate voltage on the capacitor C.sub.M. After this operation (lasting a couple of milliseconds), the system is ready for measurement, during which keys K.sub.1 and K.sub.2 are opened. The value of the accumulated charge is then measured as the voltage on the capacitor C.sub.f (the output of the integrator).

(19) Due to the compensation of quiescent currents of the integrator, the input resistance of the system tends towards infinity, and consequentially the system according to the invention can be used for measuring a very slowly induced charge.

(20) Due to the fact that the input of the system is protected from breakdowns and occurrence of relatively big charge signals, the system can be used widely in scientific, medical and also industrial research.

(21) The system according to the invention can be used in standard situations, as well as in situations in which the charge is accumulated relatively slowly, for example in the process of its induction lasting even for a couple of seconds or a couple of tens of seconds. In the systems known in the prior art, especially in the system disclosed in WO2012114291, a feedback compensating gate currents of FET transistors is not used. In case of using resistance feedback—taking into account time constants for 1 pF capacitance of the feedback, and the resistance of the feedback of 10.sup.9—a maximal time constant of the capacitor discharge of 10.sup.−3 second is achieved. In the solution according to the present invention, due to appropriate currents compensation, the time constant of the capacitor's discharge is much higher, easily reaching said value of a few tens to a few hundreds of seconds.