Method of reading an electronic memory device including a plurality of memory cells of resistive random access memory type

Abstract

A method for reading an electronic memory device including N memory cells Ci with 1≧i≧N and N≧2, each cell Ci having a resistance Ri, the method including for each cell Ci, determining a set Ei of resistance values capable of being associated with the resistance Ri of the cell Ci; for each combination of N variables Vi, each variable Vi taking successively each resistance value among the predetermined set Ei, applying a mathematical function to the combination to obtain a resulting resistance value; for each combination of N variables Vi, associating a logic state of the electronic memory device with the resulting resistance value obtained previously, according to a comparison of the resulting resistance value with a same threshold resistance value; associating a resistance value with each resistance Ri to obtain a particular combination of N variables Vi; determining the logic state of the electronic memory device.

Claims

1. A method for reading an electronic memory device comprising a plurality N of memory cells of resistive random access memory type Ci with i varying from 1 to N and N≧2, each memory cell Ci having a resistance Ri, the method Comprising in order the following steps: for each memory cell Ci, determining a set Ei of resistance values capable of being associated with the resistance Ri of the memory cell Ci; for each combination of N variables Vi, each variable Vi taking successively each resistance value among the predetermined set Ei, applying a mathematical function to said combination of N variables Vi to obtain a resulting resistance value; for each combination of N variables Vi, associating a logic state of the electronic memory device with the resulting resistance value obtained previously, according to a comparison of the resulting resistance value with a same threshold resistance value; associating a resistance value with each resistance Ri to obtain a particular combination of N variables Vi, and determining the logic state of the electronic memory device, the logic state being associated with the resulting resistance value corresponding to the particular combination.

2. The reading method according to claim 1, wherein the mathematical function applied is the geometric mean function.

3. The reading method according to claim 1, wherein each memory cell Ci of the plurality N of memory cells is an oxide based resistive random access memory.

4. The reading method according to claim 1, wherein each memory cell Ci of the plurality N of memory cells is a conductive bridge resistive random access memory.

5. The reading method according to claim 1, wherein each resistance value is associated with a binary code, and wherein each resulting resistance value is associated with a resulting binary code.

6. The reading method according to claim 1, wherein associating a resistance value with each resistance Ri is carried out using at least one comparator.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) The figures are presented for indicative purposes and in no way limit the invention.

(2) FIG. 1 shows schematically an electronic memory device comprising a plurality of memory cells of resistive random access memory type.

(3) FIG. 2 shows a diagram of the steps of a method for reading an electronic memory device according to a first embodiment of the invention.

(4) FIG. 3 shows schematically an example of carrying out the method for reading an electronic memory device according to the first embodiment of the invention.

(5) FIG. 4 shows schematically an example of carrying out a step of associating a resistance value with a resistance of a memory cell of resistive random access memory type, according to an embodiment of the invention.

(6) FIG. 5 shows a diagram of the steps of a method for reading an electronic memory device according to a second embodiment of the invention.

(7) FIG. 6a shows a first table, for carrying out a step of applying a mathematical function, according to the second embodiment of the invention.

(8) FIG. 6b shows a second table grouping together the resulting resistance values obtained by the application of a first mathematical function, according to the second embodiment of the invention.

(9) FIG. 6b′ shows a second table grouping together the resulting resistance values obtained by the application of a second mathematical function, according to the second embodiment of the invention.

(10) FIG. 6c shows a third table grouping together the logic states associated with the resulting resistance values of FIG. 6b, according to the second embodiment of the invention.

(11) FIG. 6c′ shows a third table grouping together the logic states associated with the resulting resistance values of FIG. 6b′, according to the second embodiment of the invention.

(12) FIG. 7 shows schematically: a first distribution of the resistance values obtained for a same resistance state of an electronic memory device, in accordance with a reading method of the prior art; a second distribution of the resistance values obtained for a same resistance state of an electronic memory device, in accordance with a reading method according to an embodiment of the invention; a third distribution of the resistance values obtained for a same resistance state of an electronic memory device, in accordance with a reading method according to an embodiment of the invention.

DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT OF THE INVENTION

(13) Unless stated otherwise, a same element appearing in the different figures has a single reference.

(14) FIG. 1 shows schematically an electronic memory device 1 comprising a plurality of memory cells of resistive random access memory type Ci, with i varying from 1 to N, N being a natural number greater than or equal to 2. Each memory cell Ci has a resistance Ri.

(15) The particular example of FIG. 1 corresponds to the case where N=2 and the electronic memory device 1 thus comprises: a first memory cell C1 of resistive random access memory type, the first memory cell C1 having a first resistance R1, and a second memory cell C2 of resistive random access memory type, the second memory cell C2 having a second resistance R2.

(16) The field of the present invention more particularly relates to two categories of resistive memories: oxide based resistive random access memories OxRRAM, comprising an active zone based on an oxide based active material, and conductive bridge resistive random access memories CBRAM, comprising an active zone based on an ionic conduction material, the active zone forming a solid ionic conduction electrolyte arranged between an electrode forming an inert cathode and an electrode forming a soluble anode.

(17) Thus, each memory cell Ci of the plurality N of memory cells of the electronic memory device 1 is advantageously an oxide based resistive random access memory OxRRAM, or alternatively a conductive bridge resistive random access memory CBRAM.

(18) FIG. 2 shows a diagram of the steps of a method 100 for reading an electronic memory device according to a first embodiment of the invention. FIG. 2 thus shows: a step 110 according to which a resistance value is associated with each resistance Ri of each memory cell Ci of the electronic memory device 1, to obtain a particular combination of N resistance values. Each resistance value may advantageously be represented by a binary code. At the end of step 110 described previously, a step 120 according to which a mathematical function is applied to the particular combination of N resistance values, to obtain a resulting resistance value. The resulting resistance value may advantageously be represented by a resulting binary code. At the end of step 120 described previously, a step 130 according to which the logic state of the electronic memory device 1 is determined.

(19) FIG. 3 shows schematically an example of carrying out the method 100 for reading an electronic memory device according to the first embodiment of the invention.

(20) The first memory cell C1 of the electronic memory device 1 is read in order to associate a first resistance value V1 with the first resistance R1 of the first memory cell C1. Similarly, the second memory cell C2 of the electronic memory device 1 is read in order to associate a second resistance value V2 with the second resistance R2 of the second memory cell C2.

(21) A method and a device for reading a memory cell of an electronic memory device are described hereafter, in relation with FIG. 4.

(22) A mathematical function, referenced “F” in FIG. 3, is then applied to the first resistance value V1 and to the second resistance value V2. The result of the application of the mathematical function F to the first and second resistance values V1 and V2 is a resulting resistance value, referenced “Res” in FIG. 3:
F(V1,V2)=Res

(23) The resulting resistance value Res is then compared, for example by means of a comparator referenced “Com1” in FIG. 3, with a threshold resistance value, referenced “Ref” in FIG. 3. The threshold resistance value Ref is typically predefined. The logic state of the electronic memory device 1 is then determined according to the result of the comparison of the resulting resistance value Res with the threshold resistance value Ref. The logic state of the electronic memory device 1 is referenced “LS” in FIG. 3. For example: if Res>Ref, the electronic memory device 1 is in the OFF state, if Res≦Ref, the electronic memory device 1 is in the ON state.

(24) The mathematical function F is advantageously a geometric mean function. The mathematical function F applied to a particular combination of N resistance values is expressed thus:
F(V.sub.1,V.sub.2, . . . ,V.sub.N)=(V.sub.1×V.sub.2× . . . ×V.sub.N).sup.1/N

(25) The mathematical function F may alternatively be an arithmetic mean function. The mathematical function F applied to a particular combination of N resistance values is then expressed:

(26) $F\left(V_1,V_2,\mathrm{.Math.},V_N\right)=\frac{\left(V_1+V_2+\mathrm{.Math.}+V_N\right)}{N}$

(27) By using a mathematical function such as a geometric or arithmetic mean, the resulting distribution of the resistance values obtained is reduced for a same resistance state. In order to be able to distinguish correctly the two resistance states ON and OFF, it remains necessary that the distribution obtained for the resistance state ON is distinct and separate from the distribution obtained for the resistance state OFF.

(28) In the particular case where the electronic memory device 1 only comprises the first memory cell C1 and the second memory cell C2, and where the first and second memory cells C1 and C2 are programmed in a complementary manner, the mathematical function F may advantageously be a subtraction function. “Complementary programming” is taken to mean the fact that if the first memory cell C1 is in the OFF state then the second memory cell C2 is in the ON state, and conversely that if the first memory cell C1 is in the ON state then the second memory cell C2 is in the OFF state. The mathematical function F applied to a particular combination of two resistance values is then expressed:
F(V.sub.1,V.sub.2)=V.sub.1−V.sub.2

(29) When the first and second memory cells C1 and C2 are programmed in a complementary manner and when the mathematical function F is a subtraction function, it is no longer necessary that the distribution obtained for the resistance state ON is distinct and separate from the distribution obtained for the resistance state OFF: it suffices in fact that the first and second memory cells C1 and C2 have distinct resistance values.

(30) FIG. 4 shows schematically an example of carrying out of the step 110 of associating a resistance value with a resistance of a memory cell of resistive random access memory type, according to an embodiment of the invention. A comparator Com2 compares the first resistance R1 of the first memory cell C1 with several predefined resistances, of known value. In the particular example represented in FIG. 4, the comparator Com2 compares the first resistance R1 with three predefined resistances: a first predefined resistance of value 1 kΩ, a second predefined resistance of value 10 kΩ, and a third predefined resistance of value 100 kΩ.

(31) The comparator Com2 may naturally comprise only two predefined resistances, or more than three predefined resistances. The values of the predefined resistances may naturally be chosen differently with respect to the particular example cited.

(32) The comparator Com2 associates with the first resistance R1 a first value V1, which is the predefined resistance value the closest to the real value of the first resistance R1. In the particular example represented in FIG. 4, if the first resistance R1 has a real resistance of 6 kΩ or 12 kΩ, the comparator Com2 associates with it the first value V1=10 kΩ, that is to say the value of the second predefined resistance. If the first resistance R1 has a real resistance of 55 kΩ, 78 kΩ or 110 kΩ, the comparator Com2 associates with it the first value V1=100 kΩ, that is to say the value of the third predefined resistance.

(33) The comparator Com2 may also be used to associate with the second resistance R2 of the second memory cell C2 a second value V2. Alternatively, another comparator than the comparator Com2 may be used to associate with the second resistance R2 of the second memory cell C2 a second value V2. This other comparator may comprise the same number of predefined resistances as the comparator Com2, or a different number of predefined resistances compared to the comparator Com2. If this other comparator comprises the same number of predefined resistances as the comparator Com2, the values of the predefined resistances of the other comparator may be identical to the values of the predefined resistances of the comparator Com2, or different to the predefined resistance values of the comparator Com2.

(34) FIG. 5 shows a diagram of the steps of a method 200 for reading an electronic memory device according to a second embodiment of the invention. FIG. 5 shows a step 210 according to which, for each resistance Ri of each memory cell Ci, a set Ei of resistance values capable of being associated with said resistance Ri is determined. In the particular example of the electronic memory device 1: a first set E1 of distinct resistance values capable of being associated with the first resistance R1 of the first memory cell C1 is determined, and a second set E2 of distinct resistance values capable of being associated with the second resistance R2 of the second memory cell C2 is determined.

(35) The first set E1 comprises for example three resistance values capable of being associated with the first resistance R1: a first value v1, a second value v2 distinct from the first value v1 and a third value v3 distinct from the first and second values v1 and v2. The second set E2 is for example identical to the first set E1. Alternatively, the second set E2 may comprise a different number of resistance values and/or different resistance values compared to the first set E1.

(36) At the end of step 210, the step 120 of applying a mathematical function to a particular combination of N resistance values, described previously, is carried out for each combination of N variables Vi, each variable Vi taking successively each resistance value among the predetermined set Ei.

(37) In the particular example of the electronic memory device 1: the first set E1 comprising the first, second and third resistance values v1, v2 and v3 has been determined for the first resistance R1 of the first memory cell C1, and the second set E2, identical to the first set E1, has been determined for the second resistance R2 of the second memory cell C2.

(38) The mathematical function F is thus applied to the nine combinations of two variables (V1, V2), where the first value V1 of the first resistance R1 takes successively the values v1, v2 and v3 of the first set E1, and where the second value V2 of the second resistance R2 takes successively the values v1, v2 and v3 of the second set E2.

(39) A first table T1, represented in FIG. 6a, shows the application of the mathematical function F to said nine combinations.

(40) A second table T2, represented in FIG. 6b, shows the result of the application of the mathematical function F to said nine combinations, in the particular case where: the first resistance value v1 is equal to 1 kΩ, the second resistance value v2 is equal to 10 kΩ and the third resistance value v3 is equal to 100 kΩ; the mathematical function F is the geometric mean function.

(41) The second table T2 thus groups together the nine resulting resistance values obtained by the application of the mathematical geometric mean function F to said nine combinations. The nine resulting resistance values in the second table T2 are rounded off by truncation to kΩ.

(42) A table T2′ according to another example, represented in FIG. 6b′, shows the result of the application of the mathematical function F to said nine combinations, in the particular case where: the first resistance value v1 is equal to 1 kΩ, the second resistance value v2 is equal to 10 kΩ and the third resistance value v3 is equal to kΩ; the mathematical function F is the subtraction function.

(43) The alternative table T2′ according to this other example thus groups together the resulting nine resistance values obtained by the application of the mathematical subtraction function F to said nine combinations.

(44) At the end of step 120, a step 220 is carried out according to which a logic state of the electronic memory device is associated with each resulting resistance value obtained previously, according to a comparison of each resulting resistance value with a threshold resistance value.

(45) A third table T3, represented in FIG. 6c, shows an example of result of the association of a logic state of the electronic memory device 1 with each of the nine resulting resistance values of the second table T2, in the particular case where: the threshold resistance value is equal to 10 kΩ, the electronic memory device 1 is in the OFF state, or “0”, when its resulting resistance value is greater than or equal to the threshold resistance value, that is to say 10 kΩ, the electronic memory device 1 is in the ON state, or “1”, when its resulting resistance value is less than the threshold resistance value, that is to say 10 kΩ.

(46) A table T3′ according to another example, represented in FIG. 6c′, shows the result of the association of a logic state of the electronic memory device 1 with each of the resulting nine resistance values of table T2′, in the particular case where: the threshold resistance value is equal to 0 kΩ, the electronic memory device 1 is in the OFF state, or “0”, when its resulting resistance value is greater than or equal to the threshold resistance value, that is to say 0 kΩ, the electronic memory device 1 is in the ON state, or “1”, when its resulting resistance value is less than the threshold resistance value, that is to say 0 kΩ.

(47) In the particular examples of tables T3 and T3′, a binary code is associated with each resistance value of the first set E1 and of the second set E2: the binary code “00” is associated with the first resistance value v1, the binary code “01” is associated with the second resistance value v2, and the binary code “10” is associated with the third resistance value v3.

(48) At the end of step 220, the step 110 of associating a resistance value with each resistance Ri, described previously, is carried out. The example of carrying out step 110, described previously in relation with FIG. 4, may be used.

(49) The result of step 110 may for example be the following, in the case of the electronic memory device 1: the first resistance R1 has a first value V1=10 kΩ, the second resistance R2 has a second value V2=100 kΩ.

(50) At the end of step 110, the step 130 of determining the logic state of the electronic memory device is carried out. According to the second embodiment, the logic state is predetermined by the value of the resulting resistance. The value of the resulting resistance has been calculated previously during step 120, and a logic state has been associated previously with this resulting resistance value during step 220.

(51) In the particular example where the mathematical function is the geometric mean function, for the first value V1=10 kΩ and the second value V2=100 kΩ, the value of the resulting resistance is equal to 31 kΩ. The state associated with this resulting resistance value is the OFF state.

(52) In the other particular example where the mathematical function is the subtraction function, for the first value V1=10 kΩ and the second value V2=100 kΩ, the resulting resistance value is equal to −90 kΩ. The state associated with this resulting resistance value is the ON state.

(53) FIG. 7 shows: a first distribution d1 of the resistance values obtained for a same resistance state of an electronic memory device, in accordance with a reading method of the prior art; a second distribution d2 of the resistance values obtained for a same resistance state of an electronic memory device, in accordance with a reading method 100 or 200 according to an embodiment of the invention; a third distribution d3 of the resistance values obtained for a same resistance state of an electronic memory device, in accordance with a reading method 100 or 200 according to an embodiment of the invention.

(54) The first, second and third distributions d1, d2 and d3 have been measured for around 10,000 resistance states. The second distribution d2 is obtained for an electronic memory device comprising two electronic memory cells. The third distribution d3 is obtained for an electronic memory device comprising three electronic memory cells. FIG. 7 shows that the second and third distributions d2 and d3 have a dispersion narrower than the first distribution d1.