OLED display panel
09786721 ยท 2017-10-10
Assignee
Inventors
Cpc classification
H10K50/8445
ELECTRICITY
H10K59/38
ELECTRICITY
H10K59/123
ELECTRICITY
H10K50/865
ELECTRICITY
International classification
Abstract
The utility model provides an OLED display panel, by disposing a color filter layer on an array substrate, an alignment process of an upper with a lower substrate can be omitted, the manufacturing process of the OLED display panel can be simplified, and a thin film packaging can be carried out on the color filter layer so that the OLED display panel can become more lightweight and thin.
Claims
1. An OLED display panel comprising an array substrate and a color filter layer, the color filter layer being disposed on the array substrate, wherein the array substrate comprises a cathode layer disposed on the top of the array substrate, the color filter layer is disposed on the cathode layer, a surface of the color filter layer away from the cathode layer is disposed with a second thin film layer thereon, a first thin film layer is disposed between the cathode layer and the color filter layer, and the first thin film layer and the second thin film layer each are a plurality of organic and inorganic layers being alternately stacked.
2. The OLED display panel according to claim 1, wherein the organic layer comprises a single layer or a stacked layer formed by polyethylene terephthalate, polyimide, polycarbonate, an epoxy resin, polyethylene, and/or polyacrylate; the inorganic layer comprises a single layer or a stacked layer formed by a metal oxide(s) or a metal nitride(s).
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) The above and other aspects, features and advantages of embodiments of the utility model will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
(2)
(3)
(4)
(5)
(6)
DETAILED DESCRIPTION OF EMBODIMENTS
(7) In the following, various embodiments of the utility model will be described in detail with reference to accompanying drawings. The utility model may be embodied in many different forms and should not be construed as limiting to the embodiments set forth herein. Rather, these embodiments are provided to explain the principles of the utility model and its practical applications, so that other skilled in the art can understand various embodiments of the utility model and various modifications suitable for specific intended applications.
(8) Please refer to
(9) In the illustrated embodiment, the array substrate 110 is a conventional top-gate type TFT (thin film transistor) array substrate and includes: a base substrate 101, a buffer layer 102 disposed on the base substrate 101 and a plurality of TFTs 103 disposed on the buffer layer 102. Herein, the TFTs 103 refer to a thin film transistor active matrix. The TFTs 103 each include a semiconductor layer 104 disposed on the buffer layer 102, a gate insulating layer 105 disposed on the buffer layer 102 and covering the semiconductor layer 104, a gate electrode 107 disposed on the gate insulating layer 105, and a source electrode 108 and a drain electrode 109 respectively disposed on two sides of the semiconductor layer 104.
(10) In other embodiment, the TFTs 103 each may be a conventional thin film transistor with bottom-gate structure instead and thus will not be repeated herein.
(11) In addition, the array substrate 110 further includes a planarization layer 111, an anode layer 113, a light-emitting layer 114, a pixel defining layer 115 and the cathode layer 116 all disposed on the plurality of TFTs 103. An interlayer insulating layer 106 is disposed between the planarization layer 111 and the gate insulating layer 105. The interlayer insulating layer 106 is disposed covering a gate electrode 107 and on the gate insulating layer 105. The planarization layer 111 is disposed on the interlayer insulating layer 106 and covering the source electrode 108 as well as the drain electrode 109. A plurality of via holes are formed/disposed on the planarization layer 111. The anode layer 113 is discontinuously disposed on (e.g., penetrating through) the planarization layer 111, and the anode layer 113 is electrically connected to the drain electrode 109 of each TFT 103 by a corresponding one of the via holes 112 disposed on the planarization layer 111. In some embodiment, the anode layer 113 is a reflective film formed by one or more than one of gold (Au), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), titanium (Ti) and their compounds. In other embodiment, the anode layer 113 may include at least one transparent film formed by a compound with high work function such as ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped zinc oxide) or ZnO (zinc oxide). The array substrate 110 is disposed with the plurality of TFTs 103, the planarization layer 111 is disposed with the plurality of via holes 112, and the anode layer 113 is electrically connected to the TFTs 103 by respective via holes 112.
(12) The light-emitting layer 114 correspondingly is disposed above the anode layer 113. The pixel defining layer 115 and the light-emitting layer 114 are disposed adjacent to and alternate with each other. In some embodiment, the cathode layer 116 is formed on the light-emitting layer 114 and the pixel defining layer 115. The cathode layer 116 contains a transparent metal, and the transparent metal may be constituted by a metal mixture with low work function of Mg (magnesium) and Ag (silver), LiF (lithium fluoride) and Al (aluminum), or Li (lithium) and Al (aluminum), or constituted by metals such as Li (lithium), Ca (calcium), Ag (silver) and Al (aluminum).
(13) The color filter layer 120 is disposed on the cathode layer 160. The color filter layer 120 includes an R photoresist (red photoresist) 121, a G photoresist (green photoresist) 122 and a B photoresist (blue photoresist) 123 disposed adjacent to one after another. The R photoresist 121, the G photoresist 122 and the B photoresist 123 are disposed corresponding to respective discrete portions of the light-emitting layer 114. Preferably, a thickness of the color filter layer 120 is greater than or equal to a thickness of the pixel defining layer 115. In addition, in other embodiment, in order to increase the brightness of the OLED display panel 100, the color filter layer 120 may further include a white light transmissive region (not shown in the drawings).
(14) The OLED display panel 100 further includes a second thin film layer 130 disposed on a surface of the color filter layer 120 away from the cathode layer 116. The second thin film layer 130 is used for encapsulating/packaging the OLED display panel 100, so as to avoid the OLED display panel 110 to be affected by external environment and relieve performance degradation of the OLED display panel caused by moisture and oxygen.
(15) Sum up, the illustrated embodiment disposes the color filter layer 120 on the cathode layer 116 of the array substrate 110, which can omit/avoid an alignment process of an upper substrate with a lower substrate, simplify the manufacturing process of the OLED display panel 100, and realize a thin film encapsulation/packaging on the color filter layer 120 to thereby make the OLED display panel 100 be more lightweight and thin.
(16) Referring to
(17) As shown in
(18) In addition, a buffer layer (not shown in the drawing) may be disposed between the cathode layer 116 and the color filter layer 120. A material of the buffer layer includes but is not limited to any one of TiO.sub.2 (titanium dioxide), SiN.sub.x (silicon nitride) and SiO.sub.x (silicon oxide) or a combination thereof. By setting the buffer layer, the first thin film layer 140 is not easy to be damage during a process of forming the color filter layer 120.
(19) Please further refer to
(20) Please further refer to
(21) The OLED display panel of any one of the above embodiments may be applied to mobile phones, tablet PCs, televisions, monitors, navigators and other display devices with displaying function.
(22) In summary, as to the OLED display panel of the utility model, by disposing the color filter layer on the array substrate, the OLED display panel can omit/avoid an alignment process of upper and lower substrates, a manufacturing process thereof can be simplified, and a thin film encapsulation/packaging can be performed on the color filter layer so that the OLED display panel can become more lightweight and thin.
(23) While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.