One-way packet delay measurement

Abstract

A method for measuring one-way delays in a communications network, the method comprising: maintaining a virtual clock state comprising information for converting times measured with respect to remote clocks into times as would be measured with respect to a local reference clock; registering, for each packet of the plurality of packets in a communications session between the first and second nodes, a timeset comprising transmission and reception times at the first and second nodes; converting, responsive to the virtual clock, times in the timeset measured with respect to the first node clock or the second node clock, into times as would be measured with respect to the reference clock; calculating, for each packet of the series of packets, a forward one-way delay (FOWD) from the first node to the second node and a reverse one-way delay (ROWD) from the second node to the first node, responsive to the converted timeset.

Claims

1. A method for measuring one-way delays in a communications network, the method comprising: transmitting a plurality of packets comprised in a communications session from a first node associated with a first node clock to a second node associated with a second node clock and receiving the plurality of packets after the packets are reflected from the second node back to the first node; maintaining a virtual clock state comprising information for converting times measured with respect to the first and/or second node clock into times as would be measured with respect to a reference clock; registering, for each packet of the plurality of packets in the communications session, a timeset comprising transmission and reception times at the first and second nodes that are measured with respect to the first and second node clocks, respectively; converting, responsive to the virtual clock, times in the timeset measured with respect to the first node clock or the second node clock, into times as would be measured with respect to the reference clock; calculating, for each packet of the series of packets, a forward one-way delay (FOWD) from the first node to the second node and a reverse one-way delay (ROWD) from the second node to the first node, responsive to the converted timeset; testing the FOWD and ROWD of each packet of the series of packets against a gating criterion; updating estimates of forward floor delay (FFD) and reverse floor delay (RFD) responsive to FOWDs and/or ROWDs that pass the gating criterion; and updating the virtual clock state responsive to the updated estimate of FFD and/or RFD.

2. The method according to claim 1, comprising recalculating the FOWD and the ROWD of the packets responsive to the updated virtual clock state.

3. The method according to claim 1, wherein the reference clock is the first node clock or the second node clock.

4. The method according to claim 1, the updating of the virtual clock state is further responsive to FOWD and ROWD of packets that did not pass the gating criterion.

5. The method according to claim 1, further comprising computing at least one one-way delay statistic for the FOWD and/or the ROWD, the at least one one-way delay statistic being selected from the group consisting of: a minimum, a maximum, a standard deviation, a skew, a kurtosis, and a percentile histogram.

6. The method according to claim 1, wherein the communications session is a conventional DM session and the second node is a standard reflector node conventionally used to determine round-trip time.

7. The method according to claim 1, wherein the communications session is a single communications session.

8. An apparatus for measuring one-way delays in a communications network, the apparatus comprising: a local clock; a memory, at least one virtual clock emulating a node clock located in a remote node; a delay analysis engine operable to: register, for each packet of a plurality of packets comprised in a communications session between a first node collocated with a first node clock and a second node collocated with a second node clock, a timeset comprising transmission and reception times at the first and second nodes that are measured with respect to the first and second node clocks, respectively; convert the times comprised in the timeset to be in accordance with a reference clock responsive to the at least one virtual clock; and calculate for each packet of the plurality of packets, a forward one-way delay (FOWD) from the first node to the second node and a reverse one-way delay (ROWD) from the second node to the first node, responsive to the converted timeset responsive to the converted timeset; and determine an estimated forward floor delay (FFD) and an estimated reverse floor delay (RFD) responsive to the FOWD and the ROWD, respectively.

9. The apparatus according to claim 8, wherein the delay analysis engine is further operable to update a state of the at least one virtual clock responsive to the estimated FFD and/or the RFD.

10. The apparatus according to claim 8, further comprising a packet source operable to generate and transmit the plurality of packets.

11. The apparatus according to claim 8, wherein the reference clock is the first node clock or the second node clock.

12. The apparatus according to claim 8, wherein the communications session is a conventional DM session and the second node is a standard reflector node conventionally used to determine round-trip time.

13. The apparatus according to claim 8, wherein the communications session is a single communications session.

Description

BRIEF DESCRIPTION OF FIGURES

(1) Non-limiting examples of embodiments of the disclosure are described below with reference to figures attached hereto that are listed following this paragraph. Identical features that appear in more than one figure are generally labeled with a same label in all the figures in which they appear. A label labeling an icon representing a given feature of an embodiment of the disclosure in a figure may be used to reference the given feature. Dimensions of features shown in the figures are chosen for convenience and clarity of presentation and are not necessarily shown to scale.

(2) FIG. 1 shows a schematic illustration of DM packet exchange through a communications network between a source node comprising a RADM apparatus in accordance with an embodiment of the disclosure and a reflector node;

(3) FIG. 2 shows a flowchart showing an NDM method in accordance of an embodiment of the disclosure wherein the virtual clock is collocated with the source node;

(4) FIG. 3 shows a schematic illustration of DM packet exchange through a communications network between a source node and a reflector node, in accordance with an embodiment of the disclosure wherein virtual clocks are collocated with a reference node; and

(5) FIG. 4 shows a flowchart showing a method in accordance with an embodiment of the disclosure wherein virtual clocks are collocated with a reference node.

DETAILED DESCRIPTION

(6) Reference is made to FIG. 1, which schematically illustrates a packet switched network (PSN) 100 in which an RADM apparatus 200 optionally located in, or connected to, a source node 120, and RADM apparatus 200 is shown engaging in a DM session with reflector node 130. Note that reflector node 130 may be a standard reflector node conventionally used to determine round-trip time RTT and need not know that it is participating in a one-way delay measurement. For this reason RADM apparatus 200 may be considered to be reflector agnostic.

(7) Reference is also made to FIG. 2, which shows a flowchart showing an NDM method 300 in accordance of an embodiment of the disclosure, which may be performed by RADM apparatus 200 during and/or following a DM session.

(8) As shown in FIG. 1, RADM 200 in accordance with an embodiment of the disclosure comprises a memory 206, virtual clock 210, and delay analysis engine 208, whose functions will be described further hereinbelow. According to an embodiment of the disclosure, RADM 200 and its components may be located at source node 120. According to an embodiment of the disclosure, PADM 200 may comprise at least one port 209 for receiving and transmitting packets transmitted through PSN 100, for example DM packets exchanged between source node 120 and reflector node 130. Alternatively, one or more of the virtual clock, delay analysis engine, and memory may be located elsewhere in PSN 100.

(9) In accordance with an embodiment of the disclosure, reflector virtual clock 210 maintains information required to convert times according to reflector node clock 132 located in reflector node 130 into times according to source node clock 204.

(10) PSN 100 comprises an ensemble of nodes 102 and links connecting them. Among the nodes are source node 120 and reflector node 130. Solid line 104 represents a co-routed path from source node to reflector node to be taken by DM packets, schematically represented as rectangles 140.

(11) During NDM procedure 300, DM packets 140 comprised in a DM session are exchanged through PSN 100 between source node 120 and reflector node 130 (block 302). Each DM packet 140 is transmitted from source node 120 to reflector node 130, which is then reflected back from reflector node 130 to source node 120. The reflected DM packet is optionally based on the DM packet 140 that was transmitted from source node 120, but with requisite swapping of source and destination addresses. Alternatively, a forward DM request packet transmitted from source node 120 terminates at reflector node 130, and reflector node 130 responds by transmitting a response DM packet back to source node 120. As shown in FIG. 1, DM packets 140 are co-routed between source node 120 and reflector node 130, such that if a forward DM packet 140A transmitted from source node 120 to reflector node 130 traverses communications path 104, then a reverse DM packet 140B transmitted from reflector node 130 to source node 120 traverses the same communications path 104 in the opposite direction.

(12) In embodiments of the disclosure, the DM session may consist of a TWAMP session conforming to IETF RFC 5357, or an Ethernet OAM delay measurement session, conforming to ITU-T Recommendation Y.1731. These standards specify the format of DM packets and the procedures to be followed. It should be noted that any other format and procedures for sending packets and reflecting them back to source may be utilized.

(13) In prior art embodiments, a conventional DM session typically requires packet time distribution sessions to additionally be carried out in order for OWD measurements derived from the DM session to be accurate. Such packet time distribution sessions may consist of NTP sessions conforming to IETF RFC 1305 or 5905, or to PTP sessions conforming to IEEE standard 1588. For example, a time distribution session may be carried out immediately before and immediately after the DM session, and the state of the virtual clock during the DM session may be determined by interpolation. It is noted that the NDM method in accordance with an embodiment of the invention enables both determination of OWDs as well as updating of one or more virtual clocks using packet timing information gathered in a single DM session. As such, a NDM method in accordance with an embodiment of the disclosure may advantageously enable a reduction or elimination of certain network maintenance sessions, by way of example, time distribution sessions.

(14) NDM procedure 300 further comprises registering, for each DM packet, times of transmission and reception at source node 120 and reflector node 130 (block 304). In an embodiment of the disclosure, these times may be stored in memory 206 comprised in RADM apparatus 200.

(15) Let the n.sup.th DM packet of a given session be expressed as Packet.sub.n (n=1 . . . N), N being the total number of DM packets in the DM session. The set of observed times for Packet.sub.n may be expressed as timeset TS.sub.n.

(16) Let times observed by source node clock 204 be expressed as T.sub.j (j=1 . . . 4) and times observed by reflector node clock 132 be expressed as T.sub.j′ (j=1 . . . 4).

(17) In an embodiment of the disclosure, timeset TS.sub.n for a given Packet.sub.n comprises four observed times [T1, T2′, T3′, T4].sub.i in which:

(18) T1 is a time of transmission from source node 120 according to its local clock, source node clock 204;

(19) T2′ is a time of reception by reflector node 130 according to its local clock, reflector node clock 132;

(20) T3′ is a time of reflected transmission from reflector node 130 according to reflector node clock 132; and

(21) T4 is a time of reception of the reflected packet by source node 120 according to source node clock 204.

(22) In an embodiment of the disclosure, a DM packet 140A transmitted in a forward direction from source node 120 comprises T1, and a reflected DM packet 140B transmitted in a forward direction from reflector node 130 comprises T1, T2′ and T3′. When packet 140B is received at source node 120, T4 is observed, and the timeset T1, T2′, T3′ and T4 may be recorded in memory 206. Optionally, DM packets does not comprise transmission and reception times, and source node 120 and reflector node 130 provide timesets to memory 206 for recordation through some other means.

(23) In an embodiment of the disclosure, timeset TS.sub.n stored in memory 206 is processed by delay analysis engine 208. As described further below, delay analysis engine 208 may calculate one or more of the following for a DM session or DM packet Packet.sub.n in the DM session: an adjusted timeset; a FOWD (forward one-way delay); a ROWD (reverse one-way delay); an updated estimate of the FFD (forward floor delay); an updated estimate of the RFD (reverse floor delay); an updated state of reflector node virtual clock 210. Optionally, any or all of these may be stored in memory 206.

(24) In an embodiment of the disclosure, NDM procedure 300 comprises adjusting the timeset TS.sub.n based on the state of reflector node virtual clock 210 (block 306). In an embodiment of the disclosure, the state of reflector node virtual clock 210 comprises a time correction (which may be referred to herein as Δt) for performing conversions between a time in accordance with source node clock 204 and a time in accordance with reflector node clock 132. From the timeset [T1, T2′, T3′, T4], time correction Δt may be subtracted from times T2′ and T3′ measured by reflector node clock 132 in order to convert those times into T1 and T2 that are as if observed in accordance with source node clock 204. With the converted times, one obtains an adjusted timeset [T1, T2, T3, T4] comprising times in accordance with a single node clock (in this case source node clock 204). In an exemplary case, we may assume that the reflector node virtual clock 210 differs from the source node clock by an initial time offset and a constant frequency offset Δf, so that the time correction Δt(t) for a given time t may be determined according to the formula Δt(t)=Δt(0)+Δf t. The time correction Δt(t) may be subtracted from times measured with respect to the reflector node clock to obtain times as would be measured by the source node clock.

(25) Obtaining the adjusted timesets may advantageously allow for accurate calculation of one-way delays because the times are converted as needed to have all the times be referenced to a single clock. NDM procedure 300 further comprises using the adjusted timeset to calculate one-way delays experienced by the n.sup.th DM packet, which may be in accordance with the following formulas: FOWD.sub.n=T2.sub.n−T1.sub.n for the n.sup.th DM packet to get from source node 120 to reflector node 130; and ROWD.sub.n=T4.sub.n−T3.sub.n for the n.sup.th DM packet to get from reflector node 130 to source node 120 (block 308).

(26) As described above, T2′ and T3′ registered in accordance with reflector node clock 132 were converted to T2 and T3 in accordance with source node clock 204. Alternatively, the DM packet reception and transmission times in the time set may be adjusted to be in accordance with a same clock by converting T1 and T4 registered in accordance with source node clock 204 to T1′ and T4′ in accordance with reflector node clock 132, such that TS.sub.n comprising [T1, T2′, T3′, T4].sub.n is converted to an adjusted timeset comprising [T1′, T2′, T3′, T4′].sub.n. Optionally, the timeset is adjusted based on the state of reflector node virtual clock 210. Once the adjust timeset is obtained, FOWD.sub.n and ROWD.sub.n may be calculated in accordance with the formulas FOWD.sub.n=T2′.sub.n−T1′.sub.n and ROWD.sub.n=T4′.sub.n−T3′.sub.n. Note that the full timeset may be communicated to the virtual clock located at the reflector node by sending T4 in a following DM packet or by any other means.

(27) Alternatively, the DM packet reception and transmission times may be adjusted to be in accordance with a same clock by converting timeset [T1, T2′, T3′, T4] into an adjusted timeset comprising times [T1″, T2″, T3″, T4″] that are all in accordance with a reference clock (by way of example reference clock 402 as shown in FIG. 3) that is located at a third node that is neither source node 120 nor reflector node 130.

(28) Optionally, the plurality of FOWDs and/or ROWDs, or a selection thereof, are used to calculate one or more of the following statistics: an average (mean, median or mode), a minimum (which may be a floor delay), a maximum, a standard deviation, a skew, a kurtosis, and a percentile histogram. Other statistics may be calculated as needed.

(29) Only a subset of the DM packets transmitted during a session are expected to be lucky packets that experience no queuing delay during their traversal of PSN 100. Generally, a higher number of nodes traversed in a given communication route decreases the number of lucky packets during a session, because each additional node presents an additional chance of the packet experiencing queuing delay. While floor delay values are typically identified by testing round-trip delays against a gating criterion, separately gating FOWD and ROWD advantageously tend to return more lucky packets because fewer nodes are traversed. In a simple case where the probability of traversing a given node with no queuing delay has a value p, then a one-way probability P.sub.O of traversing M nodes in one direction may be calculated as P.sub.O=p.sup.M. However, the round trip probability P.sub.R of traversing the same path in both directions (and thus twice as many nodes) without queuing delay may be calculated as P.sub.R=p.sup.2M, which, given that p has a value between 0 and 1, is exponentially lower than P.sub.O. As an illustrative example, if the probability of traversing each node without queuing delay is 10% and there are 4 nodes in each direction, the probability of a minimal FOWD or ROWD is one in ten thousand (0.1.sup.4=1*10.sup.−4), while the probability of a lucky round trip is one in a hundred million (1*10.sup.−8).

(30) In NDM procedure 300 in accordance with an embodiment of the invention, the set of FOWD values and ROWD values collected during a DM session are tested against a gating criterion to select FOWD and ROWD values from DM packets presumed to be lucky packets (step 312). Optionally, the gating criterion comprises selecting FOWDs or ROWDs that are within a range above or below a predetermined value. Optionally, the predetermined value comprises a previously determined floor delay (FFD or RFD) estimate and the gating criterion comprises selecting packets with OWDs (FOWDs or ROWDs) that are within a range above or below a previously determined floor delay estimate.

(31) RADM apparatus 200 maintains, optionally in memory 206, an estimated floor delay between source node 120 and reflector node 130 in each direction: an estimated FFD for DM packets transmitted from source node 120 to reflector node 130 and an estimated RFD for DM packets transmitted from reflector node 130 to source node 120. In NDM procedure 300 in accordance with an embodiment of the invention, if a session comprising DM packets includes FOWD and/or ROWD values that pass the gating criterion, the estimated FFD and/or RFD values are updated (block 314). Optionally, one or more gating criterion-passing FOWDs, or an average (mean, median or mode) of a plurality of gating criterion-passing FOWDs, collected during a DM session may be used to calculate a new estimated FFD. Gating criterion-passing ROWDs may be used in the same way to calculate a new estimated RFD. Optionally, the new floor delay estimate is based on the one or more criterion-passing OWDs and a previously calculated floor delay estimate. It will be appreciated that the estimated floor delay may have a value that changes periodically over time, as new gating criterion-passing OWDs are detected, such that delay analysis engine 208 maintains a running estimate of the FFD and/or the RFD. Optionally, OWDs that did not pass the gating criterion may also be used to calculate a new estimated floor delay.

(32) In NDM procedure 300 in accordance to an embodiment of the disclosure, a state of a virtual clock, by way of example reflector node virtual clock 210, may be updated responsive to an updated estimated floor delay (block 316). For the co-routed case, as shown by way of example in FIG. 1, the floor delay is assumed to be independent of direction. Hence, time correction Δt may be updated such as to equalize estimates of FFD and RFD. Optionally, Δt is updated each a new estimated FFD or RFD is calculated. It will be appreciated that time correction may be Δt periodically updated to reflect periodically updating floor delays.

(33) Time correction Δt computed based on estimated floor delays may also not remain constant due to respective frequencies of the source node clock and the reflector node clock not being synchronized. In an embodiment of the disclosure, time correction Δt may be updated based on an estimated frequency offset Δf. In a case where frequency offset is constant (clock drift), the frequency offset may be estimated by linear regression, and time correction Δt as a given time t, Δt(t) may be calculated as Δt(t)=Δt(0)+Δf t. For more complex behavior of instantaneous frequency, more sophisticated modeling may be employed. The state of the virtual clock comprises a set of all or a combination of any of the parameters thus estimated.

(34) As described above, the updating of the virtual clock state rested on an assumption of equality of FFD and RFD. For the non-co-routed case this assumption cannot be made, and although frequency differences may still be determined, absolute time offsets may not. In such cases it may be possible to find a third node (which may be referred to as a reference node) having co-routed paths to both source and reflector nodes. In an embodiment of the disclosure, if such a reference node exists, then the above NDM procedures may be carried out from the reference node to both source and reflector nodes, thus enabling updating of a state of both a first virtual clock emulating the source clock and a second virtual clock emulating the reflector node clock.

(35) Reference is made to FIG. 3, which schematically illustrates packet switched network (PSN) 100 in DM packets are transmitted between DN 120 and RN 130 in a non-co-routed manner, in which DM packets are transmitted in a forward direction via communication path 104, and DM packets are transmitted in a reverse direction via a different communication path 106. Reference is also made to FIG. 4, which shows a flowchart showing procedure 500 to accurately measure one-way delay of packet transmission between source node 120 and reflector node 130 in accordance of an embodiment of the disclosure.

(36) Network 100 comprises a delay measurement center 200 in accordance with an embodiment of the disclosure that is engaging in a NDM procedure in accordance with an embodiment of the invention. Delay measurement center 400 is located neither at source node 120 nor reflector node 130, but at a reference node 125 with co-routed paths to source node 120 and a reflector node 130. Delay measurement center 400 is similar to RADM apparatus 200 described with reference to FIG. 1, with the exception that delay measurement center 400 comprises at least two virtual clocks, a reflector node virtual clock 410 that emulates a state of reflector node clock 132 located in reflector node 130; and a source node virtual clock 415 that emulates a state of source node clock 204 located in source node 120.

(37) During procedure 500 in accordance with an embodiment of the procedure, delay measurement center 400 maintains a first virtual clock 415 that emulates source node clock 204 and a second virtual clock 410 that emulates RN clock 132 (block 502). In an embodiment of the disclosure, virtual clocks 415 and 410 are maintained by a NDM procedure in accordance with an embodiment of the disclosure. Alternatively or additionally, one of source node clock 204 and reflector node clock 132 are synchronized to the other, or both are synchronized to a common master clock, through a packet-based time distribution protocol. The packet-based time distribution protocol is optionally PTP or NTP.

(38) The timesets of the DM session may be sent to and registered by the reference node (block 504), and the timestamps in the timesets may be converted, responsive to the respective states of first virtual clock 415 and/or second virtual clock 410, into times in accordance with a reference clock comprised in the reference node (block 506). By way of example, a timeset registered by delay measurement center 400 may comprise times [T1, T2′, T3′, T4], where T1 and T4 were measured in accordance with source node clock 204, and T2′ and T3′ were measured in accordance with reflector node clock 132. By subtracting a first time correction Δt.sub.1 comprised in the state of first virtual clock 415 from times T1 and T4 one obtains adjusted times T1″ and T4″ in accordance with reference clock 402. By subtracting a second time correction Δt.sub.2 comprised in the state of second virtual clock 410 from times T2′ and T3′ one obtains adjusted times T2″ and T3″ in accordance with reference clock 402. As a result, adjusted timeset [T1″, T2″, T3″, T4″] comprises times in accordance with a single node clock, reference clock 402.

(39) With all the times in the timesets thus being in accordance with a same clock, FOWD and ROWD may then be determined as described above (block 508), the determined OWDs may be used to determine an estimated floor delay, and the estimated floor delay may be used to update the state of the first and second virtual clocks, as described above.

(40) In an embodiment of the disclosure, the delay measurement center may maintain more than two virtual clock states emulating more than two node clocks in a network. Optionally, the more than two node clocks includes all node clocks in a network with available co-routed paths to the reference node.

(41) There is therefore provided in accordance with an embodiment of the disclosure a a method for measuring one-way delays in a communications network, the method comprising: transmitting a plurality of packets comprised in a communications session from a first node associated with a first node clock to a second node associated with a second node clock and receiving the plurality of packets after the packets are reflected from the second node back to the first node; maintaining a virtual clock state comprising information for converting times measured with respect to the first and/or second node clock into times as would be measured with respect to a reference clock; registering, for each packet of the plurality of packets in the communications session, a timeset comprising transmission and reception times at the first and second nodes that are measured with respect to the first and second node clocks, respectively; converting, responsive to the virtual clock, times in the timeset measured with respect to the first node clock or the second node clock, into times as would be measured with respect to the reference clock; calculating, for each packet of the series of packets, a forward one-way delay (FOWD) from the first node to the second node and a reverse one-way delay (ROWD) from the second node to the first node, responsive to the converted timeset.

(42) In an embodiment of the disclosure, the method further comprises: testing the FOWD and ROWD of each packet of the series of packets against a gating criterion; updating estimates of forward floor delay (FFD) and reverse floor delay (RFD) responsive to FOWDs and/or ROWDs that pass the gating criterion; and updating the virtual clock state responsive to the updated estimate of FFD and/or RFD.

(43) In an embodiment of the disclosure, the method further comprises recalculating the FOWD and the ROWD of the packets responsive to the updated virtual clock state.

(44) In an embodiment of the disclosure, the reference clock is the first node clock or the second node clock.

(45) In an embodiment of the disclosure, the updating of the virtual clock state is further responsive to FOWD and ROWD of packets that did not pass the gating criterion.

(46) In an embodiment of the disclosure, the method comprises computing at least one one-way delay statistic for the FOWD and/or the ROWD, the at least one one-way delay statistic being selected from the group consisting of: a minimum, a maximum, a standard deviation, a skew, a kurtosis, and a percentile histogram.

(47) In an embodiment of the disclosure, the communications session is a TWAMP session or a Y.1731 session.

(48) There is also provided in accordance with an embodiment of the disclosure a method for measuring one-way delays in a communications network, the method comprising: maintaining, at a third node having a third node clock, a first virtual clock state emulating a first node clock located at a first node and a second virtual clock state emulating a second node clock located at a second node; registering a timeset comprising transmission and reception times at the first node and the second node, respectively, for each packet of a plurality of packets that are transmitted from the first node to the second node and reflected from the second node back to the first node; converting times in the timeset, responsive to the first and/or second virtual clocks, into times in accordance with a reference clock; calculating, for each packet of the plurality of packets, a forward one-way delay (FOWD) from the first node to the second node and a reverse one-way delay (ROWD) from the second node to the first node, responsive to the converted timeset.

(49) In an embodiment of the disclosure, the reference clock is the first node clock, the second node clock, or the third node clock.

(50) In an embodiment of the disclosure, the method computing at least one one-way delay statistic for the FOWD and/or the ROWD, the at least one one-way delay statistic being selected from the group consisting of: a minimum, a maximum, a standard deviation, a skew, a kurtosis, and a percentile histogram.

(51) In an embodiment of the disclosure, the communications session is a TWAMP session or a Y.1731 session.

(52) There is also provided an apparatus for measuring one-way delays in a communications network comprising: a local clock; a memory, at least one virtual clock emulating a node clock located in a remote node; a delay analysis engine operable to: register, for each packet of a plurality of packets comprised in a communications session between a first node collocated with a first node clock and a second node collocated with a second node clock, a timeset comprising transmission and reception times at the first and second nodes that are measured with respect to the first and second node clocks, respectively; convert the times comprised in the timeset to be in accordance with a reference clock responsive to the at least one virtual clock; and calculate for each packet of the plurality of packets, a forward one-way delay (FOWD) from the first node to the second node and a reverse one-way delay (ROWD) from the second node to the first node, responsive to the converted timeset responsive to the converted timeset.

(53) In an embodiment of the disclosure, the apparatus further comprises at least one port for communicating with the communications network.

(54) In an embodiment of the disclosure, the apparatus further comprises a packet source operable to generate and transmit the plurality of packets.

(55) In an embodiment of the disclosure, the delay analysis engine is further operable to determine an estimated FFD and an estimated RFD responsive to the FOWD and the ROWD, respectively.

(56) In an embodiment of the disclosure, the delay analysis engine is further operable to update a state of the at least one virtual clock responsive to the estimated FFD and/or the RFD.

(57) In an embodiment of the disclosure, the reference clock is the first node clock, or a second node clock.

(58) In an embodiment of the disclosure, the apparatus comprises at least two virtual clocks emulating the first and second node clocks, respectively, and the reference clock is a third node clock that is located in a third node.

(59) As used herein, the term “location”, “remote”, “local”, or other terms relating to location may refer to a physical location and/or a logical location.

(60) Descriptions of embodiments of the disclosure in the present application are provided by way of example and are not intended to limit the scope of the disclosure. The described embodiments comprise different features, not all of which are required in all embodiments of the disclosure. Some embodiments utilize only some of the features or possible combinations of the features. Variations of embodiments of the disclosure that are described, and embodiments of the disclosure comprising different combinations of features noted in the described embodiments, will occur to persons of the art. The scope of the disclosure is limited only by the claims.