ABSOLUTE-TYPE LINEAR ENCODER ABSOLUTE SIGNAL CONSISTENCY CORRECTION METHOD

Abstract

An absolute-type linear encoder absolute signal consistency correction method, related to the field of absolute-type linear encoder measurements, for solving the problem of narrow linear range for photoelectric responses and large signal dispersion found in an existing consistency correction method for a photoelectric conversion component and a processing circuit thereof. The correction method allows for enhanced absolute signal quality and increased system measurement precision.

Claims

1. An absolute signal consistency correction method for an absolute grating scale, the method adopting a formula of:
v=P.Math.(1+A).Math.I+Q.Math.(1+A).Math.(C−D)+D where v represents a voltage value output by a photodiode array and an amplifying and sampling holding circuit array after processing of a consistency correction structure; I represents a bias current of a light source; P and Q represent two constant coefficient vectors of the photodiode array and the amplifying and sampling holding circuit array; D represents a constant voltage value; A represents a correction vector of a gain correction circuit of the photodiode array and the amplifying and sampling holding circuit array; and C represents a correction vector of a bias correction circuit of the photodiode array and the amplifying and sampling holding circuit array; the above formula simplified as
v=K.Math.I+B wherein, K=P.Math.(1+A), B=Q.Math.(1+A).Math.(C−D)+D, the method comprising steps of: S1: by a host computer, respectively inputting two groups of initial correction data vectors a.sub.1[1:n] and b.sub.1[1:n] to the gain correction circuit and the bias correction circuit through a storage, then respectively regulating bias currents of the light source into I.sub.1, I.sub.2, I.sub.3, . . . , I.sub.m from weak to strong, where m represents a grade number of regulation, and simultaneously recording voltage values v1.sub.1[1:m], v1.sub.2[1: m], v1.sub.3[1: m], . . . , v1.sub.n[1: m]output by the n photodiodes under m grades of bias currents of the light source after processing of the consistency correction structure; S2: carrying out linear fitting on response curves of the voltage values output by the n photodiodes under m grades of bias currents of the light source after processing of the consistency correction structure obtained in the step S1, and then calculating slope vectors K[1:n] and intercept vectors B[1:n] of response straight lines of voltage values output by the n photodiodes under m grades of bias currents of the light source after processing of the consistency correction structure, so that the 2n constant coefficient vectors P[1:n] and Q[1:n] of the photodiode array and the amplifying and sampling holding circuit array can be obtained; S3: selecting one of the n response straight lines obtained in the step S2 as a target straight line, fitting the other n-1 response straight lines to the target response straight line, to obtain correction data vectors a.sub.2[1: n] of the gain correction circuit and correction data vectors b.sub.2[1: n] of the bias correction circuit; S4: by the host computer, inputting the correction data vectors a.sub.2[1: n] and the correction data vectors b.sub.2[1: n], which are obtained in the step S3, into the gain correction circuit and the bias correction circuit through the storage, then regulating the bias current of the light source into an intermediate value I.sub.m/2, and simultaneously recording voltage values v2.sub.1[m/2], v2.sub.2[m/2], v2.sub.3[m/2], . . . , v2.sub.n[m/2] output by the n photodiodes under the bias current of the light source; S5: carrying out averaging on n voltage values v2.sub.1[m/2], v2.sub.2[m/2], v2.sub.3[m/2], . . . , v2.sub.n[m/2] obtained in the step S4, then translating all the response straight lines of the output voltages towards an average value, and only regulating the correction data vectors of the bias correction circuit to obtain a group of new correction data vectors b.sub.3[1: n]; S6: repeating the step S4 and the step S5 until dispersions of the response straight lines of the out voltages meet requirements, and then obtaining correction data vectors a.sub.2[1: n] of the gain correction circuit and correction data vectors b.sub.4[1: n] of the bias correction circuit; S7: carrying out linearity range expansion on the response straight lines of the output voltages, which are obtained in the step S6, slightly increasing each value in the correction data vectors a.sub.2[1: n] of the gain correction circuit, and slightly reducing each value of the correction data vectors b.sub.4[1: n] of the bias correction circuit, so as to obtain new correction data vectors a.sub.3[1: n] of the gain correction circuit and new correction data vectors b.sub.5[1: n] of the bias correction circuit; S8: by the host computer, transmitting the correction data vectors a.sub.3[1: n] of the gain correction circuit and the correction data vectors b.sub.5[1: n] of the bias correction circuit to the gain correction circuit and the bias correction circuit through the storage, detecting whether linearity ranges of the response straight lines of the output voltages meet requirements, and if no, repeating the step S7 until the requirements are met, so as to obtain correction data vectors a.sub.4[1: n] of the gain correction circuit and correction data vectors b.sub.6[1: n] of the bias correction circuit; S9: detecting whether the dispersions of the response straight lines of the output voltages at the moment meet requirements, and if no, respectively inputting, by the host computer, two groups of new initial correction data a.sub.4[1: n] and b.sub.6[1: n] to the correction data vectors of the gain correction circuit and the correction data vectors of the bias correction circuit through the storage, and repeatedly executing the steps S1 to S9 until the dispersions and the linearity ranges of the response straight lines of the output voltages meet the requirements.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG. 1 is a flow chart of an absolute signal consistency correction method for an absolute grating scale according to the present disclosure.

[0022] FIG. 2 is a structural schematic diagram of a system adopted by the absolute signal consistency correction method for the absolute grating scale according to the present disclosure.

[0023] FIG. 3 is a schematic diagram of after linear fitting the n voltage response cuves according to the present disclosure.

[0024] FIG. 4 is a schematic diagram of a process of translating the n response straight lines to an average value according to the present disclosure; FIG. 4(a) is a schematic diagram before translating, and FIG. 4(b) is a schematic diagram after translating.

[0025] FIG. 5 is a schematic diagram of response straight lines of voltages output by the photodiode array and the amplifying and sampling holding circuit after processing of a consistency correction structure, which are subjected to linearity range expansion, according to the present disclosure.

[0026] FIG. 6 shows response curves of voltages output by 20 photodiodes and 20 amplifying and sampling holding circuits after processing of the consistency correction structure in the initial data correction process in an embodiment of the present disclosure.

[0027] FIG. 7 shows translated response straight lines of the voltages output by 20 photodiodes and 20 amplifying and sampling holding circuits after processing of the consistency correction structure in the embodiment of the present disclosure.

[0028] FIG. 8 shows response straight lines of the voltages output by 20 photodiodes and 20 amplifying and sampling holding circuits after processing of the consistency correction structure, which are subjected to linearity range expansion, in the embodiment of the present disclosure.

DETAILED DESCRIPTION

[0029] A method provided by the present disclosure will be further illustrated in details in connection with the drawings and embodiments in the following.

[0030] As shown in FIG. 2, a system structure adopted by an absolute signal consistency correction method for an absolute grating scale includes a light source 1, a collimating lens 2, a grating scale 3 on which absolute codes are engraved, a photodiode array 4, an amplifying and sampling holding circuit array 5, a bias correction circuit 6, a gain correction circuit 7, a consistency correction structure 8, a storage 9 and a host computer 10, wherein, the consistency correction structure 8 includes the bias correction circuit 6 and the gain correction circuit 7. The photodiode array 4, the amplifying and sampling holding circuit array 5, the bias correction circuit 6, the gain correction circuit 7 and the storage 9 are integrated on one silicon slice.

[0031] The system structure adopts a working principle that firstly, a system is powered on, and the host computer 10 transmits initial correction data vectors a.sub.1[1: n] of the gain correction circuit 7 and initial correction data vectors b.sub.1[1: n] of the bias correction circuit 6 to the storage 9; the light source 1 can emit light with corresponding intensities by regulating bias currents of the light source 1, the light passes through the collimating lens 2 to generate parallel light, and after the parallel light passes through the grating scale 3 on which the absolute codes are engraved, the photodiode array 4 receives optical signals with the absolute codes and outputs n light currents with absolute code information, and then the amplifying and sampling holding circuit array 5 carries out amplifying and sampling holding processing on the n light currents and outputs n voltage signals with the absolute code information; the bias correction circuit 6 requests the correction data vectors b.sub.1[1: n] of the bias correction circuit 6 for the storage 9, correction vectors C of the bias correction circuit 6 are formed by a D/A (Digital-to-Analog) conversion circuit, simultaneously, the gain correction circuit 7 requests the correction data vectors a.sub.1[1: n] of the gain correction circuit 7 for the storage 9, and the correction data vectors a.sub.1[1: n] are converted into correction vectors A of the gain correction circuit 7. The bias correction circuit 6 and the gain correction circuit 7 correct the voltage signals with the absolute code information, which are output by the amplifying and sampling holding circuit array 5 and uploads corrected voltages to the host computer 10, and the host computer 10 judges whether linearity ranges and dispersions of response straight lines of voltages output by the photodiode array 4 and the amplifying and sampling holding circuit array 5 of the absolute grating scale under m grades of bias currents of the light source 1 after processing of the consistency correction structure 8 meet requirements.

EMBODIMENTS

[0032] The absolute signal consistency correction method for the absolute grating scale specifically includes steps of:

[0033] S1: by the host computer 10, respectively inputting two groups of initial correction data vectors a.sub.1[1:n] and b.sub.1[1:n] to the gain correction circuit 7 and the bias correction circuit 6 of the consistency correction structure 8 of the photodiode array 4 (20 photodiodes are selected) and the amplifying and sampling holding circuit array 5 (20 amplifying and sampling holding circuits are selected) of the absolute grating scale through the storage 9; supposing that each element value in the correction data vectors a.sub.1[1:n] of the gain correction circuit 7 is 15 and each element value in the correction data vectors b.sub.1[1:n] of the bias correction circuit 6 is 32.

[0034] A rated bias current of the adopted light source 1 is 50 mA, 8 bias current grades of the light source 1 are taken respectively as 2.5 mA, 7.0 mA, 11.0 mA, 15.5 mA, 19.5 mA, 23.5 mA, 28.0 mA and 32.0 mA., bias currents of the light source 1 are regulated respectively to the above 8 values, voltage values v1.sub.1[1:8], v1.sub.2[1: 8], v1.sub.3[1: 8], . . . , v1.sub.20[1: 8] output by the 20 photodiodes and the 20 amplifying and sampling holding circuits under each bias current of the light source 1 after processing of the consistency correction structure 8 are stored on the host computer 10, and the diagram is drawn on the host computer 10; as shown in FIG. 6, a saturation output voltage of the design circuit is 3.3V, and response curves of output voltages after processing of the consistency correction structure 8 are great in dispersion and are also not wide in linearity range.

[0035] S2: carrying out linear fitting on the response curves of the voltages v1.sub.1[1:8], v1.sub.2[1: 8], v1.sub.3[1: 8], . . . ,v1.sub.20[1: 8] output by the 20 photodiodes after processing of the consistency correction structure 8, which are obtained in the step S1, and then calculating slope vectors K[1:20] and intercept vectors B[1:20] of 20 response straight lines after fitting, as shown in Table 1:

TABLE-US-00001 TABLE 1 Slope K[1] K[2] K[3] K[4] K[5] K[6] K[7] K[8] K[9] K[10] 0.067 0.070 0.068 0.064 0.071 0.069 0.072 0.069 0.073 0.067 Slope K[11] K[12] K[13] K[14] K[15] K[16] K[17] K[18] K[19] K[20] 0.072 0.067 0.066 0.069 0.070 0.073 0.072 0.069 0.071 0.072 Intercept B[1] B[2] B[3] B[4] B[5] B[6] B[7] B[8] B[9] B[10] 0.537 0.497 0.450 0.274 0.340 0.563 0.458 0.416 0.447 0.323 Intercept B[11] B[12] B[13] B[14] B[15] B[16] B[17] B[18] B[19] B[20] 0.540 0.415 0.330 0.373 0.445 0.541 0.520 0.551 0.525 0.566

[0036] Suppose that according to design of the consistency correction structure 8, the D/A conversion circuit in the bias correction circuit 6 reads corresponding correction data vectors b[1:20] of the bias correction circuit 6 from the storage 9, and converts the correction data vectors b[1:20] into corresponding correction vectors C[1:20] of the bias correction circuit 6, and a conversion formula is:

C[i]=0.00343a[i]+0.191 i=1,2, . . . 20   (5)

[0037] The gain correction circuit 7 reads corresponding correction data vectors a[1:20] of the gain correction circuit 7 from the storage 9, and converts the correction data vectors a[1:20] into corresponding correction vectors A[1:20] of the gain correction circuit 7, and a conversion formula is:

A[i]=0.16b[i]+0.156 i=1,2, . . . 20   (6)

[0038] By the formulas (3), (4), (5) and (6), 40 constant coefficient vectors P[1:20] and Q[1:20] can be calculated, as shown in Table 2:

TABLE-US-00002 TABLE 2 P[1] P[2] P [3] P [4] P [5] P [6] P [7] P [8] P [9] P [10] 0.0135 0.0142 0.0136 0.0129 0.0144 0.0140 0.0146 0.0139 0.0146 0.0135 P [11] P [12] P [13] P [14] P [15] P [16] P [17] P [18] P [19] P [20] 0.0145 0.0136 0.0133 0.0139 0.0142 0.0146 0.0146 0.0139 0.0144 0.0146 Q[1] Q [2] Q [3] Q [4] Q [5] Q [6] Q [7] Q [8] Q [9] Q [10] 1.7487 1.4874 1.1798 0.0245 0.4604 1.9195 1.2310 0.9584 1.1602 0.3482 Q [11] Q [12] Q [13] Q [14] Q [15] Q [16] Q [17] Q [18] Q [19] Q [20] 1.7682 0.9531 0.3942 0.6744 1.1487 1.7778 1.6409 1.8422 1.6708 1.9376

[0039] S3: selecting a tenth response straight line from 20 response straight lines obtained in the step S2 as a target response straight line, fitting the other 19 response straight lines to the target response straight line, and calculating, by the host computer 10, correction data vectors a.sub.2[1: 20] of the gain correction circuit 7 and correction data vectors b.sub.2[1: 20] of the bias correction circuit 6 after fitting, as shown in Table 3:

TABLE-US-00003 TABLE 3 a.sub.2 [1] a.sub.2 [2] a.sub.2 [3] a.sub.2 [4] a.sub.2 [5] a.sub.2 [6] a.sub.2 [7] a.sub.2 [8] a.sub.2 [9] a.sub.2 [10] 19 17 19 21 17 18 16 18 16 19 a.sub.2 [11] a.sub.2 [12] a.sub.2 [13] a.sub.2 [14] a.sub.2 [15] a.sub.2 [16] a.sub.2 [17] a.sub.2 [18] a.sub.2 [19] a.sub.2 [20] 16 19 20 18 17 16 16 18 17 16 b.sub.2 [1] b.sub.2 [2] b.sub.2 [3] b.sub.2 [4] b.sub.2 [5] b.sub.2 [6] b.sub.2 [7] b.sub.2 [8] b.sub.2 [9] b.sub.2 [10] 24 25 25 31 28 24 25 25 25 29 b.sub.2 [11] b.sub.2 [12] b.sub.2 [13] b.sub.2 [14] b.sub.2 [15] b.sub.2 [16] b.sub.2 [17] b.sub.2 [18] b.sub.2 [19] b.sub.2 [20] 24 25 28 26 25 24 24 24 24 24

[0040] S4: by the host computer 10, inputting the correction data vectors a.sub.2[1: 20] of the gain correction circuit 7 and the correction data vectors b.sub.2[1: 20] of the bias correction circuit 6, which are obtained in the step S3, into the consistency correction structure 8 through the storage 9, then regulating the bias current of the light source 1 into an intermediate value I.sub.4, and simultaneously recording voltage values v2.sub.1[4], v2.sub.2[4], v2.sub.3[4], . . . , v2.sub.20[4] output by the 20 photodiodes under the bias current of the light source 1, as shown in Table 4:

TABLE-US-00004 TABLE 4 v2.sub.1[4] v2.sub.2[4] v2.sub.3[4] v2.sub.4[4] v2.sub.5[4] v2.sub.6[4] v2.sub.7[4] v2.sub.8[4] v2.sub.9[4] v2.sub.10[4] 1.40 1.40 1.35 1.33 1.35 1.45 1.35 1.31 1.36 1.33 v2.sub.11[4] v2.sub.12[4] v2.sub.13[4] v2.sub.14[4] v2.sub.15[4] v2.sub.16[4] v2.sub.17[4] v2.sub.18[4] v2.sub.19[4] v2.sub.20[4] 1.40 1.30 1.31 1.31 1.34 1.42 1.38 1.42 1.38 1.42

[0041] S5: carrying out averaging on the voltage values v2.sub.1[4], v2.sub.2[4], v2.sub.3[4], . . . , v2.sub.20[4] in the step S4 to obtain an average value of 1.37, then only regulating the correction data vectors b.sub.2[1: 20] of the bias correction circuit 6, translating the response straight lines of the output voltages after processing of the consistency correction structure 8 towards the position of the average value of 1.37, and according to the formulas (4) and (5), calculating, by the host computer 10, a group of new correction data vectors b.sub.3[1: 20] of bias correction circuit 6, as shown in Table 5:

TABLE-US-00005 TABLE 5 b.sub.3 [1] b.sub.3 [2] b.sub.3 [3] b.sub.3 [4] b.sub.3 [5] b.sub.3 [6] b.sub.3 [7] b.sub.3 [8] b.sub.3 [9] b.sub.3 [10] 24 25 26 33 29 22 26 27 26 31 b.sub.3 [11] b.sub.3 [12] b.sub.3 [13] b.sub.3 [14] b.sub.3 [15] b.sub.3 [16] b.sub.3 [17] b.sub.3 [18] b.sub.3 [19] b.sub.3 [20] 24 27 30 28 26 23 24 23 23 22

[0042] S6: repeating the step S4 and the step S5 until the dispersions of the response straight lines of the output voltages meet requirements. The 20 translated response straight lines are as shown in FIG. 7. Then correction data vectors b.sub.4[1: n] of the bias correction circuit 6 are obtained, as shown in Table 6:

TABLE-US-00006 TABLE 6 b.sub.4 [1] b.sub.4 [2] b.sub.4 [3] b.sub.4 [4] b.sub.4 [5] b.sub.4 [6] b.sub.4 [7] b.sub.4 [8] b.sub.4 [9] b.sub.4 [10] 24 25 26 32 29 22 26 27 26 31 b.sub.4 [11] b.sub.4 [12] b.sub.4 [13] b.sub.4 [14] b.sub.4 [15] b.sub.4 [16] b.sub.4 [17] b.sub.4 [18] b.sub.4 [19] b.sub.4 [20] 24 27 30 28 27 23 24 23 23 23

[0043] S7: carrying out linearity range expansion on the response straight lines of the output voltages, which are obtained in the step S6, so as to meet an input range requirement of a subsequent analog-digital collector, slightly increasing each value in the correction data vectors a.sub.2[1: 20] of the gain correction circuit 7, and slightly reducing each value of the correction data vectors b.sub.4[1: 20] of the bias correction circuit 6, so as to obtain new correction data vectors a.sub.3[1: 20] of the gain correction circuit 7 and new correction data vectors b.sub.5[1: 20] of the bias correction circuit 6, as shown in Table 7:

TABLE-US-00007 TABLE 7 a.sub.3 [1] a.sub.3 [2] a.sub.3 [3] a.sub.3 [4] a.sub.3 [5] a.sub.3 [6] a.sub.3 [7] a.sub.3 [8] a.sub.3 [9] a.sub.3 [10] 29 27 29 31 27 28 26 28 26 29 a.sub.3 [11] a.sub.3 [12] a.sub.3 [13] a.sub.3 [14] a.sub.3 [15] a.sub.3 [16] a.sub.3 [17] a.sub.3 [18] a.sub.3 [19] a.sub.3 [20] 26 29 30 28 27 26 26 28 27 26 b.sub.5 [1] b.sub.5 [2] b.sub.5 [3] b.sub.5 [4] b.sub.5 [5] b.sub.5 [6] b.sub.5 [7] b.sub.5 [8] b.sub.5 [9] b.sub.5 [10] 17 18 19 25 22 15 19 20 19 24 b.sub.5 [11] b.sub.5 [12] b.sub.5 [13] b.sub.5 [14] b.sub.5 [15] b.sub.5 [16] b.sub.5 [17] b.sub.5 [18] b.sub.5 [19] b.sub.5 [20] 17 20 23 21 20 16 17 16 16 16

[0044] S8: by the host computer 10, transmitting the correction data vectors a.sub.3[1: 20] of the gain correction circuit 7 and the correction data vectors b.sub.5[1: 20] of the bias correction circuit 6 to the gain correction circuit 7 and the bias correction circuit 6 through the storage 9, detecting whether the linearity ranges of the response straight lines of the output voltages meet requirements at the moment; as shown in FIG. 8, the linearity ranges of the response straight lines of the output voltages are obviously improved compared to those in FIG. 6.

[0045] S9: detecting whether the dispersions of the response straight lines of the output voltages at the moment meet requirements, and if no, by the host computer 10, respectively inputting two groups of new initial correction data a.sub.3[1: 20] and b.sub.5[1: 20] to the correction data vectors of the gain correction circuit 7 and the correction data vectors of the bias correction circuit 6, and repeatedly executing the steps S1 to S9 until the dispersions and the linearity ranges of the response straight lines of the output voltages after processing of the consistency correction structure 8 meet the requirements. Finally, correction data vectors a.sub.4[1: 20] of the gain correction circuit 7 and correction data vectors b.sub.6[1: 20] of the bias correction circuit 6 are obtained, as shown in Table 8.

TABLE-US-00008 TABLE 8 a.sub.4 [1] a.sub.4 [2] a.sub.4 [3] a.sub.4 [4] a.sub.4 [5] a.sub.4 [6] a.sub.4 [7] a.sub.4 [8] a.sub.4 [9] a.sub.4 [10] 33 31 33 36 30 31 30 32 29 34 a.sub.4 [11] a.sub.4 [12] a.sub.4 [13] a.sub.4 [14] a.sub.4 [15] a.sub.4 [16] a.sub.4 [17] a.sub.4 [18] a.sub.4 [19] a.sub.4 [20] 30 32 29 34 30 33 34 32 31 30 b.sub.6 [1] b.sub.6 [2] b.sub.6 [3] b.sub.6 [4] b.sub.6 [5] b.sub.6 [6] b.sub.6 [7] b.sub.6 [8] b.sub.6 [9] b.sub.6 [10] 14 15 17 23 20 14 16 18 17 21 b.sub.6 [11] b.sub.6 [12] b.sub.6 [13] b.sub.6 [14] b.sub.6 [15] b.sub.6 [16] b.sub.6 [17] b.sub.6 [18] b.sub.6 [19] b.sub.6 [20] 13 18 22 19 17 13 14 14 14 13