METHOD AND DEVICE FOR OPERATING POWER SEMICONDUCTOR SWITCHES CONNECTED IN PARALLEL

Abstract

The invention relates to a method (100) and a control device (SG) for operating power semiconductor switches (LH1 . . . LHn) connected in parallel, having the following steps: determining a nominal value for a total gate series resistor (GGVL . . . GGVn) of at least one power semiconductor switch (LH1 . . . LHn); providing the total gate series resistor (GGV1 . . . GGVn) for the at least one power semiconductor switch (LH1 . . . LHn) depending on the relevant nominal value, and operating the at least one power semiconductor switch (LH1 . . . LHn) with the associated total gate series resistor (GGV1 . . . GGVn).

Claims

1. A method for operating power semiconductor switches (LH1 . . . LHn) connected in parallel, wherein a total gate series resistor (GGV1 . . . GGVn) is assigned to at least one of the power semiconductor switches (LH1 . . . LHn), the method comprising: ascertaining (220), via a control device, a setpoint value for the total gate series resistor (GGV1 . . . GGVn) of the at least one power semiconductor switch (LH1 . . . LHn), forming (240), via the control device, the total gate series resistor (GGV1 . . . GGVn) for the at least one power semiconductor switch (LH1 . . . LHn) depending on the setpoint value, and operating (250), via the control device, the at least one power semiconductor switch (LH1 . . . LHn) with the associated total gate series resistor (GGV1 . . . GGVn).

2. The method as claimed in claim 1 comprising the following additional steps: providing (230) a multiplicity of gate series resistors (GV1 . . . GVn) which can be assigned to the at least one total gate series resistor (GGV1 . . . GGVn), and selecting a selection from the multiplicity of gate series resistors (GV1 . . . GVn) depending on the setpoint value ascertained, wherein forming (240) the at least one total gate series resistor (GGV1 . . . GGVn) is carried out by interconnecting the selected gate series resistors (GV1 . . . GVn).

3. The method as claimed in claim 1 comprising the following additional step: ascertaining a respective temperature (T1 . . . Tn) of at least one first and one second one of the power semiconductor switches (LH1 . . . LHn), wherein ascertaining the at least one setpoint value is carried out depending on the temperatures (T1 . . .Tn) ascertained.

4. The method as claimed in claim 3, wherein ascertaining the at least one setpoint value is carried out depending on a difference between the ascertained temperatures (T1 . . . Tn) of the at least first and second power semiconductor switches (LH1 . . . LHn).

5. The method as claimed in claim 1 comprising the following additional step: ascertaining a respective current (I1 . . . In) through at least one first and one second one of the power semiconductor switches (LH1 . . . LHn), wherein ascertaining the at least one setpoint value is carried out depending on the currents (I1 . . . In) ascertained.

6. The method as claimed in claim 5, wherein ascertaining the at least one setpoint value is carried out depending on a difference between the ascertained currents (I1 . . . In) through the at least first and second power semiconductor switches (LH1 . . . LHn).

7. The method as claimed in claim 1, wherein ascertaining the setpoint value, forming the total gate series resistor (GGV1 . . . GGVn) and operating the at least one of the power semiconductor switches (LH1 . . . LHn) are carried out by means of at least one logic unit (LE).

8. The method as claimed in claim 1, wherein at least partly parallel-connected power semiconductor modules are used as power semiconductor switches (LH1 . . . LHn) connected in parallel, wherein a power semiconductor module comprises power semiconductor switches connected in parallel.

9. A control device (SG) for operating power semiconductor switches (LH1 . . . LHn) connected in parallel, wherein a total gate series resistor (GGV1 . . . GGVn) is assigned to at least one of the power semiconductor switches (LH1 . . . LHn) and the control device (SG), wherein the control device is configured to ascertain a setpoint value for the total gate series resistor (GGV1 . . . GGVn) of the at least one power semiconductor switch (LH1 . . . LHn), to form the total gate series resistor (GGV1 . . . GGVn) of the at least one power semiconductor switch (LH1 . . . LHn) depending on the setpoint value, and to operate the at least one power semiconductor switch (LH1 . . . LHn) with the associated total gate series resistor (GGV1 . . . GGVn).

10. An electrical circuit comprising power semiconductor switches (LH1 . . . LHn) connected in parallel, wherein a total gate series resistor (GGV1 . . . GGVn) is assigned to at least one of the power semiconductor switches (LH1 . . . LHn), wherein the value of the total gate series resistor (GGV1 . . . GGVn) is variably adjustable.

11. An electrical system (10) comprising power semiconductor switches (LH1 . . . LHn) connected in parallel, comprising total gate series resistors (GGV1 . . . GGVn) and a control device (SG) configured to ascertain a setpoint value for the total gate series resistor (GGV1 . . . GGVn) of the at least one power semiconductor switch (LH1 . . . LHn), to form the total gate series resistor (GGV1 . . . GGVn) of the at least one power semiconductor switch (LH1 . . . LHn) depending on the setpoint value, and to operate the at least one power semiconductor switch (LH1 . . . LHn) with the associated total gate series resistor (GGV1 . . . GGVn).

12. (canceled)

13. A non-transitory machine-readable storage that when executed on a computer, cause the computer to ascertain a setpoint value for the total gate series resistor of at least one power semiconductor switch, control forming the total gate series resistor for the at least one power semiconductor switch the setpoint value, and operate the at least one power semiconductor switch with the associated total gate series resistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Further features and advantages of embodiments of the invention are evident from the following description with reference to the accompanying drawings.

[0040] The invention will be explained in greater detail below with reference to some figures. To that end, in the figures:

[0041] FIG. 1 shows an electrical system comprising a control device in a schematic illustration

[0042] FIG. 2 shows an excerpt from the electrical system from FIG. 1

[0043] FIG. 3 shows a flow diagram for a method for operating power semiconductor switches connected in parallel.

DETAILED DESCRIPTION

[0044] FIG. 1 shows an electrical system 10 in a schematic illustration. The electrical system 10 comprises power semiconductor switches LH1, LH2, LH3 . . . LHn, which are connected in parallel and conduct an electric current from the potential T+to the potential T− in the closed state and isolate the potentials in the open state. The gate terminals of the power semiconductor switches LH1 . . . LHn are connected to the respective total gate series resistors GGV1, GGV2, GGV3 . . . GGVn. Furthermore, a control device SG is provided, which is connected via the individual total gate series resistors GGV1 . . . GGVn to the individual gate terminals of the power semiconductor switches LH1 . . . LHn. By applying a voltage by means of voltage source (not illustrated) at the gate terminals of the power semiconductor switches LH1 . . . LHn, the power switches are controlled or a current flow through them is made possible; by removing or disconnecting the voltage at the gate terminals of the power semiconductor switches LH1 . . . LHn, the current flow through the latter is interrupted. Furthermore, temperature sensors T1, T2, T3 . . . Tn are provided for ascertaining the temperatures at the individual power semiconductor switches. The temperature sensors can be fitted directly on the individual semiconductors. A different position of the temperature sensors is also conceivable if the temperature value ascertained can be assigned to a corresponding power semiconductor switch LH1 . . . LHn and the temperature of the corresponding power semiconductor switch LH1 . . . LHn can be deduced therefrom. Furthermore, the power semiconductor switches LH1 . . . LHn have the sense terminals. By means of the latter, the control device can determine the current intensity through the individual power semiconductor switches LH1 . . . LHn. Here, too, other variants for measuring the current through the individual power semiconductor switches LH1 . . . LHn are conceivable. It should once again be possible to assign an ascertained current value to a power semiconductor switch. Depending on the temperatures ascertained and/or the currents ascertained, the control device in each case ascertains setpoint values for the total gate series resistors GGV1 . . . GGVn by means of which the power semiconductor switches LH1 . . . LHn are operated. Particularly in the case of a combined ascertainment of the setpoint values depending on the ascertained temperatures and currents, it is possible to predefine the setpoint values for the total gate series resistors GGV1 . . . GGVn even more exactly. The control device SG furthermore comprises a logic unit LE, which performs and controls the process of ascertaining the setpoint value, the process of forming the total gate series resistor GGVn and the operation of the at least one of the power semiconductor switches LHn.

[0045] FIG. 2 shows the construction of a variably adjustable total gate series resistor GGVn in particular in a schematic form. A multiplicity of gate series resistors GVn, GV1, GV2, GV3 . . . GVn are assigned to the total gate series resistor GGVn. With the aid of the switches S1, S2, S3 . . . Sn, the gate series resistors GV1 . . . GVn can be interconnected or combined in any desired way, thus ultimately resulting in a total gate series resistor GGVn having a value corresponding to the setpoint value, that is to say a resistance value corresponding to the setpoint value. FIG. 2 only illustrates a parallel connection of the gate series resistors, but a series connection or a combination of series and parallel connection can also be used as necessary. By controlling the switches S1 . . . Sn, it is thus possible to configure total gate series resistors GGVn with any desired setpoint value. In this case, the control of the switches S1 . . . Sn can be carried out in particular by the control device. A corresponding connection from the control device to the switches S1 . . . Sn is not included in the drawing, for reasons of clarity, but is of course provided. Depending on the operating condition of the power switch LHn, that is to say in particular depending on the temperature Tn and/or the current In, the control device SG ascertains a setpoint value for the total gate series resistor GGVn. From the provided multiplicity of gate series resistors, by means of selection via the switches S1 . . . Sn, a total gate series resistor GGVn is configured in a manner corresponding to the setpoint value. Operation of the power semiconductor switch LHn by the control device SG is thus carried out via the correspondingly set total gate series resistor GGVn.

[0046] FIG. 3 shows a method 200 for operating power semiconductor switches connected in parallel. The method starts in step 210. A setpoint value for a total gate series resistor GGVn for the at least one power semiconductor switch LHn is ascertained in step 220. In step 230, optionally, a multiplicity of gate series resistors GVn which can be assigned to the total gate series resistor GGVn are provided and a selection of the gate series resistors GVn is selected depending on the setpoint value ascertained. In step 240, the total gate series resistor GGVn for the at least one power semiconductor switch LHn is formed depending on the respective setpoint value, in particular by interconnection of the selection of the gate series resistors GVn. In step 250, the at least one power semiconductor switch is operated with the associated total gate series resistor GGVn. The method ends in step 260.