METHOD FOR GENERATING AN ALTERNATING ELECTRIC CURRENT

Abstract

A method for generating an alternating electric current is provided. In the method, multiple partial currents are generated and superimposed into a total current. Each of the partial currents is generated using a modulation method. The modulation method uses a tolerance band method having tolerance limits that are changeable.

Claims

1. A method for generating an alternating electric current, comprising: generating a plurality of partial currents; and superimposing the plurality of partial currents into a total current, wherein: each of the plurality of partial currents is generated using a modulation method, the modulation method uses a tolerance band method having tolerance limits, and the tolerance limits are changeable.

2. The method according to claim 1, wherein the tolerance limits are changed as a function of the generated total current.

3. The method according to claim 1, wherein the tolerance limits of the modulation method of a plurality of modulation methods form a tolerance band having an upper and a lower tolerance limit, and the method further comprises at least one of: changing the upper and lower tolerance limits independently of each other, and shifting the tolerance band while retaining a constant distance between the lower and upper tolerance limits.

4. The method according to claim 1, wherein the tolerance limits are selected such that the total current lies within a predefined tolerance limit.

5. The method according to claim 1, further comprising: measuring the partial currents and the total current for setting the tolerance limits.

6. The method according to claim 1, further comprising: transforming the partial currents and the total current into a shared coordinate system in which compliance limits are predefined such that the total current lies within a predefined tolerance limit.

7. The method according to claim 6, wherein the shared coordinate system is a rotating coordinate system.

8. A feed-in device for feeding in electric current into an electric power supply network, comprising a plurality of inverters having a plurality of partial current outputs, respectively, each inverter of the plurality of inverters generating a respective partial current of a plurality of partial currents at a respective partial current output and an inverter of the plurality of inverters generating the respective partial current using a modulation method; and a sum current output for summing up the plurality of partial currents to a total current, wherein the plurality of partial current outputs are connected to the sum current output at a summing node.

9. The feed-in device according to claim 8, wherein the plurality of inverters are connected in parallel and include a line reactor at each of their partial current outputs.

10. The feed-in device according to claim 8 wherein the plurality of inverters operate using a line reactor at each of their current outputs without an additional output filter or without an additional line reactor at the sum current output.

11. The feed-in device according to claim 8, further comprising: a plurality of first measuring means at the plurality of partial current outputs, respectively, for measuring the plurality of partial current; and a measuring means at the sum current output for measuring the total current.

12. The feed-in device according to claim 8 wherein one or more of the plurality of inverters are galvanically decoupled on at least one of an input side and an output side.

13. A wind turbine for generating and feeding the electric current into the electric power supply network, the wind turbine comprising: a rotor; a generator; and the feed-in device according to claim 8.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0032] The present invention will be described in greater detail below by way of example on the basis of specific embodiments, with reference to the accompanying figures.

[0033] FIG. 1 shows a wind turbine in a perspective view.

[0034] FIG. 2 schematically depicts an interconnection of multiple inverters for generating a total current.

[0035] FIG. 3 illustrates a tolerance band method.

[0036] FIG. 4 shows a schematic structure for explaining a portion of a control method according to one embodiment.

DETAILED DESCRIPTION

[0037] FIG. 1 shows a wind turbine 100 including a tower 102 and a nacelle 104. A rotor 106 having three rotor blades 108 and a spinner 110 is situated on the nacelle 104. During operation, the wind causes the rotor 106 to rotate, thus driving a generator in the nacelle 104.

[0038] The circuit configuration according to FIG. 2 illustrates a feed-in device 1 and shows three inverters 2 which exemplify additional inverters. In this respect, these three inverters 2 also generate the partial currents i.sub.1, i.sub.2 and i.sub.n. The inverters 2 each have a DC voltage input 4, which may also be referred to as a DC input. The inverters 2 receive their input power via this DC input 4. These DC inputs 4 of the inverters 2 are coupled via a DC bus 6. However, according to one embodiment, it is also provided that these DC inputs 4 are not coupled, but are each connected to a separate DC source 8. FIG. 2 shows both of these options. A separation of the DC inputs 4 so that each DC input 4 is able to have a separate DC source 8 may, for example, be designed in such a way that one generator, in particular of a wind turbine, feeds separate DC sources 8. The inverters 2 now generate the output currents i.sub.1, i.sub.2 and i.sub.n at their outputs, each being referred to as a partial current output 10. The output of each inverter also includes an output inductor 12. After each output inductor, it is indicated that each inverter 2 generates a three-phase current. Thus, it is also to be inferred from FIG. 2 that this output inductor 12 may be sufficient at every partial current output 10 in the provided method. An otherwise common filter, in particular an LCL filter, is not required. The partial output currents i.sub.1, i.sub.2 and i.sub.n are superimposed at a summing node 14, i.e., added up, and routed to the sum current output 16 as the total current i.sub.G. The sum current output has a shared network inductor 18 which, however, may also be dispensable. The total current i.sub.G may then be fed in via a transformer 20 into the electric power supply network 22.

[0039] The additional functionality will now be explained by considering the currents. It is to be noted that both the partial currents at the output of each inverter 2 and the total output current at the sum current output 16 are three-phase. However, each of the additional explanations deals with only one phase of these three-phase currents. Thus, only one phase is considered, and the other phases function in the same manner.

[0040] In FIG. 2, it is now apparent that there is measuring means, which is a current sensor 24 for each partial current i.sub.1, i.sub.2 and i.sub.n. A current sensor 26 for the total current i.sub.G is also provided.

[0041] Each inverter 2 now uses a measured value of its partial current, i.e., i.sub.1, i.sub.2 or i.sub.n, and also uses the measured value of the total current i.sub.G. The total current i.sub.G thus flows into each of the inverters 2. Each inverter then sets the corresponding tolerance band or the corresponding tolerance limits of the tolerance band as a function of the total current i.sub.G, and then controls the corresponding semiconductor switches as a function of its partial current, in order to modulate a corresponding current.

[0042] Thus, the currents i.sub.1, i.sub.2 and i.sub.n are then generated, which already have an advantageous, low-oscillation state due to the type of their circuit and due to the output inductor 12, and are then superimposed at the summing node 14. The result is the total current i.sub.G, whose measured value is fed back to each of the inverters 2, as described.

[0043] FIG. 3 illustrates an optimal sinusoidal curve 30 for a tolerance band method, about which a tolerance band having an upper tolerance limit T.sub.1 and a lower tolerance limit T.sub.2 is placed. For purposes of illustration, this tolerance band is depicted as being very wide, and would in reality of course be much narrower.

[0044] The generated current i.sub.1, which is used here by way of example, lies in this tolerance band between the limits T.sub.1 and T.sub.2.

[0045] The current is generated by closing a switch for generating a positive pulse. As long as this positive pulse is applied, the current increases, and as soon as it has reached the upper limit T.sub.1, the corresponding switch is reopened and the pulse is terminated. The current then decreases until it has reached the lower limit T.sub.2, so that the aforementioned switch is then closed again, in order to explain the process graphically in a simplified manner.

[0046] FIG. 3 shows a tolerance band in which the optimal sinusoid 30 lies in the center, i.e., has equally large distances from the upper and lower limits T.sub.1 and T.sub.2. In order, for example, to take into consideration or to counteract a high total current, the upper limit T.sub.1 may be shifted downward so that it approaches the optimal sinusoid 30. The lower limit T.sub.2 may also be shifted downward, or it remains unchanged.

[0047] However, after such a shift of the tolerance band, i.e., the shifting of the upper limit T.sub.1 described by way of example, the basic tolerance band method otherwise continues to run unchanged for the partial current i.sub.1 shown by way of example in FIG. 3. Furthermore, the method thus tests whether the rising edge of the current has reached the upper tolerance limit T.sub.1, which now, however, lies elsewhere, or whether its falling edge has reached the lower tolerance limit T.sub.2.

[0048] The method is depicted in FIG. 4 in a schematic structure which illustrates a feed-in device 41 or depicts it in a simplified manner. The actual generation of the partial current i.sub.1 takes place in the inverter 42, which schematically indicates a DC link circuit 44 here. The two switches S.sub.1 and S.sub.2, which are situated between the positive and negative nodes, generate a voltage pulse pattern, so that the partial current i.sub.1 at the partial current output 50 also results due to the output inductor 52. This partial current i.sub.1 sums with various other partial currents i.sub.2 to i.sub.n up to the total current i.sub.G. A network inductor 58 may be provided for the total current i.sub.G; however, the network inductor 58 may also be dispensable.

[0049] This total current i.sub.G is measured using a total current meter 66 and input to a tolerance block 70. The tolerance block 70 may then predefine or change the specific upper tolerance limit T.sub.1 and the lower tolerance limit T.sub.2 for the total current, which were illustrated in FIG. 3, as a function of the total current and as a function of tolerance limits T.sub.G1 and T.sub.G2. These upper and lower tolerance limits T.sub.1 and T.sub.2 are then input into the control unit 72. In addition, the control unit 72 receives the instantaneous partial current i.sub.1 and then functions as illustrated in FIG. 3. Depending on the position of the partial current i.sub.1 in the tolerance band which is determined via the upper and lower tolerance limits T.sub.1 and T.sub.2, switching signals S are then generated which may be provided to the inverter 42. The inverter 42 then correspondingly switches the switches S.sub.1 and S.sub.2. In particular for a positive pulse, the switch S.sub.1 is closed and the switch S.sub.2 is opened, and for the end of a positive pulse, or for a negative pulse, the switch S.sub.2 is closed and the switch S.sub.1 is opened.

[0050] A partial current i.sub.1 then results, which is again fed back for the next calculation. A new value for the total current i.sub.G also results, i.e., together with the additional currents i.sub.2 to i.sub.n, and this value of the total current i.sub.G is also fed back as described above.

[0051] In addition to this basic schematic description, particularly with respect to FIGS. 3 and 4, it may also be provided to transform the tolerance range, in particular an established tolerance range for the total current i.sub.G, i.e., the tolerance limits T.sub.G1 and T.sub.G2 illustrated in FIG. 4, into suitable coordinates, in order to be able to be able to check the compliance via the total current in a better manner and/or to be able to derive better responses, in particular the change in the upper and lower tolerance limits T.sub.1 and T.sub.2. Correspondingly, a method is provided which comply with this tolerance range for the total current.

[0052] Therefore, the case is considered in which multiple power electronics systems are operated together, i.e., connected in series and/or in parallel, and controlled independently of each other with the aid of approximated sliding-mode controllers, which may also be referred to as tolerance band controllers or which may include such controllers. The sliding-mode controllers may, for example, be designed as hysteresis controllers. It may then be mostly ensured that the control deviation of the sliding function remains within certain tolerance bands for each subsystem.

[0053] However, since there is no synchronization of the switching actions in the individual subsystems, it may happen that the control deviation of interconnected systems simultaneously deviates in the same direction, so that a disadvantageous superimposition results. For this problem, a solution as described above is provided.

[0054] In order also to influence the superimposition of current or voltage ripples in a targeted manner, methods are generally used in practice which utilize a pulse-width modulation or a space-vector modulation. In this method, the switching frequency is generally fixed and the switching time points of interconnected systems are offset in a targeted manner, in order to achieve a desired superimposition of the current or voltage ripple.

[0055] One disadvantage of this approach is that it is necessary to forgo the advantages which are inherent in the sliding-mode controllers, i.e., in particular the characteristic in which certain interference is strongly suppressed.

[0056] Interconnected power electronics systems are operated in an approximated sliding mode in such a way that compliance with an established tolerance range is ensured whenever possible. By selecting the tolerance range in a suitable manner, a disadvantageous superimposition of harmonics in the sense of the above descriptions may be prevented or greatly reduced.