Method for Serially Transmitting a Frame from a Transmitter to at Least One Receiver via a Bus System, and a Subscriber Station for a Bus System
20170289321 · 2017-10-05
Inventors
- Florian Hartwich (Reutlingen, DE)
- Martin Heinebrodt (Stuttgart, DE)
- Christian Horst (Dusslingen, DE)
- Thomas Lindenkreuz (Reutlingen, DE)
- Peter Svejkovsy (Renningen, DE)
- Arthur Mutter (Neuhausen, DE)
Cpc classification
H04L1/0008
ELECTRICITY
H04L1/0091
ELECTRICITY
H04L1/0083
ELECTRICITY
International classification
H04L1/00
ELECTRICITY
Abstract
The disclosure relates to a method for serially transmitting a frame from a transmitter to at least one receiver via a bus line, as well as a subscriber station for a bus system. According to said method, stuff bits for generating additional signal edges are inserted into the frame by the transmitter according to a predetermined rule, and the stuff bits are removed again by the receiver when evaluating a received frame, a CRC calculation logic of a CRC generator calculating a CRC checksum that is comprised by said frame, and a value of “1” being inserted into said CRC calculation logic in an additional evaluation step if a value of “0 . . . 0” has been determined for the CRC checksum in the running calculation executed by the CRC calculation logic.
Claims
1. A method for serial transmission of a frame, the method comprising: transmitting the frame from the from a transmitter to a receiver via a bus line; inserting, before the transmitting, stuff bits into the frame with the transmitter according to a predetermined rule to generate additional signal edges; removing, after the transmitting, the stuff bits with the receiver in an evaluation of the frame; calculating a CRC checksum with a CRC calculation logic of a CRC generator, the frame including the CRC checksum; and inserting a value “1” into the CRC calculation logic in an additional evaluation step in response to a value of “0 . . . 0” being found for the CRC checksum in the calculating carried out by the CRC calculation logic.
2. The method as claimed in claim 1, wherein the additional evaluation step is carried out before an evaluation of a next transmitted bit.
3. The method as claimed in claim 1, wherein an initialization vector of the CRC checksum has a value “1 . . . 0”.
4. The method as claimed in claim 1, wherein at least one of: the frame includes a header part, a data part, and an end part; and the frame includes a header part having an identifier.
5. The method as claimed in claim 1, wherein the frame is one of a CAN frame, a TTCAN frame, and a CAN FD frame.
6. A subscriber station for a bus system, the subscriber station comprising: a transmitting/receiving device configured to at least one of (i) transmit a frame to and (ii) receive the frame from a further subscriber station of the bus system via a bus line; and a verifying device configured to verify a CRC checksum of the frame, which is calculated by a CRC calculation logic of a CRC generator, wherein the transmitting/receiving device is configured to at least one of (i) before transmitting the frame, insert stuff bits into the frame according to a predetermined rule to generate additional signal edges, and (ii) remove the stuff bits from the frame when evaluating the received frame, wherein the verifying device is configured to insert a value “1” into the CRC calculation logic in an additional evaluation step in response to a value of “0 . . . 0” being found for the CRC checksum in the calculating carried out by the CRC calculation logic.
7. A bus system comprising: a bus line; and at least two subscriber stations configured to be connected to one another via the bus line such that they can communicate with one another, at least one of the at least two subscriber stations comprising: a transmitting/receiving device configured to at least one of (i) transmit a frame to and (ii) receive the a frame from a further subscriber station of the at least two subscriber stations via the bus line; and a verifying device configured to verify a CRC checksum of the frame, which is calculated by a CRC calculation logic of a CRC generator, wherein the transmitting/receiving device is configured to at least one of (i) before transmitting the frame, insert stuff bits into the transmitted frame according to a predetermined rule to generate additional signal edges, and (ii) remove the stuff bits from the frame when evaluating the received frame, wherein the verifying device is configured to insert a value “1” into the CRC calculation logic in an additional evaluation step in response to a value of “0 . . . 0” being found for the CRC checksum in the calculating carried out by the CRC calculation logic.
Description
DRAWINGS
[0033] The invention is described in more detail below on the basis of exemplary embodiments and with reference to the accompanying drawing, in which:
[0034]
[0035]
[0036]
[0037]
[0038] Unless otherwise stated, in the figures elements that are the same or functionally the same are provided with the same reference signs.
First Exemplary Embodiment
[0039]
[0040] In
[0041] As shown in
[0042] The communication control devices 11, 21, 31 respectively serve for controlling a communication of the respective subscriber station 10, 20, 30 via the bus line 3 with another subscriber station of the subscriber stations 10, 20, 30 connected to the bus line 3. The communication control devices 11, 21, 31 may be respectively configured like a conventional CAN or TTCAN or CAN FD controller. The communication control devices 11, 21, 31 may also be respectively formed as part of a microcontroller, which is likewise comprised by the respective subscriber station 10, 20, 30.
[0043] The transmitting/receiving devices 13, 23, 33 may be respectively configured like a conventional CAN or TTCAN or CAN FD transceiver.
[0044] The verifying devices 12, 22, 32 may also be configured as software modules, which form part of the software running on the subscriber station. In this case, the method according to the present invention is fully implemented in software.
[0045]
[0046] In
[0047]
[0048] In
[0049] In
[0050] As shown in
[0051]
[0052]
[0053] As shown in
[0054]
[0055] For CAN FD frames 60, 600 in the base format, which are shown in
[0056]
[0057] Shown in
[0058] Accordingly, the receiving signal RX-20 corresponding to the transmitting signal TX-10 is obtained with a delay (not represented), which is caused by the transmission of the transmitting signal TX-10 via the bus line 3. This receiving signal RX-20 may for various reasons (hardware errors, external disturbances, electromagnetic radiation, etc.) have a recessive level for a time period T, although the transmitting signal has a dominant level of the SOF bit. In the thus-falsified receiving signal RX-20 there may additionally be short disturbance pulses G, which falsify the bus signal 35 further, as shown in
[0059] On account of the falsified receiving signal RX-20, the subscriber station. 20 sees the signal. V-20. After the bit boundary 50 for the SOF bit there follows a sync_seg phase, provided with the reference sign 54. This is followed by a transmission phase prop_seg, which is provided in
[0060] The subscriber station 20 samples the receiving signal RX-20 at sample points SP1, SP2, SP3, SP4, SP5. The sample points SP1 to SP5 lie between the phase_seg1, provided with the reference sign 56, and the phase_seg2, provided with the reference sign 57.
[0061] In the case shown in
[0062] In the case of the present exemplary embodiment, to solve the problem described above, for CRC-17 and CRC-21 the initialization vector “1 . . . 0” may be used instead of “0 . . . 0” as the initialization vector of the CRC generator 13A, 23A, 33A. The initialization may be performed with the verifying devices 12, 22, 32, in the case of the verifying device 22 in particular with the CRC evaluation unit 22A and the insertion unit 22B. As a result, the problems with respect to the two critical values of the identifier bits ID28 to ID25 of “0000” and “0001” can no longer occur.
[0063] As a supplementary or alternative solution to the problem being considered, the following procedure is adopted.
[0064] If a CRC value of “0 . . . 0” is sensed, a “1” is inserted into the CRC logic in an additional evaluation of the CRC mechanism. This is performed before the evaluation of the next received/sent bit.
[0065] In other words, the CRC calculation logic concerned of the CRC generator 13A, 23A, 33A calculates the CRC checksum. If in the continuous calculation carried out by the CRC calculation logic of the CRC generator 13A, 23A, 33A, with the associated verifying device 12, 22, 32, a CRC value of “0 . . . 0” is found, a value “1” is inserted into the CRC calculation logic in an additional evaluation step. In the case of the subscriber station 20, the checking of the CRC value that finds “0 . . . 0” may be carried out with the CRC evaluation unit 22A. The insertion of the value “1” into the CRC calculation logic may be carried out with the insertion unit 223.
[0066] This inserted “1” may be regarded as a virtual stuff bit, which is only visible to the CRC logic. On account of this insertion, the CRC value is no longer “0 . . . 0” when the next received/sent bit arrives.
Second Exemplary Embodiment
[0067] In the case of a second exemplary embodiment, the bus system 1 is constructed in the same way as described in the case of the first exemplary embodiment. As a difference from the latter, however, the second exemplary embodiment is concerned with the problem that can arise if within a CAN FD frame a recessive bit after a series of four sent dominant bits is misinterpreted by the receiver as a stuff bit because of a shortening of a bit or a shift in the synchronization of the subscribers and at the same time the interim CRC register value is coincidentally equal to “0 . . . 0”. The interim CRC register value of the CRC generator 13A, 23A, 33A is equal to “0 . . . 0” it the continuously carried out calculation of the CRC checksum gives the value “0 . . . 0”.
[0068] A distinction should be made between two cases:
[0069] Case 2a occurs if the interim CRC register value is equal to “0 . . . 0”, while a stuffed sequence of “0”s is sent and the first of these “0” hits is shortened by synchronization. Accordingly, a bit sequence of “00000I” (“I” stands here for a sent stuff bit) is sampled here by the receiver in a falsified form as “00001”. This error is not sensed by the CRC.
[0070] Case 2b occurs if the interim CRC register value is equal to “0 . . . 0”, while a non-stuffed sequence “00001” is sent and the receiver samples an additional “0”. Then, the “1” is interpreted as a stuffing “1” and accordingly the sent bit sequence of “00001” is sampled by the receiver in a falsified form as “00000I (“I” stands here for a received—presumed—stuffing bit). This insertion is not sensed by the CRC.
[0071] The problem may occur at any bit position between the Start of Frame and the sent CRC checksum. With the initialization vector “1 . . . 0”, which is described in the case of the first exemplary embodiment, an interim CRC register value equal to “0 . . . 0” cannot occur for the first 18 sent bits.
[0072] As a solution to the problem considered in the case of the second exemplary embodiment, the following procedure is adopted.
[0073] If a CRC value of “0 . . . 0” is sensed, a “1” is inserted into the CRC logic in an additional evaluation of the CRC mechanism. This is performed before the evaluation of the next received/sent bit.
[0074] In other words, the CRC calculation logic concerned of the CRC generator 13A, 23A, 33A calculates the CRC checksum. If in the continuous calculation carried out by the CRC calculation logic of the CRC generator 13A, 23A, 33A, with the associated verifying device 12, 22, 32, a CRC value of “0 . . . 0” is found, a value “1” is inserted into the CRC calculation logic in an additional evaluation step. In the case of the subscriber station 20, the checking of the CRC value that finds “0 . . . 0” may be carried out with the CRC evaluation unit 22A. The insertion of the value “1” into the CRC calculation logic may be carried out with the insertion unit 22B.
[0075] This inserted “1” may be regarded as a virtual stuff bit, which is only visible to the CRC logic.
[0076] On account of this insertion, the CRC value is no longer “0 . . . 0” when the next received/sent bit arrives.
[0077] All of the refinements described above of the bus system 1, the subscriber stations 10, 20, 30 and the method may be used individually or in all possible combinations. In particular, all of the features of the previously described exemplary embodiments may be combined as desired or be omitted. In addition, the following modifications are conceivable in particular.
[0078] The bus system 1 according to the exemplary embodiments that is described above is described on the basis of a bus system based on the CAN FD protocol. The bus system 1 according to the exemplary embodiments may however also be another kind of communication network. It is advantageous, but not an absolute prerequisite, that with the bus system 1 exclusive, collision-free access of a subscriber station 10, 20, 30 to a common channel is ensured, at least for certain time periods.
[0079] There may be any desired number and arrangement of the subscriber stations 10 to 30 in the bus system 1 of the exemplary embodiments and any desired modifications thereof. In particular, there may also only be subscriber stations 10 or 20 or 30 in the bus system 1. Any desired combinations of the subscriber stations 10 to 30 in the bus systems 1 are possible.
[0080] Instead of the way in which they are configured that is shown in