LIQUID CRYSTAL DISPLAY DEVICE

Abstract

A first substrate (10) in a liquid crystal display device (100) includes a first electrode (11) provided in each pixel and a second electrode (12) generating a lateral electric field in a liquid crystal layer (30) together with the first electrode. A second substrate (20) includes a third electrode (21) generating a vertical electric field in the liquid crystal layer together with the first electrode and the second electrode. Each pixel exhibits, in a switched manner, a black display state where black display is provided in a state where the vertical electric field is generated in the liquid crystal layer, a white display state where white display is provided in a state where the lateral electric field is generated in the liquid crystal layer, and a transparent display state where a rear side of a liquid crystal display panel (1) is seen through in a state where no voltage is applied to the liquid crystal layer. A potential difference between the first electrode and the second electrode at each gray scale level from a lowest level to a highest level is 60% or less of a potential difference between the second electrode and the third electrode in the black display state.

Claims

1. A liquid crystal display device, comprising: a liquid crystal display panel including a first substrate and a second substrate facing each other, and a liquid crystal layer provided between the first substrate and the second substrate; the liquid crystal display device including a plurality of pixels arrayed in a matrix; wherein: the first substrate includes a first electrode provided in each of the plurality of pixels and a second electrode provided below the first electrode with an insulating layer being provided between the first electrode and the second electrode, the second electrode generating a lateral electric field in the liquid crystal layer together with the first electrode; the second substrate includes a third electrode provided to face the first electrode and the second electrode, the third electrode generating a vertical electric field in the liquid crystal layer together with the first electrode and the second electrode; the plurality of pixels each exhibit, in a switched manner, a black display state where black display is provided in a state where the vertical electric field is generated in the liquid crystal layer, a white display state where white display is provided in a state where the lateral electric field is generated in the liquid crystal layer, and a transparent display state where a rear side of the liquid crystal display panel is seen through in a state where no voltage is applied to the liquid crystal layer; and a potential difference between the first electrode and the second electrode at each gray scale level from a lowest level to a highest level is 60% or less of a potential difference between the second electrode and the third electrode in the black display state.

2. The liquid crystal display device according to claim 1, wherein the potential difference between the first electrode and the second electrode at each gray scale level from the lowest level to the highest level is 54% or less of the potential difference between the second electrode and the third electrode in the black display state.

3. The liquid crystal display device according to claim 1, wherein the potential difference between the first electrode and the second electrode at each gray scale level from the lowest level to the highest level is 47% or less of the potential difference between the second electrode and the third electrode in the black display state.

4. The liquid crystal display device according to claim 1, wherein at a gray scale level, among all the gray scale levels from the lowest level to the highest level, at which the potential difference between the first electrode and the second electrode is maximum, the potential difference between the first electrode and the second electrode is 30% or greater of the potential difference between the second electrode and the third electrode in the black display state.

5. The liquid crystal display device according to claim 1, wherein: a voltage applied to the first electrode is decreased as the gray scale level is increased from the lowest level to a level corresponding to the white display state; and a voltage applied to the second electrode is kept the same as the gray scale level is increased from the lowest level to a halftone level, and is decreased as the gray scale level is increased from the halftone level to the level corresponding to the white display state.

6. The liquid crystal display device according to claim 1, wherein liquid crystal molecules in the liquid crystal layer assume twisted alignment in the transparent display state.

7. The liquid crystal display device according to claim 6, wherein: the first electrode includes a plurality of slits extending in a predetermined direction; and in the white display state and the transparent display state, liquid crystal molecules at, and in the vicinity of, a central portion of the liquid crystal layer in a thickness direction are aligned to be generally perpendicular to the predetermined direction.

8. The liquid crystal display device according to claim 1, wherein the liquid crystal layer contains liquid crystal molecules having positive dielectric anisotropy.

9. The liquid crystal display device according to claim 1, further comprising an illumination element directing light of a plurality of colors including red light, green light and blue light in a switched manner toward the liquid crystal display panel.

10. The liquid crystal display device according to claim 1, wherein the liquid crystal display device provides color display in a field sequential system.

11. The liquid crystal display device according to claim 1, wherein the liquid crystal display panel does not include a color filter.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0024] FIG. 1 is a cross-sectional view schematically showing a liquid crystal display device 100 in an embodiment according to the present invention.

[0025] FIG. 2 is a plan view schematically showing the liquid crystal display device 100 in the embodiment according to the present invention.

[0026] FIG. 3 is a plan view showing an example of specific line structure of a rear substrate 10 in the liquid crystal display device 100.

[0027] FIG. 4(a) and FIG. 4(b) are respectively a cross-sectional view and a plan view showing an alignment state of liquid crystal molecules 31 in a black display state of the liquid crystal display device 100.

[0028] FIG. 5(a) and FIG. 5(b) are respectively a cross-sectional view and a plan view showing an alignment state of the liquid crystal molecules 31 in a white display state of the liquid crystal display device 100.

[0029] FIG. 6(a) and FIG. 6(b) are respectively a cross-sectional view and a plan view showing an alignment state of the liquid crystal molecules 31 in a transparent display state of the liquid crystal display device 100.

[0030] FIG. 7 is a cross-sectional view showing an alignment state of the liquid crystal molecules 31 in a halftone display state of the liquid crystal display device 100.

[0031] FIG. 8 provides cross-sectional views schematically showing a liquid crystal display device 800 in a comparative example; FIG. 8(a) shows a black display state, and FIG. 8(b) shows a white display state.

[0032] FIG. 9 schematically shows that the display is blurred (visually recognized double).

[0033] FIG. 10 is a graph showing an example of voltage settings (relationship between an upper voltage/a lower voltage and the gray scale level) at which abnormal alignment change occurs at the time of gray scale level transition.

[0034] FIG. 11 schematically shows an alignment change from the black display state via the halftone display state to the white display state in the case where the voltage settings shown in FIG. 10 are adopted.

[0035] FIG. 12 schematically shows an alignment change from the white display state via the halftone display state to the black display state in the case where the voltage settings shown in FIG. 10 are adopted.

[0036] FIG. 13(a) and FIG. 13(b) are each a graph provided to describe a mechanism by which the abnormal alignment change occurs.

[0037] FIG. 14 is a graph showing an example of settings of the upper voltage and the lower voltage in the liquid crystal display device 100.

[0038] FIG. 15 is a graph showing response waveforms (time vs. brightness relationships) of rise response.

[0039] FIG. 16 is a graph showing waveform integrated values in a second half of period P1 shown in FIGS. 15 (132.1 to 134.2 ms).

[0040] FIG. 17 is a graph showing response waveforms (time vs. brightness relationships) of decay response.

[0041] FIG. 18 is a graph showing waveform integrated values in a second half of period P2 shown in FIGS. 17 (162.1 to 164.2 ms).

[0042] FIG. 19 is a graph showing another example of settings of the upper voltage and the lower voltage in the liquid crystal display device 100.

[0043] FIG. 20 is a graph showing still another example of settings of the upper voltage and the lower voltage in the liquid crystal display device 100.

[0044] FIG. 21 is a cross-sectional view schematically showing another liquid crystal display device 100′ in an embodiment according to the present invention.

[0045] FIG. 22 is a plan view schematically showing the another liquid crystal display device 100′ in the embodiment according to the present invention.

[0046] FIG. 23(a) and FIG. 23(b) are respectively a cross-sectional view and a plan view showing an alignment state of liquid crystal molecules 31 in a black display state of the liquid crystal display device 100′.

[0047] FIG. 24(a) and FIG. 24(b) are respectively a cross-sectional view and a plan view showing an alignment state of the liquid crystal molecules 31 in a white display state of the liquid crystal display device 100′.

[0048] FIG. 25(a) and FIG. 25(b) are respectively a cross-sectional view and a plan view showing an alignment state of the liquid crystal molecules 31 in a transparent display state of the liquid crystal display device 100′.

[0049] FIG. 26(a) and FIG. 26(b) are respectively an isometric view and a cross-sectional view schematically showing another structure of the liquid crystal display device 100.

DESCRIPTION OF EMBODIMENTS

[0050] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention is not limited to any of the following embodiments.

[0051] With reference to FIG. 1 and FIG. 2, a liquid crystal display device 100 in this embodiment will be described. FIG. 1 is a cross-sectional view schematically showing the liquid crystal display device 100, and FIG. 2 is a plan view schematically showing the liquid crystal display device 100.

[0052] As shown in FIG. 1, the liquid crystal display device 100 includes a liquid crystal display panel 1 and an illumination element 2. The liquid crystal display device 100 includes a plurality of pixels arrayed in a matrix. As described below, the liquid crystal display device 100 provides color display in a field sequential system.

[0053] The liquid crystal display panel 1 includes a first substrate 10 and a second substrate 20 facing each other, and a liquid crystal layer 30 provided between the first substrate 10 and the second substrate 20. Among the first substrate 10 and the second substrate 20, the first substrate 10 located relatively on a rear side will be referred to as a “rear substrate”, and the second substrate 20 located relatively on a front side will be referred to as a “front substrate”.

[0054] The rear substrate 10 includes a first electrode 11 provided in each of the plurality of pixels, and a second electrode 12 generating a lateral electric field in the liquid crystal layer 30 together with the first electrode 11. The first electrode 11 is located above the second electrode 12 with an insulating layer 13 being provided therebetween. In other words, the second electrode 12 is located below the first electrode 11 with the insulating layer 13 being provided therebetween. In the following description, among the first electrode 11 and the second electrode 12, the first electrode 11 located relatively on the upper side will be referred to as an “upper electrode” and the second electrode 12 located relatively on the lower side will be referred to as a “lower electrode”. The lower electrode 12, the insulating layer 13 and the upper electrode 11 are supported by a transparent substrate (e.g., glass substrate) 10a having an insulating property.

[0055] As shown in FIG. 1 and FIG. 2, the upper electrode 11 includes a plurality of slits 11a extending in a predetermined direction D and a plurality of branched portions 11b(comb teeth) extending parallel to the direction D in which the slits 11a extend (hereinafter, the direction D will also be referred to as a “slit direction”). The number of the slits 11a and the branched portions 11b are not limited to those shown in FIG. 1 and FIG. 2. There is no specific limitation on width S of each of the slits 11a. The width S of each slit 11a is typically 2 μm or greater and 10 μm or less. There is no specific limitation either on width L of each of the branched portions 11b. The width L of each branched portion 11b is typically 2 μm or greater and 10 μm or less. The upper electrode 11 is formed of a transparent conductive material (e.g., ITO).

[0056] The lower electrode 12 does not include any slit. Namely, the lower electrode 12 is a so-called solid electrode. The lower electrode 12 is formed of a transparent conductive material (e.g., ITO).

[0057] There is no specific limitation on the material of the insulating layer 13. The insulating layer 13 may be formed of, for example, an inorganic material such as silicon oxide (SiO.sub.2), silicon nitride (SiN.sub.x) or the like or an organic material such as a photosensitive resin or the like.

[0058] The front substrate 20 includes a third electrode 21 provided to face the upper electrode (first electrode) 11 and the lower electrode (second electrode) 12 (hereinafter, the third electrode will be referred to as a “counter electrode”). The counter electrode 21 is supported by a transparent substrate (e.g., glass substrate) 20a having an insulating property.

[0059] The counter electrode 21 generates a vertical electric field in the liquid crystal layer 30 together with the upper electrode 11 and the lower electrode 12. The counter electrode 21 is formed of a transparent conductive material (e.g., ITO).

[0060] Although not shown in FIG. 1, a dielectric layer (overcoat layer) may be formed on the counter electrode 21. The overcoat layer is provided to weaken the vertical electric field unavoidably generated when the lateral electric field is generated. The overcoat layer is formed of, for example, a photosensitive resin.

[0061] The liquid crystal layer 30 contains liquid crystal molecules 31 having positive dielectric anisotropy. Namely, the liquid crystal layer 30 is formed of a positive liquid crystal material. In FIG. 1 and FIG. 2, the liquid crystal molecules 31 are aligned in the state where no voltage is applied to the liquid crystal layer 30.

[0062] The liquid crystal display panel 1 further includes a pair of horizontal alignment films 14 and 24 provided to face each other with the liquid crystal layer 30 being provided therebetween. One of the pair of horizontal alignment films 14 and 24, specifically, the horizontal alignment film 14 (hereinafter, may be referred to as a “first horizontal alignment film”), is formed on a surface of the rear substrate 10 on the side of the liquid crystal layer 30. The other of the pair of horizontal alignment films 14 and 24, specifically, the horizontal alignment film 24 (hereinafter, may be referred to as a “second horizontal alignment film”), is formed on a surface of the front substrate 20 on the side of the liquid crystal layer 30.

[0063] The first horizontal alignment film 14 and the second horizontal alignment film 24 are each alignment-processed and thus have an alignment control force that aligns the liquid crystal molecules 31 in the liquid crystal layer 30 in a predetermined direction (referred to as a “pretilt direction”). The alignment process may be, for example, a rubbing process or an optical alignment process.

[0064] The pretilt directions respectively controlled by the first horizontal alignment film 14 and the second horizontal alignment film 24 are set such that the liquid crystal molecules 31 assume twisted alignment in the state where no voltage is applied to the liquid crystal layer 30 (in the state where no electric field is generated). Specifically, the pretilt directions respectively controlled by the first horizontal alignment film 14 and the second horizontal alignment film 24 have an angle of about 45 degrees with respect to the slit direction D. The pretilt direction controlled by the second horizontal alignment film 24 has an angle of 90 degrees with respect to the pretilt direction controlled by the first horizontal alignment film 14. Therefore, in the state where no voltage is applied to the liquid crystal layer 30, the liquid crystal molecules 31 are twisted at 90 degrees.

[0065] The liquid crystal display panel 1 further includes a pair of polarization plates 15 and 25 provided to face each other with the liquid crystal layer 30 being provided therebetween. One of the pair of polarization plates 15 and 25, specifically, the polarization plate 15 (hereinafter, also referred to a “first polarization plate”), has a transmission axis (polarization axis) 15a, and the other of the pair of polarization plates 15 and 25, specifically, the polarization plate 25 (hereinafter, also referred to as a “second polarization plate”), has a transmission axis (polarization axis) 25a. As shown in FIG. 2, the transmission axes 15a and 25a are generally perpendicular to each other. Namely, the polarization plates 15 and 25 are located in a crossed-Nicols state. The transmission axis 15a of the first polarization plate 15 and the transmission axis 25a of the second polarization plate 25 are generally parallel or generally perpendicular to the pretilt directions respectively controlled by the first horizontal alignment film 14 and the second horizontal alignment film 24. Therefore, the transmission axis 15a of the first polarization plate 15 and the transmission axis 25a of the second polarization plate 25 each have an angle of about 45 degrees with respect to the slit direction D.

[0066] The illumination element (also referred to as a “backlight unit”) 2 is located on the rear side of the liquid crystal display panel 1. The illumination element 2 is capable of directing light of a plurality of colors including red light, green light and blue light in a switched manner toward the liquid crystal display panel 1.

[0067] The illumination element 2 may be, for example, of an edge light system as shown in FIG. 1. The illumination element 2 of the edge light system includes a light source unit 2a and a light guide plate 2b. The light source unit 2a may emit light of a plurality of colors including red light, green light and blue light. The light source unit 2a includes, for example, a red LED, a green LED and a blue LED. The light guide plate 2b guides the color light emitted from the light source unit 2a toward the liquid crystal display panel 1.

[0068] The liquid crystal display device 100 provides color display in the field sequential system. Therefore, the liquid crystal display panel 1 does not include any color filter.

[0069] When a predetermined voltage is applied between the upper electrode 11 and the lower electrode 12 (namely, when a predetermined potential difference between the upper electrode 11 and the lower electrode 12 is given), a lateral electric field (fringe field) is generated in the liquid crystal layer 30. The “lateral electric field” is an electric field including a component parallel to the substrate surface. The direction of the lateral electric field generated by the upper electrode 11 and the lower electrode 12 is generally perpendicular to the slit direction D.

[0070] By contrast, when a predetermined voltage is applied between the counter electrode 21 and the upper electrode 11/lower electrode 12 (namely, when a predetermined potential difference between the counter electrode 21 and the upper electrode 11/lower electrode 12 is given), a vertical electric field is generated. The “vertical electric field” is an electric field directed generally parallel to the normal to the substrate surface.

[0071] The liquid crystal display device 100 has a structure capable of controlling the strength of each of the lateral electric field and the vertical electric field for each of the pixels. Typically, the liquid crystal display device 100 has a structure capable of supplying a different voltage to each of the upper electrode 11 and the lower electrode 12 on a pixel-by-pixel basis. Specifically, the upper electrode 11 and the lower electrode 12 are both provided for each of the pixels, and each pixel includes a switching element (e.g., thin film transistor; not shown) electrically connected with the upper electrode 11 and a switching element (e.g., thin film transistor; not shown) electrically connected with the lower electrode 12. Predetermined voltages are respectively supplied to the upper electrode 11 and the lower electrode 12 via the corresponding switching elements. The counter electrode 21 is formed as a single continuous conductive film corresponding to all the pixels. Therefore, a common potential is applied to the counter electrode 21 in all the pixels.

[0072] FIG. 3 shows an example of specific line structure of the rear substrate 10. In the structure shown in FIG. 3, each pixel includes a first TFT 16A corresponding to the upper electrode 11 and a second TFT 16B corresponding to the lower electrode 12.

[0073] A gate electrode 16g of each of the first TFT 16A and the second TFT 16B is electrically connected with a gate bus line (scanning line) 17. A portion of the gate bus line 17 that overlaps a channel region of each of the first TFT 16A and the second TFT 16B acts as the gate electrodes 16g. Source electrodes 16s of the first TFT 16A and the second TFT 16B are electrically connected with source bus lines (signal line) 18 respectively. A portion branched from each of the source bus lines 18 acts as the source electrode 16s. A drain electrode 16d of the first TFT 16A is electrically connected with the upper electrode 11. By contrast, a drain electrode 16d of the second TFT 16B is electrically connected with the lower electrode 12. The line structure of the rear substrate 10 is not limited to that shown in FIG. 3.

[0074] In the liquid crystal display device 100 in this embodiment, each of the plurality of pixels may exhibit, in a switched manner, a “black display state” in which black display is provided in the state where a vertical electric field is generated in the liquid crystal layer 30, a “white display state” in which white display is provided in the state where a lateral electric field is generated in the liquid crystal layer 30, and a “transparent display state” in which the rear side of the liquid crystal display panel 1 (i.e., background) is seen through in the state where no voltage is applied to the liquid crystal layer 30.

[0075] Hereinafter, with reference to FIG. 4, FIG. 5 and FIG. 6, the black display state, the white display state and the transparent display state will be described in more detail.

[0076] FIG. 4 (a) and FIG. 4 (b) each show an alignment state of the liquid crystal molecules 31 in the black display state. In the black display state, a predetermined voltage is applied between the counter electrode 21 and the upper electrode 11/lower electrode 12 (for example, potentials of 7 V, 7.5 V and 0 V are given to the upper electrode 11, the lower electrode 12 and the counter electrode 21 respectively), and a vertical electric field is generated in the liquid crystal layer 30. FIG. 4(a) schematically shows lines of electric force in this state with dashed lines.

[0077] In the black display state, as shown in FIG. 4(a) and FIG. 4 (b), the liquid crystal molecules 31 in the liquid crystal layer 30 are aligned to be generally vertical to the substrate surface (surfaces of the rear substrate 10 and the front substrate 20) (namely, aligned to be generally parallel to the normal to the liquid crystal layer 30). The liquid crystal molecules 31 in the close vicinity of the first horizontal alignment film 14 and the second horizontal alignment film 24 are strongly influenced by the alignment control force of the first horizontal alignment film 14 and the second horizontal alignment film 24 and thus are kept aligned to be generally parallel to the substrate surface. However, such liquid crystal molecules 31 are generally parallel or generally perpendicular to the transmission axis 15a of the first polarization plate 15, and thus do not give phase difference almost at all to light incident on the liquid crystal layer 30 via the first polarization plate 15 and do not decrease the contrast ratio almost at all.

[0078] FIG. 5 (a) and FIG. 5 (b) each show an alignment state of the liquid crystal molecules 31 in the white display state. In the white display state, a predetermined voltage is applied between the upper electrode 11 and the lower electrode 12 (for example, potentials of 0 V, 7.5 V and 0 V are given to the upper electrode 11, the lower electrode 12 and the counter electrode 21 respectively), and a lateral electric field (fringe field) is generated in the liquid crystal layer 30. FIG. 5(a) schematically shows lines of electric force in this state with dashed lines.

[0079] In the white display state, as shown in FIG. 5(a) and FIG. 5(b), the liquid crystal molecules 31 in the liquid crystal layer 30 are aligned to be generally parallel to the substrate surface (namely, aligned to be generally vertical to the normal to the liquid crystal layer 30). More specifically, the liquid crystal molecules 31 in the vicinity of the first horizontal alignment film 14 and the liquid crystal molecules 31 in the vicinity of the second horizontal alignment film 24 are aligned to have an angle of about 90 degrees with respect to each other. As a result, the liquid crystal molecules 31 at, and in the vicinity of, a central portion of the liquid crystal layer 30 in a thickness direction are aligned to be generally perpendicular to the direction D in which the slits 11a of the upper electrode 11 extend (generally perpendicular in the slit direction D). Therefore, the average alignment direction of the bulk liquid crystal portion is generally perpendicular to the slit direction D (namely, has an angle of about 45 degrees with respect to the transmission axes 15a and 25a of the first polarization plate 15 and the second polarization plate 25).

[0080] FIG. 6(a) and FIG. 6(b) each show an alignment state of the liquid crystal molecules 31 in the transparent display state. In the transparent display state, no voltage is applied to the liquid crystal layer 30 (for example, a potential of 0 V is given to all of the upper electrode 11, the lower electrode 12 and the counter electrode 21), and neither a vertical electric field nor a lateral electric field is generated in the liquid crystal layer 30.

[0081] In the transparent display state, as shown in FIG. 6(a) and FIG. 6(b), the liquid crystal molecules 31 in the liquid crystal layer 30 assume twisted alignment. Namely, the liquid crystal molecules 31 are aligned to be generally parallel to the substrate surface (namely, generally vertical to the normal to the liquid crystal layer 30). The liquid crystal molecules 31 in the vicinity of the first horizontal alignment film 14 and the liquid crystal molecules 31 in the vicinity of the second horizontal alignment film 24 are aligned to have an angle of about 90 degrees with respect to each other. As a result, the liquid crystal molecules 31 at, and in the vicinity of, the central portion of the liquid crystal layer 30 in the thickness direction are aligned to be generally perpendicular to the slit direction D. Therefore, the average alignment direction of the bulk liquid crystal portion is generally perpendicular to the slit direction D (namely, has an angle of about 45 degrees with respect to the transmission axes 15a and 25a of the first polarization plate 15 and the second polarization plate 25). Each of the pixels in the liquid crystal display device 100 has a highest light transmittance in this transparent display state (namely, higher light transmittance than in the black display state or the white display state).

[0082] Each of the plurality of pixels in the liquid crystal display device 100 may exhibit a “halftone display state” in which display is provided at a luminance corresponding to a halftone as shown in FIG. 7, in addition to the black display state, the white display state and the transparent display state described above. In the halftone display state, a desired transmittance may be realized by adjusting the strength of the lateral electric field (fringe field) generated in the liquid crystal layer 30.

[0083] As described above, in the case where the liquid crystal display device 100 displays information displayed on the liquid crystal display panel 1 and the background in an overlapping manner, the pixels in a portion in the display region in which the information is to be displayed exhibit the black display state, the white display state or the halftone display state, and the pixels in the remaining portion exhibit the transparent display state. The display states are switched as follows, for example.

[0084] A driving circuit for a general liquid crystal display device includes an 8-bit driver IC, and generates an output voltage for 256 levels (levels 0 to 255). In a general liquid crystal display device, level 0 is assigned to the black display state, levels 1 through 254 are assigned to the halftone display state, and level 255 is assigned to the white display state.

[0085] In the liquid crystal display device 100 in this embodiment, for example, level 0 is assigned to the black display state, levels 1 through 253 are assigned to the halftone display state, level 254 is assigned to the white display state, and level 255 is assigned to the transparent display state. In this manner, the black display state, the halftone display state, the white display state and the transparent display state are switched to each other. It is not necessary that level 255 is assigned to the transparent display state. Any level may be assigned to the transparent display state. In a display system other than the above-described 256-level display system, a specific level may be assigned to the transparent display state.

[0086] As described above, the liquid crystal display device 100 in this embodiment provides color display in the field sequential system. Therefore, the liquid crystal display panel 1 does not need a color filter. This improves the light utilization factor. Also in the liquid crystal display device 100, a vertical electric field is generated in the liquid crystal layer 30 in the black display state and a lateral electric field is generated in the liquid crystal layer 30 in the white display state. Therefore, a torque by voltage application acts on liquid crystal molecules 31 in both of the fall (transition from the white display state to the black display state) and the rise (transition from the black display state to the white display state), and thus a high speed response characteristic is provided.

[0087] In the liquid crystal display device 100 in this embodiment, the pixels may each exhibit the transparent display state in which no voltage is applied to the liquid crystal layer 30, in addition to the black display state and the white display state. Displaying the background in the transparent display prevents the problem that the background is blurred (visually recognized double). Hereinafter, reasons why this problem (the display is blurred and visually recognized double) occurs in the liquid crystal display devices in Patent Documents 1 through 3 will be described by way of a liquid crystal display device in a comparative example.

[0088] FIG. 8(a) and FIG. 8(b) respectively show a liquid crystal display device 800 in a comparative example in the black display state and the white display state. The liquid crystal display device 800 in the comparative example has the same structure as that shown in FIG. 1 and FIG. 2 of Patent Document 3.

[0089] The liquid crystal display device 800 includes an array substrate 810, a counter substrate 820 and a liquid crystal layer 830 provided therebetween. The array substrate 810 includes a glass substrate 810a, and a lower electrode 812, an insulating layer 813 and a pair of comb electrodes (upper electrodes) 817 and 828 stacked on the glass substrate 810a in this order. Meanwhile, the counter substrate 820 includes a glass substrate 820a and a counter electrode 821 provided on the glass substrate 820a.

[0090] The liquid crystal layer 830 contains liquid crystal molecules 831 having positive dielectric anisotropy. In the liquid crystal display device 800, the liquid crystal molecules 831 in the liquid crystal layer 830 assume a vertical alignment state in the state where no voltage is applied.

[0091] In the liquid crystal display device 800 in the comparative example, for proving black display, a predetermined voltage is applied between the counter electrode 821 and the lower electrode 812/upper electrodes (pair of comb electrodes) 817 and 818 (for example, a potential of 7 V is given to the counter electrode 821, and a potential of 14 V is given to the lower electrode 812 and the upper electrodes 817 and 818), and a vertical electric field is generated in the liquid crystal layer 830. As a result, as shown in FIG. 8(a), the liquid crystal molecules 831 are aligned to be generally vertical to the substrate surface.

[0092] In the liquid crystal display device 800 in the comparative example, for proving white display, a predetermined voltage is applied between the pair of comb electrodes 817 and 818 (for example, a potential of 0 V is given to one of the comb electrodes, specifically, the comb electrode 817, and a potential of 14 V is given to the other of the comb electrodes, specifically, the comb electrode 818), and a lateral electric field is generated in the liquid crystal layer 830. As a result, as shown in FIG. 8(b), the liquid crystal molecules 831 are aligned as being inclined with respect to the normal to the substrate surface.

[0093] In the case where the liquid crystal display device 800 in the comparative example is simply used as a see-through display device, see-through display is provided, namely, display in which the background is seen though is provided, in the white display state in which the light transmittance of the pixels is high. However, the white display state is realized by applying a voltage to the liquid crystal layer 830 to align the liquid crystal molecules 830. Therefore, there occurs a refractive index distribution in each pixel. As a result, light L from the rear side is scattered (namely, the advancing direction of the light L is changed; see FIG. 8(b)) by the refractive index distribution), and thus the background is blurred. As a result, as shown in FIG. 9, a viewer V viewing the background BG via a see-through display device STDP visually recognizes the background double.

[0094] As described above, when see-through display is provided in the white display state in which a voltage is applied to the liquid crystal layer, the display is blurred (visually recognized double). By contrast, the liquid crystal display device 100 in this embodiment provides background display (see-through display) in the state where no voltage is applied to the liquid crystal layer 30 (in the transparent display state). Therefore, a viewer viewing the background via the liquid crystal display device 100 visually recognizes the background clearly. Thus, the display is prevented from being blurred (from being visually recognized double), and the quality of the see-through display is improved.

[0095] In the liquid crystal display device 100 in this embodiment, the ratio of the potential difference between the upper electrode 11 and the lower electrode 12 at each gray scale level from the lowest level to the highest level, with respect to the potential difference between the lower electrode 12 and the counter electrode 21 in the black display state, is a predetermined value or less. More specifically, the potential difference between the upper electrode 11 and the lower electrode 12 at each gray scale level is 60% or less of the potential difference between the lower electrode 12 and the counter electrode 21 in the black display state. This suppresses the occurrence of the abnormal alignment change described below. Hereinafter, this will be described more specifically.

[0096] As a result of active studies, the present inventors have confirmed that when a voltage applied to the upper electrode 11 (hereinafter, referred to as an “upper voltage”) and a voltage applied to the lower electrode 12 (hereinafter, referred to as a “lower voltage”) are simply set with no specific consideration, abnormal alignment change may occur at the time of gray scale level transition. FIG. 10 shows an example of voltage settings (relationship between the upper voltage/the lower voltage and the gray scale level) at which the abnormal alignment change occurs. Although not shown in FIG. 10, the voltage applied to the counter electrode 21 (counter voltage) is 0 V at all the gray scale levels.

[0097] In the example shown in FIG. 10, as the gray scale level is increased from level 0(corresponding to the black display state) to level 254(corresponding to the white display state), the upper voltage is decreased while the lower voltage is kept the same. Specifically, the upper voltage is changed (decreased) from 7 V to 0 V while the lower voltage is kept at 7.5 V. At level 255 (corresponding to the transparent display state), the upper voltage and also the lower voltage become 0 V. In this example, there are gray scale levels at which the potential difference between the upper electrode 11 and the lower electrode 12 exceeds 60% of the potential difference between the lower electrode 12 and the counter electrode 21 in the black display state. In the case where the voltage settings shown in FIG. 10 are adopted, abnormal alignment change may occur at the time of gray scale level transition.

[0098] FIG. 11 schematically shows an alignment change from the black display state via the halftone display state to the white display state. As seen from FIG. 11, as the gray scale level is increased, liquid crystal molecules 31 twisted in a direction opposite to the proper twisting direction and liquid crystal molecules 31 tilted in a direction opposite to the proper tilting direction appear in addition to liquid crystal molecules 31 aligned normally.

[0099] FIG. 12 schematically shows an alignment change from the white display state via the halftone display state to the black display state. As seen from FIG. 12, as the gray scale level is decreased, the number of the liquid crystal molecules 31 twisted in the opposite direction and the liquid crystal molecules 31 tilted in the opposite direction is decreased.

[0100] As seen from above, in the case where the voltage settings shown in FIG. 10 are adopted, abnormal alignment change occurs at the time of gray scale level transition. FIG. 11 and FIG. 12 show how white lines and black lines caused by the abnormal alignment change extend. The abnormal alignment change occurs at a visually recognizable speed (several hundred milliseconds to several seconds). The degree of abnormal alignment change varies inside each pixel and/or on a pixel-by-pixel basis. Therefore, the abnormal alignment change is observed as display non-uniformity or roughness, which declines the display quality.

[0101] With reference to FIG. 13(a) and FIG. 13 (b), an observation of the present inventors on a mechanism by which the abnormal alignment change occurs will be described. The abnormal alignment change is considered to occur because the alignment control force provided by the lateral electric field (fringe field) generated by the potential difference between the upper electrode 11 and the lower electrode 12, and the alignment control force provided by the horizontal alignment films 14 and 24, do not match each other partially. As shown in FIG. 13(a), while the gray scale level is increased from the black display state to the white display state, the potential difference between the upper electrode 11 and the lower electrode 12 exceeds a certain threshold. This is considered to cause the abnormal alignment change (herein, this is referred to “set”). As shown in FIG. 13(b), the abnormal alignment change is considered to be solved (herein, this is referred to “reset”) while the gray scale level is decreased from the white display state to the black display state.

[0102] FIG. 14 shows an example of settings of the upper voltage and the lower voltage in the liquid crystal display device 100 in this embodiment. As shown in FIG. 14, in the liquid crystal display device 100 in this embodiment, the potential difference between the upper electrode 11 and the lower electrode 12 is set so as not to exceed a certain threshold. Namely, the ratio of the potential difference between the upper electrode 11 and the lower electrode 12 at each gray scale level from the lowest level to the highest level, with respect to the potential difference between the lower electrode 12 and the counter electrode 21 in the black display state, is set to be a predetermined value or less (specifically, 60% or less)

[0103] In the example shown in FIG. 14, as the gray scale level is increased from the lowest level to the highest level, the voltage applied to the upper electrode 11 is decreased. Specifically, as the gray scale level is increased, the upper voltage is decreased from V.sub.1(e.g., 7 V) to 0 V. By contrast, the voltage applied to the lower electrode 12 is kept the same as the gray scale level is increased from the lowest level to a certain halftone level, and is decreased as the gray scale level is increased from the halftone level to the level corresponding to the white display state. Specifically, the lower voltage is kept at V.sub.2(e.g., 7.5 V) as the gray scale level is increased from the lowest level to a certain halftone level (level at which the upper voltage becomes V.sub.3), and then is decreased from V.sub.2 to V.sub.4 at the same ratio as that of the upper voltage as the gray scale level is increased from the halftone level to the level corresponding to the white display state. Namely, in this example, the potential difference between the upper electrode 11 and the lower electrode 12 is set to be V.sub.4 or less, and V.sub.4 is 60% or less of the potential difference V.sub.2 between the lower electrode 12 and the counter electrode 21 in the black display state.

[0104] The present inventors made an investigation on whether the abnormal alignment change would be suppressed or not in a plurality of settings different from each other in the maximum potential difference between the upper electrode 11 and the lower electrode 12. The results will be described. Table 1 shows, for each of settings 1 through 5, the upper voltage and the lower voltage in the black display state, the upper voltage when the lower voltage starts to be decreased (V.sub.3 in FIG. 14), the upper voltage and the lower voltage in the white display state (V.sub.4 in FIG. 14), and whether the abnormal alignment change is suppressed or not. In Table 1, “×” indicates that the abnormal alignment change occurred, and “◯” indicates that the abnormal alignment change was suppressed. “Δ” indicates that the abnormal alignment change was basically suppressed, but the abnormal alignment change occurred when the gray scale level was changed to the level corresponding to the white display state in a certain manner. The investigation results shown in Table 1 were obtained under the following conditions: width S of the slit 11a of the upper electrode 11: 3 μm; width L of the branched portion 11b: 4 μm; and dielectric anisotropy Δε of the liquid crystal material used for the liquid crystal layer 30: 17.8.

TABLE-US-00001 TABLE 1 BLACK DISPLAY WHITE DISPLAY STATE UPPER VOLTAGE STATE WHETHER UPPER LOWER WHEN LOWER VOLTAGE UPPER LOWER ABNORMAL VOLTAGE VOLTAGE STARTS TO BE DECREASED VOLTAGE VOLTAGE ALIGNMENT (V) (V) (V) (V) (V) IS SUPPRESSED SETTING 1 7 7.5 — 0 7.5 X SETTING 2 2 5.5 X SETTING 3 3 4.5 X SETTING 4   3.5 4 Δ SETTING 5 4 3.5 ◯

[0105] As seen from Table 1, in settings 1, 2 and 3, in which the maximum potential difference between the upper electrode 11 and the lower electrode 12 (same potential as the lower voltage in the white display state) was 7.5 V, 5.5 V and 4.5 V, the abnormal alignment change occurred. By contrast, in setting 4, in which the maximum potential difference between the upper electrode 11 and the lower electrode 12 was 4 V, the abnormal alignment change was suppressed. In setting 5, in which the maximum potential difference between the upper electrode 11 and the lower electrode 12 was 3.5 V, the abnormal alignment change was further suppressed.

[0106] Regarding each of settings 1 through 5, an investigation was made on whether the abnormal alignment change would be suppressed or not while the manner of transition of the gray scale level to the level corresponding to the white display state in various manners was changed. Table 2 shows the investigation results obtained when the transparent display state was suddenly changed to the white display state, when the black display state was suddenly changed to the white display state, when the black display state was gradually changed to the white display state, and when the transparent display state was gradually changed to the white display state. In Table 2, “×” indicates that the abnormal alignment change occurred, and “◯” indicates that the abnormal alignment change was suppressed.

TABLE-US-00002 TABLE 2 LOWER VOLTAGE IN WHITE DISPLAY STATE MANNER OF (=MAXIMUM POTENTIAL DIFFERENCE BETWEEN UPPER TRANSITION TO ELECTRODE AND LOWER ELECTRODE) WHITE DISPLAY SETTING SETTING SETTING SETTING SETTING STATE 1: 7.5 V 2: 5.5 V 3: 4.5 V 4: 4 V 5: 3.5 V SUDDENLY FROM x x x ∘ ∘ TRANSPARENT DISPLAY STATE SUDDENLY FROM x x x ∘ ∘ BLACK DISPLAY STATE GRADUALLY FROM x x x x ∘ BLACK DISPLAY STATE GRADUALLY FROM x x x x ∘ TRANSPARENT DISPLAY STATE

[0107] As seen from Table 2, in settings 1 through 3, the abnormal alignment change occurred in any of the manners of transition. In setting 4, the abnormal alignment change was suppressed when the transparent display state was suddenly changed to the white display state and when the black display state was suddenly changed to the white display state, but the abnormal alignment change occurred when the black display state was gradually changed to the white display state and when the transparent display state was gradually changed to the white display state. By contrast, in setting 5, the abnormal alignment change was suppressed in any of the manners of transition.

[0108] An investigation was made on whether the abnormal alignment change would be suppressed or not while the specification of the liquid crystal display panel 1 was changed. Table 3 shows the investigation results. Table 3 shows, in each of specifications 1 through 4, whether the abnormal alignment change was suppressed or not at various values of the dielectric anisotropy Δε of the liquid crystal material, the length L (μm) of the branched portion 11b of the upper electrode 11 and the width S (μm) of the slit 11a of the upper electrode 11, and when the lower voltage in the white display state was 3 V, 3.5 V, 4 V and 4.5 V. Specification 1 is used for the results shown in Table 1. In Table 3, “×”, “◯” and “Δ” indicate the same as those in Table 1.

TABLE-US-00003 TABLE 3 LOWER VOLTAGE IN WHITE DISPLAY STATE (=MAXIMUM POTENTIAL DIFFERENCE BETWEEN Δε OF UPPER ELECTRODE LIQUID AND LOWER CRYSTAL L/S OF UPPER ELECTRODE) MATERIAL ELECTRODE 3 V 3.5 V 4 V 4.5 V SPECIFI- 17.8 4/3 — ◯ Δ X CATION 1 SPECIFI- 5/3 — ◯ ◯ Δ CATION 2 SPECIFI- 3/5 ◯ Δ X — CATION 3 SPECIFI- 20 5/3 — ◯ Δ — CATION 4

[0109] As shown in Table 3, when the maximum potential difference between the upper electrode 11 and the lower electrode 12 was 4.5 V, the abnormal alignment change was suppressed in specification 2. When the maximum potential difference was 4 V, the abnormal alignment change was suppressed in specifications 1, 2 and 4. When the maximum potential difference was 3.5 V, the abnormal alignment change was suppressed in any of specifications 1 through 4.

[0110] It is seen from these results that in the case where the potential difference between the upper electrode 11 and the lower electrode 12 at each gray scale level from the lowest level to the highest level is 60% or less of the potential difference between the electrode 11 and the counter electrode 12 in the black display state, the abnormal alignment change is suppressed. It is also seen that from the point of view of suppressing the abnormal alignment change, the potential difference between the upper electrode 11 and the lower electrode 12 at each gray scale level from the lowest level to the highest level is preferably 54% or less, and more preferably 47% or less, of the potential difference between the electrode 11 and the counter electrode 12 in the black display state.

[0111] When the maximum potential difference between the upper electrode 11 and the lower electrode 12 is too small, the response speed may be undesirably decreased. Therefore, from the point of view of the response speed, it is considered to be preferable that the maximum potential difference between the upper electrode 11 and the lower electrode 12 is as large as possible in the range in which the abnormal alignment change is suppressed. Specifically, at a gray scale level, among all the gray scale levels from the lowest level to the highest level, at which the potential difference between the upper electrode 11 and the lower electrode 12 is maximum, the potential difference between the upper electrode 11 and the lower electrode 12 is preferably 30% or greater, and more preferably 40% or greater, of the potential difference between the lower electrode 12 and the counter electrode 21 in the black display state.

[0112] FIG. 15 shows the response waveforms (time vs. brightness relationships) of rise response in settings 4 and 5 shown in Table 1. FIG. 15 shows the response waveforms when the black display state is switched to the white display state at the maximum potential difference of 4 V (setting 4) and 3.5 V (setting 5) (respectively labeled as “0-254: 4 V” and “0-254: 3.5 V”). Fora comparison, FIG. 15 also shows the response waveforms when the black display state is switched to the white display state (labeled as “0-254”) and when the black display state is switched to the transparent display state (labeled as “0-255”) at the maximum potential difference of 7.5 V (setting 1). The brightness values along the vertical axis in FIG. 15 are relative values with respect to the brightness in the transparent display state being 100 (this is also applied to FIG. 17 described below).

[0113] As seen from FIG. 15, the rise response when the maximum potential difference is 3.5 V or 4 V (0-254: 3.5 V, 0-254: 4 V) is slightly lower than the rise response when the maximum potential difference is 7.5 V (0-254), but is higher than the response to the switch from the black display state to the transparent display state (0-255). Even in the case where the maximum potential difference between the upper electrode 11 and the lower electrode 12 is made smaller to a certain degree, a sufficiently high response speed is guaranteed.

[0114] FIG. 16 shows the waveform integrated values in a second half of period P1 shown in FIGS. 15 (132.1 to 134.2 ms). Herein, it is assumed to perform field sequential driving with a frame frequency of 240 Hz (1 frame: about 4.2 msec.) and a duty ratio (period in which the backlight is lit on) of 50%.

[0115] As seen from FIG. 16, when the maximum potential difference is 3.5 V or 4 V (0-254: 3.5 V, 0-254: 4 V), the brightness is lower by about 10% than the brightness when the maximum potential difference is 7.5 V (0-254).

[0116] FIG. 17 shows the response waveforms (time vs. brightness relationships) of decay response in settings 4 and 5 shown in Table 1. FIG. 17 shows the response waveforms when the white display state is switched to the black display state at the maximum potential difference of 4 V (setting 4) and 3.5 V (setting 5) (respectively labeled as “0-254: 4 V” and “0-254: 3.5 V”). Fora comparison, FIG. 17 also shows the response waveforms when the white display state is switched to the black display state (labeled as “0-254”) and when the transparent display state is switched to the black display state (labeled as “0-255”) at the maximum potential difference of 7.5 V (setting 1).

[0117] As seen from FIG. 17, the decay response when the maximum potential difference is 3.5 V or 4 V (0-254: 3.5 V, 0-254: 4 V) is higher than the decay response when the maximum potential difference is 7.5 V (0-254). As can be seen, the decay response is improved by decreasing the maximum potential difference between the upper electrode 11 and the lower electrode 12. It is seen from the waveforms at 158 to 160 ms that the color of white is made brighter by decreasing the lower voltage in the white display state.

[0118] FIG. 18 shows the waveform integrated values in a second half of period P2 shown in FIGS. 17 (162.1 to 164.2 ms). Herein, it is assumed to perform field sequential driving with a frame frequency of 240 Hz and a duty ratio of 50%.

[0119] As seen from FIG. 18, when the maximum potential difference is 3.5 V or 4 V (0-254: 3.5 V, 0-254: 4 V), the black display is darker than when the maximum potential difference is 7.5 V (0-254). As can be seen, when the field sequential driving is performed, the occurrence of color mixing is suppressed by decreasing the maximum potential difference between the upper electrode 11 and the lower electrode 12.

[0120] As described above, even when the maximum potential difference between the upper electrode 11 and the lower electrode 12 is decreased (even when the lower voltage in the white display state is decreased), a sufficiently high rise response speed is realized. In addition, the decay response is improved, and brighter white display is realized.

[0121] As described above, in the liquid crystal display device 100 in this embodiment, each pixel may exhibit the black display state, the white display state and the transparent display state in a switched manner. A conventional see-through display device provides see-through display in either the black display state or the white display state regardless of the type thereof (liquid crystal display device, PDLC display, organic EL display, etc.) (namely, the gray scale level corresponding to the black display state or the white display state is assigned to the see-through display). Therefore, see-through display is not provided at an applied voltage different from both of the voltage for the black display state and the voltage for the white display state. By contrast, in the liquid crystal display device 100 in this embodiment, each pixel may exhibit the black display state, the white display state, and also the transparent display state provided at a voltage different from both of the voltage for the black display state and the voltage for the white display state. Therefore, the display is prevented from being blurred (from being visually recognized double). In the liquid crystal display device 100 in this embodiment, the potential difference between the upper electrode 11 and the lower electrode 12 at each gray scale level is 60% or less of the potential difference between the lower electrode 12 and the counter electrode 21 in the black display state. This suppresses the occurrence of the abnormal alignment change at the time of gray scale level transition.

[0122] The settings of the upper voltage and the lower voltage are not limited to those shown in FIG. 14. FIG. 19 shows another example of settings of the upper voltage and the lower voltage.

[0123] In the example shown in FIG. 19, the voltage applied to the upper electrode 11 is decreased as the gray scale level is increased from the lowest level to the level corresponding to the white display state. Specifically, the upper voltage is decreased from V.sub.1(e.g., 7 V) to 0 V as the gray scale level is increased. The voltage applied to the lower electrode 12 is also decreased as the gray scale level is increased from the lowest level to the level corresponding to the white display state. Specifically, the lower voltage is decreased from V.sub.2(e.g., 7.5 V) to V.sub.3(predetermined voltage exceeding 0 V) at a ratio lower than that of the upper voltage, as the gray scale level is increased. Namely, in this example, the potential difference between the upper electrode 11 and the lower electrode 12 is set to be V.sub.3 or less, and V.sub.3 is 60% or less of the potential difference V.sub.2 between the lower electrode 12 and the counter electrode 21 in the black display state.

[0124] From the point of view of realizing high speed response, it is preferable that as strong a lateral electric field (fringe field) as possible is generated in the liquid crystal layer 30 at many gray scale levels. Therefore, from the point of view of providing a high response characteristic, the example shown in FIG. 14 is considered to be preferable to the example shown in FIG. 19.

[0125] FIG. 20 shows still another example of settings of the upper voltage and the lower voltage. In the example shown in FIG. 20, the voltage applied to the upper electrode 11 is decreased as the gray scale level is increased from the lowest level to one halftone level, is kept the same as the gray scale level is increased from the one halftone level to another halftone level, and is decreased as the gray scale level is increased from the another halftone level to the level corresponding to the white display state. Specifically, the upper voltage is decreased from V.sub.1(e.g., 7 V) to V.sub.3(predetermined voltage exceeding 0 V) as the gray scale level is increased from the lowest level to one halftone level, is kept at V.sub.3 as the gray scale level is increased from the one halftone level to another halftone level, and is decreased from V.sub.3 to 0 V as the gray scale level is increased from the another halftone level to the level corresponding to the white display state. By contrast, the voltage applied to the lower electrode 12 is kept the same as the gray scale level is increased from the lowest level to a halftone level, and is decreased as the gray scale level is increased from the halftone level to the level corresponding to the white display state. Specifically, the lower voltage is kept at V.sub.2 (e.g., 7.5 V) as the gray scale level is increased from the lowest level to a halftone level (level at which the upper voltage becomes V.sub.3), and is decreased from V.sub.2 to V.sub.4 as the gray scale level is increased from the halftone level to the level corresponding to the white display state. Namely, in this example, the potential difference between the upper electrode 11 and the lower electrode 12 is set to be not more than V.sub.4 or (V.sub.2−V.sub.3), whichever is larger. V.sub.4 or (V.sub.2−V.sub.3), whichever is larger, is 60% or less of the potential difference V.sub.2 between the lower electrode 12 and the counter electrode 21 in the black display state.

[0126] From the point of view of realizing high speed response, the example shown in FIG. 14 is considered to be preferable to the example shown in FIG. 20 for the same reason as described above regarding the example shown in FIG. 19.

[0127] In this embodiment, in the transparent display state, the liquid crystal molecules 31 in the liquid crystal layer 30 assume twisted alignment. This realizes clearer transparent display for the following reason. When assuming twisted alignment, the liquid crystal molecules 31 are oriented in the same direction in a plane parallel to the display surface. Therefore, there is no diffraction caused by the refractive index difference in the plane or diffraction by the dark line caused by the liquid crystal mode (dark line caused by a structural body controlling the alignment direction or dark line by discontinuity in the alignment direction caused in the plane).

[0128] In this example, in the white display state and the transparent display state, the liquid crystal molecules 31 at, and in the vicinity of, the central portion of the liquid crystal layer 30 in the thickness direction are aligned to be generally perpendicular to the slit direction D (namely, the average alignment direction of the bulk liquid crystal portion is generally perpendicular to the slit direction D). Alternatively, the liquid crystal molecules 31 at, and in the vicinity of, the central portion of the liquid crystal layer 30 in the thickness direction may be aligned to be generally parallel to the slit direction D (namely, the average alignment direction of the bulk liquid crystal portion is generally parallel to the slit direction D). It should be noted that the former structure (perpendicular type structure) is preferable to the latter structure (parallel type structure) from the point of view of display brightness.

[0129] Still alternatively, as in a liquid crystal display device 100′ shown in FIG. 21 and FIG. 22, the liquid crystal molecules 31 in the liquid crystal layer 30 may assume homogeneous alignment in the transparent display state.

[0130] In the liquid crystal display device 100′, the pretilt directions respectively controlled by the first horizontal alignment film 14 and the second horizontal alignment state 24 are set such that the liquid crystal molecules 31 assume homogeneous alignment in the state where no voltage is applied to the liquid crystal layer 30(in the state where no electric field is generated). Specifically, the pretilt directions respectively controlled by the first horizontal alignment film 14 and the second horizontal alignment state 24 are generally perpendicular to the direction in which the slits 11a of the upper electrode 11 extend (generally perpendicular to the slit direction D). Namely, the pretilt direction controlled by the first horizontal alignment film 14 and the pretilt direction controlled by the second horizontal alignment film 24 are parallel or antiparallel to each other.

[0131] The transmission axes 15a and 25a of the first polarization plate 15 and the second polarization plate 25 have an angle of about 45 degrees with respect to the pretilt directions respectively controlled by the first horizontal alignment film 14 and the second horizontal alignment film 24. Therefore, the transmission axes 15a and 25a of the first polarization plate 15 and the second polarization plate 25 have an angle of about 45 degrees with respect to the slit direction D.

[0132] FIG. 23(a) and FIG. 23(b) show an alignment state of the liquid crystal molecules 31 in the black display state. In the black display state, a predetermined voltage is applied between the counter electrode 21 and the upper electrode 11/lower electrode 12 (for example, potentials of 7 V, 7.5 V and 0 V are respectively given to the upper electrode 11, the lower electrode 12 and the counter electrode 21), and a vertical electric field is generated in the liquid crystal layer 30. FIG. 23(a) schematically shows line of electric force in this state with dashed lines.

[0133] In the black display state, as shown in FIG. 23(a) and FIG. 23(b), the liquid crystal molecules 31 in the liquid crystal layer 30 are aligned to be generally vertical to the substrate surface (surfaces of the rear substrate 10 and the front substrate 20) (namely, aligned to be generally parallel to the normal to the liquid crystal layer 30).

[0134] FIG. 24(a) and FIG. 24(b) show an alignment state of the liquid crystal molecules 31 in the white display state. In the white display state, a predetermined voltage is applied between the upper electrode 11 and the lower electrode 12 (for example, potentials of 0 V, 7.5 V and 0 V are respectively given to the upper electrode 11, the lower electrode 12 and the counter electrode 21), and a lateral electric field (fringe field) is generated in the liquid crystal layer 30. FIG. 24(a) schematically shows line of electric force in this state with dashed lines.

[0135] In the white display state, as shown in FIG. 24(a) and FIG. 24(b), the liquid crystal molecules 31 in the liquid crystal layer 30 are aligned to be generally parallel to the substrate surface (namely, aligned to be generally vertical to the normal to the liquid crystal layer 30). More specifically, the liquid crystal molecules 31 are aligned to be generally perpendicular to the direction D in which the slits 11a of the upper electrode 11 extend. Namely, the liquid crystal molecules 31 are aligned to have an angle of about 45 degrees with respect to the transmission axes 15a and 25a of the first polarization plate 15 and the second polarization plate 25.

[0136] FIG. 25(a) and FIG. 25(b) show an alignment state of the liquid crystal molecules 31 in the transparent display state. In the transparent display state, no voltage is applied to the liquid crystal layer 30 (for example, a potential of 0 V is given to all of the upper electrode 11, the lower electrode 12 and the counter electrode 21), and neither a vertical electric field nor a lateral electric field is generated in the liquid crystal layer 30.

[0137] In the transparent display state, as shown in FIG. 25(a) and FIG. 25(b), the liquid crystal molecules 31 in the liquid crystal layer 30 assume homogeneous alignment. Namely, the liquid crystal molecules 31 are aligned to be generally parallel to the substrate surface (namely, aligned to be generally vertical to the normal to the liquid crystal layer 30). More specifically, the liquid crystal molecules 31 are aligned to be generally perpendicular to the direction D in which the slits 11a of the upper electrode 11 extend. Namely, the liquid crystal molecules 31 are aligned to have an angle of about 45 degrees with respect to the transmission axes 15a and 25a of the first polarization plate 15 and the second polarization plate 25. In this transparent display state, pixels in the liquid crystal display device 100′ have a highest light transmittance (namely, higher light transmittance than in the black display state or the white display state).

[0138] Also in the liquid crystal display device 100′, a vertical electric field is generated in the liquid crystal layer 30 in the black display state and a lateral electric field is generated in the liquid crystal layer 30 in the white display state. Therefore, a torque by voltage application acts on the liquid crystal molecules 31 in both of the fall (transition from the white display state to the black display state) and the rise (transition from the black display state to the white display state), and thus a high speed response characteristic is provided. Each of the pixels may exhibit the black display state, the white display state, and also the transparent display state in which no voltage is applied to the liquid crystal layer 30. Therefore, the problem that the background is blurred (visually recognized double) is prevented. In addition, the potential difference between the upper electrode 11 and the lower electrode 12 at each gray scale level is 60% or less of the potential difference between the lower electrode 12 and the counter electrode 21 in the black display state. This suppresses the occurrence of the abnormal alignment change at the time of gray scale level transition.

[0139] FIG. 1 and FIG. 21 show a structure in which the backlight unit of the edge light system as the illumination element 2 is located on the rear side of the liquid crystal display panel 1 so as to overlap the liquid crystal display panel 1. The illumination element 2 is not limited to being provided in this manner.

[0140] For example, the structure shown in FIG. 26 may be adopted. In the structure shown in FIG. 26, the liquid crystal display panel 1 and the illumination element 2 of the liquid crystal display device 100 (or the liquid crystal display device 100′) are attached to a box-shaped transparent case 50. The case 50 having the liquid crystal display panel 1 and the illumination element 2 attached thereto is used as, for example, a showcase.

[0141] The liquid crystal display panel 1 is attached to a side surface 50s among a plurality of side surfaces of the case 50. The illumination element 2 is attached to a top surface 50t of the case 50. As described above, the illumination element 2 may direct light of a plurality of colors including red light, green light and blue light in a switched manner toward the liquid crystal display panel 1. From the point of view of increasing the light utilization factor (from the point of view of causing light from the illumination element 2 in as much amount as possible to be incident on the liquid crystal display panel 1), it is preferable that an inner surface of the case 50 is light-diffusive.

[0142] In the above, color display provided in the field sequential system is described. The liquid crystal display device in an embodiment according to the present invention is not limited to a liquid crystal display device providing color display in the field sequential system. Even a liquid crystal display device including a liquid crystal display panel that includes a color filter prevents display from being blurred (from being visually recognized double) as long as the pixels exhibit the black display state, the white display state and the transparent display state in a switched manner.

INDUSTRIAL APPLICABILITY

[0143] An embodiment according to the present invention provides a liquid crystal display device that has a high response characteristic and also provides a high display quality and is preferably usable as a see-through display device. The liquid crystal display device (see-through display device) in an embodiment according to the present invention is usable as a display device for, for example, illumination display or digital signage.

REFERENCE SIGNS LIST

[0144] 1 Liquid crystal display panel

[0145] 2 Illumination element

[0146] 2a Light source unit

[0147] 2b Light guide plate

[0148] 10 First substrate (rear substrate)

[0149] 10a Transparent substrate

[0150] 11 First electrode (upper electrode)

[0151] 11a Slit

[0152] 11b Branched portion

[0153] 12 Second electrode (lower electrode)

[0154] 13 Insulating layer

[0155] 14 First horizontal alignment film

[0156] 15 First polarization plate

[0157] 15a Transmission axis of the first polarization plate

[0158] 16A First TFT

[0159] 16B Second TFT

[0160] 17 Gate bus line

[0161] 18 Source bus line

[0162] 20 Second substrate (front substrate)

[0163] 20a Transparent substrate

[0164] 21 Third electrode (counter electrode)

[0165] 24 Second horizontal alignment film

[0166] 25 Second polarization plate

[0167] 25a Transmission axis of the second polarization plate

[0168] 30 Liquid crystal layer

[0169] 31 Liquid crystal molecule

[0170] 50 Case

[0171] 100, 100′ Liquid crystal display device