SILICON-BASED QUANTUM DOT DEVICE

Abstract

A silicon-based quantum dot device (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate which is configured to provide at least one quantum dot (5.sub.1, 5.sub.2: FIG. 5). The layer of silicon or silicon-germanium has a thickness of no more than ten monolayers. The layer of silicon or silicon-germanium may have a thickness of no more than eight or five monolayers.

Claims

1. A silicon-based quantum dot device comprising: a substrate; and a layer of silicon or silicon-germanium supported on the substrate configured to provide at least one quantum dot; characterised in that the layer of silicon or silicon-germanium has a thickness of no more than ten monolayers.

2. A device according to claim 1, wherein the layer of silicon or silicon-germanium has a thickness no more than eight or five monolayers.

3. A device according to claim 1, wherein the layer of silicon or silicon-germanium has a thickness of at least three monolayers.

4. A device according to claim 1, wherein the layer of silicon or silicon-germanium has a thickness of three, four or five monolayers.

5. A device according to claim 1, wherein the layer of silicon or silicon-germanium has a root mean square surface roughness of no more than 2 monolayers and no more than 20% of the thickness of the layer.

6. A device according to claim 1, wherein the layer of silicon or silicon-germanium comprises an isolated region of silicon or silicon-germanium having lateral dimensions, each lateral dimension being no more than 100 nm.

7. A device according to claim 1, further comprising: first and second layers of dielectric material; wherein the layer of silicon or silicon-germanium is interposed between the first and second layers of dielectric material and is in direct contact with the first and second layers of dielectric material.

8. A device according to claim 7, wherein the first and/or second layers of dielectric material comprise silicon dioxide.

9. A device according to claim 1, wherein the layer of silicon or silicon-germanium is configured to provide at least one isolated double quantum dot.

10. A device according to claim 1, wherein the layer of silicon or silicon-germanium comprises a plurality of regions which are spaced apart, which are electrically isolated from each other and which provide at least one quantum dot system, at least one gate and at least one electrometer.

11. A device according to claim 1, further comprising: at least one electrometer arranged to measure charge distribution in the at least one quantum dot.

12. A device according to claim 1, further comprising: at least one gate arranged to apply an electric field to the at least one quantum dot.

13. A device according to claim 1, wherein the device is a quantum information processing device.

14. A device according to claim 1, wherein the device is a photon source or a photon detector.

15. Apparatus comprising: a device according to claims 1; an optional refrigerator for cooling the device to a temperature equal to or less than 4.2° K.; and circuitry for applying biases to the device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

[0019] FIG. 1a illustrates an ultra-thin layer of silicon;

[0020] FIG. 1b shows a quantum well formed by the ultra-thin layer shown in FIG. 1a;

[0021] FIG. 2 shows plots of valley splitting against number of monolayers for a silicon quantum well comprising a layer of silicon having surfaces terminated with hydrogen calculated using a density functional theory (DFT) model and a 30×30 multi-band envelope wavefunction model (k.p) model;

[0022] FIG. 3 shows a band structure a layer of silicon having a thickness of six monolayers and surfaces terminated with hydrogen calculated using a DFT model and a 30×30 k.p model;

[0023] FIG. 4 shows plots of valley splitting against number of monolayers for a silicon quantum well comprising a layer of silicon embedded in silicon dioxide calculated using a DFT model and a 30×30 k.p model;

[0024] FIG. 5 is a plan view of silicon-based quantum information processing device comprising two isolated double quantum dots; and

[0025] FIG. 6 is a cross sectional view of the silicon-based quantum information processing device shown in FIG. 5 taken along the line A-A′.

DETAILED DESCRIPTION OF CERTAIN EMBODIMENTS

[0026] Referring to FIG. 1a, the band structure of a layer of silicon is modelled using density functional theory (DFT) and a 30×30 k.p band structure models. Referring also to FIG. 1b, if the layer of silicon is sufficiently thin, then a quantum well is formed.

[0027] The DFT model uses a generalized gradient approximation employing plane-wave-based ultrasoft pseudopotentials. The model is the same as that described in Yuji Suwa and Shin-ichi Saito: “Intrinsic optical gain of ultrathin silicon quantum wells from first-principles calculations”, Physical Review B, volume 79, page 233308 (2009) which is incorporated herein by reference.

[0028] The 30×30 k.p model gives an accurate description of silicon bulk band structure in the whole Brillouin zone in an energy range from −4 eV to +4 eV (where 0 eV corresponds to the valence band edge). The wavefunctions of the carriers in a silicon thin quantum well is expanded as a superposition of bulk plane waves and the coefficients of the expansion are found numerically from the solution of the eigenvalue problem resulted from corresponding Schrodinger equation with 30×30 kp effective Hamiltonian:

[00001]$\begin{array}{cc}\Psi \left(r\right).Math.\underset{k_z}{.Math.}.Math.\underset{\alpha =1}{\overset{N_H}{.Math.}}.Math.C_{\alpha }\left(k_{//},k_z\right).Math.\exp \left({\mathrm{ik}}_z+{\mathrm{ik}}_{//.Math.}.Math.r_{//}\right).Math.u_{\alpha }\left(r\right)& \left(1\right)\end{array}$

where z is perpendicular to the silicon layer and the summation is carried over all basis states described by Bloch functions u.sub.α (r), α=1, 2, . . . , N.sub.H=30 over all possible z-components k.sub.z of the wavevector (k.sub.∥,k.sub.z) inside the Brillion zone. Reference is made to D. Rideau et al: “Strained Si, Ge, and Si.sub.1-xGe.sub.x alloys modeled with a first-principles-optimized full-zone k.Math.p method”, Physical Review B, volume 74, page 195208 (2006) and A. D. Andreev, R. A. Surfs: “Nearly free carrier model for calculating the carrier spectrum in heterostructures”, Semiconductors, volume 30, pages 285 to 292 (1996).

[0029] FIG. 2 shows plots of calculated valley splitting in silicon quantum well using DFT and 30×30 kp methods for hydrogen-terminated silicon. It is clear that the intervalley splitting significantly increases when layer thickness (i.e. quantum well width) decreases, particularly when the layer thickness is five monolayers.

[0030] FIG. 3 shows the calculated band diagram for a silicon quantum dot formed by a layer of silicon which is six monolayers thick. Both models give similar results.

[0031] FIG. 4 shows plots of calculated valley splitting in a silicon quantum well comprising a layer of silicon sandwiched between silicon dioxide using DFT and 30×30 kp methods. It is clear that if the layer of silicon is five monolayers thick, then the splitting between electrons in different valleys can be increase by up to 160 to 180 meV.

[0032] Without wishing to be bound by theory, the thin layer is thought to push electrons to the surface/interface. This is thought to increase the interface-related electric field averaged over the electron wavefunction squared modulus. A thicker layer, with a rougher surface, is thought not allow proper localization of electrons. Instead, electrons break it into small pockets.

[0033] EP 2 075 745 A1 (which is incorporated herein by reference) describes a quantum information processing device. The devices described therein comprise a layer of silicon having a thickness equal to or less than about 50 nm patterned to form regions of silicon which provide isolated double quantum dots. If the layer of silicon is made sufficiently thin and its surfaces are atomically flat, then intervalley splitting in these devices can be increased significantly.

[0034] EP 1 860 600 A1 and EP 2 264 653 A1 (which are incorporated herein by reference) describe similar devices which can be modified by using a layer of silicon no more than five monolayers thick.

[0035] An example of a quantum information processing device will be briefly described with reference to FIGS. 5 and 6. However, details regarding fabrication, device layout and operation can be found in EP 2 075 745 A1 ibid.

[0036] Referring to FIGS. 5 and 6, the quantum information processing device 1 comprises first and second isolated double quantum dot systems 21, 22 which are arranged end-to-end at near ends and which are capacitively coupled (at their far ends) to first and second single-electron transistors 3.sub.1, 3.sub.2 respectively. Each isolated quantum dot systems 2.sub.1, 2.sub.2 has first and second lobes 4.sub.1, 4.sub.2 which house first and second quantum dots respectively 5.sub.1, 5.sub.2. The device 1 includes a plurality of side gates 6.sub.1, 6.sub.2, . . . , 6.sub.8 for controlling operation of the isolated quantum dot systems 2.sub.1, 2.sub.2. The first and second single-electron transistors 3.sub.1, 3.sub.2 include source S, drain D and channel C, which includes one or more conductive islands, and side gates G. Lateral dimensions can be found in EP 2 075 745 A1 ibid.

[0037] Referring in particular to FIG. 6, the isolated quantum dot systems 2.sub.1, 2.sub.2, single-electron transistors 3.sub.1, 3.sub.2 and side gates 6.sub.1, 6.sub.2, . . . , 6.sub.8 are formed in an ultrathin layer of silicon 7, i.e. a layer of silicon having a thickness, t, which is no more than five monolayers thick. The ultrathin layer of silicon 7 is supported on a substrate 8 comprising a silicon base 9 and an overlying layer 10 of silicon dioxide. The layer of silicon 7 is covered by a layer 11 of silicon dioxide. The layer of silicon 7 is divided into regions 7.sub.1, 7.sub.2, 7.sub.3 by sidewalls 12 and flanking regions 13 of silicon dioxide. Details regarding fabrication can be found in EP 2 075 745 A1 ibid.

[0038] The silicon layer 7 is monocrystalline. The surface of the silicon layer 7 lies in the (100) crystal plane. However other crystal orientations are also possible provided that the surface roughness is sufficiently low. The layer 7 is obtained by patterning a silicon-on-insulator wafer (not shown). Different fabrication methods may be used to form suitably thin layers, e.g. by sacrificially growing an oxide layer or by depositing a dielectric layer on a suitably thin layer of silicon.

[0039] The silicon layer 7 can be obtained by sacrificially growing an oxide layer, starting from a thicker layer of silicon, using a thermal oxidation process. The thermal oxidation process can form a uniform silicon dioxide layer with small thickness variability. The thickness is controlled by the starting thickness and the oxidation time. Reference is made to K. Uchida et al: “Experimental Study on Carrier Transport Mechanisms in Double- and Single-Gate Ultrathin-Body MOSFETs—Coulomb Scattering, Volume Inversion, and δTSOI-induced Scattering—”. Technical Digest of International Electron Devices Meeting (IEDM) Washington D.C., pages 805 to 808 (2003).

[0040] Interfaces 14.sub.1, 14.sub.2 between silicon 7 and silicon dioxide 10, 11 are smooth, i.e. having a root mean square (rms) surface roughness of no more than two monolayers and which preferably is no more 20% of the layer thickness, more preferably no more than 5% of the layer thickness and even more preferably no more than 2% of the layer thickness. Thus, for a layer having a thickness of five monolayers, the rms surface roughness is preferably no more than one monolayer, more preferably no more than 0.2 monolayers and even more preferably no more than 0.1 monolayers. For a layer having a thickness of four monolayers, the rms surface roughness is preferably no more than 0.8 monolayers, more preferably no more than 0.2 monolayers and even more preferably no more than 0.1 monolayers. For a layer having a thickness of three monolayers, the rms surface roughness is preferably no more than 0.6 monolayers, more preferably no more than 0.15 monolayers and even more preferably no more than 0.06 monolayers. Even more preferably the interfaces 14.sub.1, 14.sub.2 are substantially flat.

[0041] A set of voltage sources 13.sub.1, 13.sub.2, . . . , 13.sub.n are used to apply biases to the side gates 6.sub.1, 6.sub.2, . . . , 6.sub.8 and the single-electron transistors 3.sub.1, 3.sub.2. A method of operating the device 1 can be found in EP 2 075 745 A1 ibid.

[0042] It will be appreciated that many modifications may be made to the embodiments hereinbefore described.

[0043] For example, the device can be a silicon-based photon source and/or detector comprising one or more quantum dots.

[0044] Other dielectric materials can be used, such as silicon nitride. Other gate arrangements, e.g. top gate, bottom gate etc., can be used.

[0045] Instead of silicon, the layer may comprise silicon-germanium (Si.sub.1-xGe.sub.x), where x>0, for example, in the range 0.01 to 0.2.

[0046] The silicon or silicon-germanium layer may be strained.