TEST STRUCTURE AND METHOD FOR JUDGING DE-EMBEDDING ACCURACY OF RF DEVICES BY USING AN INTRODUCED DEVICE

Abstract

The present invention discloses a test structure and a method for judging the de-embedding accuracy of RF devices, which comprises testing the S parameters of a target device test structure, an introduced device test structure and an auxiliary test structure, respectively. Then calculating de-embedding S parameters of the target device test structure and the introduced device test structure according to the above-tested results, respectively. Finally, calculating performance parameters of the target device test structure according to the above-calculated de-embedding S parameters. So, the accuracy of the de-embedding method is determined by comparing the consistency of the performance parameters. The present invention can directly judge the de-embedding accuracy and the applicable frequency range of a given de-embedding method by analyzing the testing data. Further, the using of the parallel test structure and the cascade test structure together can increase the reliability of the judgment results.

Claims

1. A test structure for judging the de-embedding accuracy of a RF device by using an introduced device, comprising a target device test structure D1, an introduced device test structure and a corresponding auxiliary test structure D5, wherein the introduced device test structure includes a reference device test structure D2, a parallel test structure D3 of the target device and the reference device, a cascade test structure D4 of the target device and the reference device; combining the target device test structure D1, the reference device test structure D2, the parallel test structure D3 of the target device and the reference device, the cascade test structure D4 of the target device and the reference device, and the auxiliary test structure D5 to judge the de-embedding accuracy of the RF device.

2. A method for judging the de-embedding accuracy of a RF device by using an introduced device, characterized that the de-embedding accuracy is judged by combination calculations of a target device test structure D1, an introduced device test structure and a corresponding auxiliary test structure D5, wherein the introduced device test structure comprises a reference device test structure D2, a parallel test structure D3 of the target device and the reference device, a cascade test structure D4 of the target device and the reference device; the combination calculations comprise: testing S parameters of the test structures D1˜D5; calculating de-embedding S parameters of the test structures D1˜D4; calculating test performance parameters of the target device test structure D1 according to the de-embedding S parameters calculated above; and judging the de-embedding accuracy by comparing the consistency of the test performance parameters.

3. The method according to claim 2, comprising the following steps: Step S01: testing the S parameters of the target device test structure D1, the reference test structure D2, the parallel test structure D3, the cascade test structure D4, and the auxiliary test structure D5, respectively; Step S02: calculating the de-embedding S parameters of the target device test structure D1, the reference test structure D2, the parallel test structure D3 and the cascade test structure D4 according to the S parameters of the test structures D1-D4 and D5; Step S031: calculating a first result value X1 of the test performance parameters of the target device according to the above-calculated de-embedding S parameter of the target device test structure D1; Step S032: calculating a second result value X2 of the test performance parameters of the target device according to the above-calculated de-embedding S parameters of the reference test structure D2 and the parallel test structure D3; Step S033: calculating a third result value X3 of the test performance parameters of the target device according to the above-calculated de-embedding S parameters of the reference test structure D2 and the cascade test structure D4; Step S04: obtaining error values by calculating the differences of X1 and X2, X2 and X3, and X1 and X3, and comparing the error values with the preset value to judge the accuracy and the applicable frequency range of the de-embedding method.

4. The method according to claim 3, wherein, the Step S02 also includes converting the S parameters of the test structures D1-D4 and the auxiliary test structure D5 into network parameters of them, then calculating and removing parasitic factors of the network parameters of the test structures D1-D4, finally, the de-embedding S parameters of the test structures D1, D2, D3, D4 are obtained.

5. The method according to claim 3, wherein, the Step S031 also includes converting the de-embedding S parameter of the target device test structure D1 into a Y parameter of its, then calculating the first result value X1 of the test performance parameters by the relationship between the converted Y parameter of the target device test structure D1 and the test performance parameters.

6. The method according to claim 3, wherein, the Step S032 also includes converting the de-embedding S parameters of the reference device test structure D2 and the parallel test structure D3 into Y parameters of them, calculating a Y parameter of the target device test structure according to a formula of Y parameters of the target device test structure, the reference device test structure and the parallel test structure in the two-port network interconnection theory, and calculating the second result value X2 of the test performance parameters by the relationship of the calculated Y parameter of the target device test structure and the test performance parameters.

7. The method according to claim 6, wherein, the formula of Y parameters of the target device test structure, the reference device test structure and the parallel test structure in the step S032 is $Y_{\mathrm{PAR}}=Y_1+Y_2=\left[\begin{array}{cc}{Y}_{1,11}+Y_{2,11}& Y_{1,12}+Y_{2,12}\\ Y_{1,21}+Y_{2,21}& Y_{1,22}+Y_{2,22}\end{array}\right]$ wherein Y.sub.PAR is the Y parameter of the parallel test structure, Y.sub.1 is the Y parameter of the target device test structure, and Y.sub.2 is the Y parameter of the reference device test structure.

8. The method according to claim 3, wherein, the Step S033 also includes converting the de-embedding S parameters of the reference device test structure D2 and the cascade test structure D4 into ABCD parameters of them, calculating an ABCD parameter of the target device test structure according to a formula of ABCD parameters of the target device test structure, the reference device test structure and the cascade test structure in the two-port network interconnection theory, converting the calculated ABCD parameter of the target device test structure into its Y parameter, and calculating the third result value X3 of the test performance parameters by the relationship of the Y parameter of the target device test structure and the test performance parameters.

9. The method according to claim 8, wherein, the formula of ABCD parameters of the target device test structure, the reference device test structure and the cascade test structure in the Step S033 is $\left[\begin{array}{cc}{A}_{\mathrm{CAS}}& B_{\mathrm{CAS}}\\ C_{\mathrm{CAS}}& D_{\mathrm{CAS}}\end{array}\right]=\left[\begin{array}{cc}{A}_1& B_1\\ C_1& D_1\end{array}\right]\left[\begin{array}{cc}{A}_2& B_2\\ C_2& D_2\end{array}\right]$ wherein the subscript CAS indicates the cascade test structure, the subscript 1 indicates the target device test structure, and the subscript 2 indicates the reference device test structure.

10. The method according to claim 3, wherein, the Step S04 also includes that if the minimum error value is lower than the preset value, it is judged that the accuracy and the applicable frequency range of the RF device both are acceptable; if the minimum error value is higher than the preset value, it is judged that the accuracy and applicable frequency range of the RF device both are unacceptable.

11. The method according to claim 2, wherein, the auxiliary test structure D5 includes one or more of an open circuit test structure, a short circuit test structure and a through test structure corresponding to the de-embedding method, the target device test structure, the reference device test structure, the parallel test structure of the target device and the reference device, the cascade test structure of the target device and the reference device, and the auxiliary test structure all have a same basic structure with same signal input and output pads, grounded pads and metal leads.

12. The method according to claim 2, wherein, the target device or the reference device is one of a capacitor, an inductor, a resistor, and a transistor without external bias, respectively.

13. The method according to claim 3, wherein, the auxiliary test structure D5 includes one or more of an open circuit test structure, a short circuit test structure and a through test structure corresponding to the de-embedding method, the target device test structure, the reference device test structure, the parallel test structure of the target device and the reference device, the cascade test structure of the target device and the reference device, and the auxiliary test structure all have a same basic structure with same signal input and output pads, grounded pads and metal leads.

14. The method according to claim 3, wherein, the target device or the reference device is one of a capacitor, an inductor, a resistor, and a transistor without external bias, respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0044] For a better understanding of the objects, features and advantages of the present invention, preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which:

[0045] FIG. 1 is a schematic view illustrating a de-embedding structure of a prior open-thru de-embedding method;

[0046] FIG. 2 is a flow chart illustrating a de-embedding calculation method of a prior open-thru de-embedding method;

[0047] FIG. 3 is a block diagram illustrating a DUT structure in a de-embedding calculation of the prior art;

[0048] FIG. 4 is a schematic view illustrating an open circuit test structure according to a first embodiment of the present invention;

[0049] FIG. 5 is a schematic view illustrating a short circuit test structure according to a first embodiment of the present invention;

[0050] FIG. 6 is a schematic view illustrating an inductance test structure according to a first embodiment of the present invention;

[0051] FIG. 7 is a schematic view illustrating a MOM capacitance test structure according to a first embodiment of the present invention;

[0052] FIG. 8 is a schematic view illustrating a parallel test structure of capacitor and inductor according to a first embodiment of the present invention;

[0053] FIG. 9 is a schematic view illustrating a cascade test structure of capacitor and inductor according to a first embodiment of the present invention;

[0054] FIG. 10 is a flow chart illustrating a method of judging the de-embedding accuracy of a RF device by using an introduced device according to a first embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0055] A test structure and method for judging de-embedding accuracy of the RF device by using an introduced device is disclosed in the present invention, which is aimed on judging the de-embedding accuracy of one or more of the test performance parameters for a target device. Through introducing additional test structures, i.e. a reference device test structure, e. g., inductance, capacitance, resistance, and etc., a parallel test structure of the reference test structure and the target device and a cascade test structure of the reference test structure and the target device, the de-embedding accuracy and the applicable frequency range of a given de-embedding method can be directly judged from the received testing results basing on the various test structures.

[0056] The test structure of the present invention includes a target device test structure D1, an introduced device test structure and a corresponding auxiliary test structure D5, wherein the introduced device test structure includes a reference device test structure D2, a parallel test structure D3 of the target device and the reference device, a cascade test structure D4 of the target device and the reference device. Combining the target device test structure D1, the reference device test structure D2, the parallel test structure D3 of the target device and the reference device, the cascade test structure D4 of the target device and the reference device, and the auxiliary test structure D5 to judge the de-embedding accuracy of the RF device.

[0057] The method of the present invention characterized that the de-embedding accuracy is judged by combination calculations of a target device test structure D1, an introduced device test structure and a corresponding auxiliary test structure D5, wherein the introduced device test structure comprises a reference device test structure D2, a parallel test structure D3 of the target device and the reference device, a cascade test structure D4 of the target device and the reference device; the combination calculations comprise: testing S parameters of the test structures D1˜D5; calculating de-embedding S parameters of the test structures D1˜D4; calculating test performance parameters of the target device test structure D1 according to the de-embedding S parameters calculated above; and judging the de-embedding accuracy by comparing the consistency of the test performance parameters. Wherein the test performance parameters of the target device D1 can be calculated basing on the de-embedding S parameters, specifically, including the de-embedding S parameter of the target device test structure D1 and the de-embedding S parameter of the introduced device test structure.

[0058] Specifically, the method comprises the steps of:

[0059] Step S01: testing the S parameters of the target device test structure D1, the reference test structure D2, the parallel test structure D3, the cascade test structure D4, and the auxiliary test structure D5, respectively;

[0060] Step S02: calculating the de-embedding S parameters of the target device test structure D1, the reference test structure D2, the parallel test structure D3 and the cascade test structure D4 according to the S parameters of the test structures D1-D4 and D5;

[0061] Step S031: calculating a first result value X1 of the test performance parameters of the target device according to the above-calculated de-embedding S parameter of the target device test structure D1;

[0062] Step S032: calculating a second result value X2 of the test performance parameters of the target device according to the above-calculated de-embedding S parameters of the reference test structure D2 and the parallel test structure D3;

[0063] Step S033: calculating a third result value X3 of the test performance parameters of the target device according to the above-calculated de-embedding S parameters of the reference test structure D2 and the cascade test structure D4;

[0064] Step S04: obtaining error values by calculating the differences of X1 and X2, X2 and X3, and X1 and X3, and comparing the error values with the preset value to judge the accuracy and the applicable frequency range of the de-embedding method.

[0065] In the present invention, the above-mentioned target device test structure, the reference device test structure, the parallel test structure of the target device and the reference device, the cascade test structure of the target device and the reference device, and the auxiliary test structure preferably have a same basic structure with same signal input and output pads (S), grounded pads (G) and metal leads.

[0066] The following first embodiment takes the open-short de-embedding method widely used in the industry as an example, not limited to this, and uses an inductor device as the target device to judge the de-embedding accuracy of the performance parameters of the inductor device. In this embodiment, a MOM capacitor device is used as a reference device, and an open- circuit test structure and a short-circuit test structure are used as the auxiliary test structures, and a GSG (ground-signal-ground) structure is used to measure the S parameters. The present invention can be suitable to any de-embedding method in the prior arts, wherein, the target device and the reference device, which can be the same or different, may also be other reasonable devices commonly used in the field, such as some passive devices, e. g. capacitors, inductors, and resistors, and some active devices without external bias, e. g. transistor without external bias. And according to different de-embedding methods, the auxiliary test structure can also be replaced by such as an open test structure in the open de-embedding method, or an open test structure, a short test structure and a through test structure in the open-short-thru de-embedding method. The test structure can also be replaced by GS and GSGSG structures.

The First Embodiment

[0067] Referring to the FIG. 10, and in conjunction with reference to FIGS. 4-9, the method of judging the de-embedding accuracy of a RF device by using an introduced device is comprised of the steps:

[0068] Step S01: providing an inductor device and a MOM capacitor device to form an inductor test structure (FIG. 6), a capacitor test structure (FIG. 7), a parallel test structure of the inductor and the capacitor (FIG. 8), a cascade test structure of the inductor and the capacitor (FIG. 9), and providing an open-circuit test structure (FIG. 4) and a short-circuit test structure (FIG. 5) as the auxiliary test structure in the open-short de-embedding method.

[0069] Step S02: testing the S parameters (scattering parameters) of the above-mentioned six test structures by a vector network analyzer, respectively, i.e. a S parameter S.sub.DUT1, of the inductor test structure, a S parameter S.sub.DUT2, of the capacitor test structure, a S parameter S.sub.open of the open-circuit test structure, a S parameter S.sub.short of the short-circuit test structure, a S parameter S.sub.LCpar of the parallel test structure and a S parameter S.sub.LCser of the cascade test structure.

[0070] Step S03: converting the six S parameters tested above into their network parameters, then calculating and removing parasitic factors of the network parameters of the inductor test structure, the capacitor test structure, the parallel test structure and the cascade test structure, finally, the de-embedding S parameters of the above four test structures are obtained.

[0071] Specifically, converting above six S parameters into their Y parameters (admittance parameters), including a Y parameter Y.sub.DUT1 of the inductor test structure, a Y parameter Y.sub.DUT2 of the capacitor test structure, a Y parameter Y.sub.open of the open-circuit test structure, a Y parameter Y.sub.short of the short-circuit test structure, a Y parameter Y.sub.LCpar of the parallel test structure and a Y parameter Y.sub.LCser of the cascade test structure.

[0072] Then, the Z parameters (impedance parameters) of the inductor test structure, the capacitor test structure, the parallel test structure and the cascade test structure are obtained by using the conventional open-short de-embedding method. Specifically, the inductor test structure is taken as an example, according to above-obtained Y parameters

Y.sub.DUT1-open=Y.sub.DUT1−Y.sub.open Y.sub.short-open=Y.sub.short−Y.sub.open

[0073] then transfer Y.sub.DUT1-open and Y.sub.short-open into Z.sub.DUT1-open and Z.sub.short-open, the exact Z parameter of the inductor device is obtained by subtracting Z.sub.DUT1-open and Z.sub.short-open

Z.sub.L=Z.sub.DUT1-open−Z.sub.short-open

[0074] finally, transfer the Z.sub.L parameter into its S parameter, i.e., S.sub.L, which is the exact de-embedding S parameter of the inductor device obtained by the de-embedding method. The above calculation method is also suitable to the capacitor test structure, the parallel test structure and the cascade test structure. Therefore, the de-embedding S parameter S.sub.C of the capacitor test structure, the de-embedding S parameter S.sub.LCpar of the parallel test structure, and the de-embedding S parameter S.sub.LCser of the cascade test structure are also obtained.

[0075] According to the two-port network interconnection theory, when two two-port networks are connected in parallel, the below relationship is obtained, that is

[00004]$\begin{array}{cc}\left[Y\right]=\left[Y^{\prime }+Y^{″}\right]=\left[\begin{array}{cc}{Y}_{11}^{\prime }+Y_{11}^{″}& Y_{12}^{\prime }+Y_{12}^{″}\\ Y_{21}^{\prime }+Y_{21}^{″}& Y_{22}^{\prime }+Y_{22}^{″}\end{array}\right]& \left(1\right)\end{array}$

[0076] and when two two-port networks are connected in cascade, the below relationship is obtained, that is

[00005]$\begin{array}{cc}\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]=\left[\begin{array}{cc}{A}^{\prime }& B^{\prime }\\ C^{\prime }& D^{\prime }\end{array}\right]\left[\begin{array}{cc}{A}^{″}& B^{″}\\ C^{″}& D^{″}\end{array}\right]& \left(2\right)\end{array}$

[0077] Assuming the de-embedding is ideal, there should have an equation, that is

[00006]$\begin{array}{cc}\left[Y_{\mathrm{LCpar}}\right]=\left[Y_L+Y_C\right]=\left[\begin{array}{cc}{Y}_{L.Math..Math.11}+Y_{C.Math..Math.11}& Y_{L.Math..Math.12}+Y_{C.Math..Math.12}\\ Y_{L.Math..Math.21}+Y_{C.Math..Math.21}& Y_{L.Math..Math.22}+Y_{C.Math..Math.22}\end{array}\right]& \left(3\right)\end{array}$

[0078] and

[00007]$\begin{array}{cc}\left[\begin{array}{cc}{A}_{\mathrm{LCser}}& B_{\mathrm{LCser}}\\ C_{\mathrm{LCser}}& D_{\mathrm{LCser}}\end{array}\right]=\left[\begin{array}{cc}{A}_L& B_L\\ C_L& D_L\end{array}\right]\left[\begin{array}{cc}{A}_C& B_C\\ C_C& D_C\end{array}\right]& \left(4\right)\end{array}$

[0079] Where Y.sub.LCpar, Y.sub.L, and Y.sub.C are the de-embedding Y parameters of the parallel test structure, the inductor test structure, and the capacitor test structure, respectively. And A.sub.LCser, A.sub.L, and A.sub.C are the de-embedding ABCD parameters of the cascade test structure, the inductor test structure, and the capacitor test structure, respectively.

[0080] The formulas (3) and (4) can be used to judge the de-embedding accuracy and the applicable frequency range. Further, more intuitively, the above formulas (3) and (4) can be transformed into formulas having performance parameters of the inductor (or the capacitor), e. g., the equivalent inductance L.sub.11 and the quality factor Q.sub.11 of the first port of the inductor, etc. (the Multiple performance parameters can be used at the same time). There is

[00008]$\begin{array}{cc}{L}_{11}=\frac{\mathrm{imag}\left(1.Math.\text{/}.Math.Y_{11}\right)}{w},L_{22}=\frac{\mathrm{imag}\left(1.Math.\text{/}.Math.Y_{22}\right)}{w}.Math..Math.Q_{11}=-\frac{\mathrm{imag}\left(Y_{11}\right)}{\mathrm{real}\left(Y_{11}\right)},Q_{22}=-\frac{\mathrm{imag}\left(Y_{22}\right)}{\mathrm{real}\left(Y_{22}\right)}& \left(5\right)\end{array}$

[0081] Thus, there are three ways in which the equivalent inductance is obtained. Correspondingly, three different results of the equivalent inductance can be obtained. Through calculating the error value of the three equivalent inductances, the de-embedding accuracy and the applicable frequency range of the de-embedding method of the present embodiment are judged. Specifically, the Step S04 also includes:

[0082] Step S041: converting the de-embedding S parameter S.sub.L of the inductor test structure into its Y parameter Y.sub.11, and obtaining the first result value L.sub.11 of the equivalent inductance of the inductor by substituting Y.sub.11 into the formula (5).

[0083] Step S042: converting the de-embedding S parameter S.sub.C of the capacitor test structure and the de-embedding S parameter S.sub.LCpar of the parallel test structure into their Y parameters Y.sub.C and Y.sub.LCpar; and then obtaining the Y parameter Y.sub.L of the inductor according to the formula (3) based on the two-port network interconnection theory; finally, obtaining the second result value L.sub.11.sub._.sub.par of the equivalent inductance of the inductor according to the formula (5).

[0084] Step S043: converting the de-embedding S parameter S.sub.C of the capacitor test structure and the de-embedding S parameter S.sub.LCpar of the cascade test structure in to their ABCD parameters A.sub.C and L.sub.LCser; and then obtaining the ABCD parameter A.sub.L of the inductor according to the formula (4) based on the two-port network interconnection theory; finally, obtaining the third result value L.sub.11.sub._.sub.ser of the equivalent inductance of the inductor according to the formula (5).

[0085] Step S05: obtaining error values by calculating the differences of the obtained L.sub.11 and L.sub.11.sub._.sub.par, L.sub.11.sub._.sub.par and L.sub.11.sub._.sub.ser, and L.sub.11 and L.sub.11.sub._.sub.ser, and comparing the error values with the preset value to judge the accuracy and the applicable frequency range of the de-embedding method.

[0086] Specifically, error values is calculated by the following formula, that is

[00009]${\Delta }_1=\left|L_{11}-L_{1_{—}.Math.\mathrm{par}}\right|.Math.{\Delta }_2=\left|L_{11}-L_{{11}_{—}.Math.\mathrm{ser}}\right|.Math.{\Delta }_3=\left|L_{{11}_{—}.Math.\mathrm{ser}}-L_{{11}_{—}.Math.\mathrm{par}}\right|.Math.\Delta =\min \left({\Delta }_1,{\Delta }_2,{\Delta }_3\right)$

[0087] The minimum error value can be obtained. If the minimum error is lower than the preset relative error threshold, it is judged that the accuracy and the applicable frequency range of the de-embedding method both are acceptable; if the minimum error is higher than the preset relative error threshold, it is judged that the accuracy and applicable frequency range of the de-embedding method both are unacceptable.

[0088] In other embodiments, there are other methods of judging the consistency of the three results to measure the accuracy of the embedded method, such as relative error, percentage error, etc., not limited to the absolute error of this embodiment.

[0089] In the practical application, there are a lot of de-embedding methods, including the open de-embedding method, the open-short de-embedding method, the open-thru de-embedding method, the open-short-thru de-embedding method, and etc. So, the Step S01 also includes building test structures corresponding to the used de-embedding method, e. g., one or more of an open-circuit test structure, a short-circuit test structure and a through test structure. The Step S02 also includes testing the S parameters of the test structures corresponding to the used de-embedding method, e. g., one or more of S parameters of the open-circuit test structure, the short-circuit test structure and the through test structure.

[0090] It should be noted that for other de-embedding methods, e.g., the open de-embedding method, the open-thru de-embedding method, and the open-short-thru de-embedding method, the corresponding auxiliary test structures and the corresponding formulas are used to calculate the S parameters and the network parameters, and then the corresponding sub-circuit model characterizing parasitic factors of one de-embedding method is used to calculate the de-embedding S parameters according to the above-received network parameters, so as to remove the corresponding parasitic factors of one de-embedding method. Wherein, the used calculation methods and formulas may have been obtained by the skilled person in the field by referring the prior art or the present invention, so will not be described again.

[0091] In the practical application, the target device and the introduced device, which can be the same or not, may be one of resistors, inductors, capacitors, transistors without external bias, respectively. The present invention is suitable to the all above-mentioned devices to judge the de-embedding accuracy and the applicable frequency range of a certain de-embedding method.

[0092] In the practical application, interconnection leads in the multi-device interconnect structure should be minimized to reduce errors introduced by interconnecting multiple devices. In order to facilitate testing and to ensure the accuracy of the test, all test structures have a same basic structure, i.e., with the same signal input and output pads, ground pads and metal leads.