TRANSFORMER

Abstract

A transformer includes a front stage circuit and a rear stage circuit. As a front stage circuit, a switch series unit, which is connected in parallel to a power supply, includes odd-numbered switches and even-numbered switches alternately turned ON. Mutual connection points of the respective switches and points at both ends of the switch series unit are regarded as m nodes in total. Capacitors are provided on at least one of a first electrical path combining odd nodes to lead them to a first output port, and a second electrical path combining even nodes to lead them to a second output port. The capacitors are present so as to correspond to at least (m−1) nodes. The rear stage circuit includes an element series unit, which is composed of a pair of semiconductor elements connected in series to each other for conducting operations of mutually opposite polarities, and necessary inductors.

Claims

1. A transformer provided between a power supply and a load, and composed of a front stage circuit and a rear stage circuit, the transformer comprising: as the front stage circuit, a switch series unit composed of a plurality of switches, as many as a multiple of 2, connected in series with each other, the plurality of switches including odd-numbered switches and even-numbered switches as seen from one of both ends of the switch series unit, the odd-numbered switches and the even-numbered switches being configured to be alternately turned ON, the switch series unit as a whole being connected in parallel to the power supply, and assuming that mutual connection points of the respective switches and points at the both ends of the switch series unit are regarded as m nodes in total and the nodes are seen in order of 1 to m from one of the both ends of the switch series unit, capacitors provided on at least one electrical path of a first electrical path and a second electrical path, the first electrical path being configured to combine odd nodes and lead the odd nodes to a first output port, the second electrical path being configured to combine even nodes and lead the even nodes to a second output port, the capacitors being present so as to correspond to at least (m−1) nodes; as the rear stage circuit, an element series unit composed of a pair of semiconductor elements that are connected in series to each other and perform conducting operations of mutually opposite polarities, one of both ends of the element series unit being connected to the first output port while the other end thereof being connected to the second output port, and inductors provided on at least one electrical path of a third electrical path and a fourth electrical path, the third electrical path being configured to combine two nodes that are points at the both ends of the element series unit and to lead the two nodes to one of both ends of the load, the fourth electrical path being configured to lead one node that is a mutual connection point of the pair of semiconductor elements to the other end of the load, the inductors being present so as to correspond to at least two nodes of the three nodes in total; and a control section configured to control ON/OFF operations of the switches.

2. The transformer according to claim 1, wherein assuming that a time period from a dead-time start time to a dead-time end time is a dead time τ, the dead-time start time being a time at which control for the odd-numbered switches and control for the even-numbered switches are both turned OFF, the dead-time end time being a time at which control for either the odd-numbered switches or the even-numbered switches is turned ON, the control section, after the dead-time start time, calculates a first half time τ.sub.1 and a second half time τ.sub.2, the first half time τ.sub.1 being calculated on the basis of electric charges that move from the inductors to floating capacitances of the switches while one of the semiconductor elements is in a conductive state, the second half time τ.sub.2 being calculated on the basis of electric charges that move from the inductors to the floating capacitances of the switches while the other semiconductor element is in a conductive state, and the control section determines the dead time τ on the basis of the first half time τ.sub.1 and the second half time τ.sub.2.

3. The transformer according to claim 2, wherein the control section terminates the dead time τ before the electric charges that have moved to the floating capacitances return to the inductors.

4. The transformer according to claim 3, wherein assuming that a switching cycle of the switches is T, an inductance of the inductors is L, and a resistance value of the load is R.sub.3, the dead time τ satisfies the following relationship:
τ.sub.1+τ.sub.2≦τ≦τ.sub.0+(τ.sub.2/2)+τ.sub.1 where ${\tau }_0=\frac{T}{4}-\frac{L}{2.Math..Math.R_3}$ ${\tau }_1=\frac{T}{2}+\frac{L}{.Math.R_3}-\frac{1}{2}.Math.\sqrt{{\left(T+\frac{2.Math.L}{R_3}\right)}^2-32.Math..Math.L.Math.\underset{n=1}{\overset{n}{.Math.}}.Math..Math.C_{\mathrm{nDS}}}$ ${\tau }_2=\frac{T}{2}-\frac{L}{.Math.R_3}-\frac{1}{2}.Math.\sqrt{{\left(T-\frac{2.Math.L}{R_3}\right)}^2-32.Math..Math.L.Math.\underset{n=1}{\overset{n}{.Math.}}.Math..Math.C_{\mathrm{nDS}}}$ where n denotes the number of floating capacitances C.sub.DS, C.sub.nDS denotes an n-th floating capacitance, a sign of a value in each radical sign is plus, and τ.sub.1<τ.sub.2 is satisfied.

5. The transformer according to claim 3, wherein assuming that a switching cycle of the switches is T, an inductance, of inductances of the inductors, that is dominant for the dead time is L.sub.1, and a resistance value of the load is R.sub.3, the dead time τ satisfies the following relationship:
τ.sub.1+τ.sub.2≦τ≦τ.sub.0+τ.sub.1 where ${\tau }_0=\frac{T}{4}-\frac{L_1}{4.Math.R_3}$ ${\tau }_1=\frac{T}{4}+\frac{L_1}{.Math.4.Math.R_3}-\frac{1}{4}.Math.\sqrt{{\left(T+\frac{L_1}{R_3}\right)}^2-32.Math..Math.L_1.Math.\underset{n=1}{\overset{n}{.Math.}}.Math..Math.C_{\mathrm{nDS}}}$ ${\tau }_2=\frac{T}{4}-\frac{L_1}{.Math.4.Math.R_3}-\frac{1}{4}.Math.\sqrt{{\left(T-\frac{L_1}{R_3}\right)}^2-32.Math..Math.L_1.Math.\underset{n=1}{\overset{n}{.Math.}}.Math..Math.C_{\mathrm{nDS}}}$ where n denotes the number of floating capacitances C.sub.DS, C.sub.nDS denotes an n-th floating capacitance, a sign of a value in each radical sign is plus, and τ.sub.1<τ.sub.2 is satisfied.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0012] FIG. 1 is a circuit diagram showing a transformer as a basic form of a transformer according to an embodiment.

[0013] FIG. 2 is a circuit diagram in which (a) shows a substantial connection state when, of four switches shown in FIG. 1, two switches on the upper side are ON and two switches on the lower side are OFF, and (b) shows, in a step-like shape, the same circuit diagram as in (a).

[0014] FIG. 3 is a circuit diagram in which (a) shows a substantial connection state when, of four switches shown in FIG. 1, two switches on the lower side are ON and two switches on the upper side are OFF, and (b) shows, in a step-like shape, the same circuit diagram as in (a).

[0015] FIG. 4 is a waveform diagram in which an upper graph shows input voltage to the transformer and a lower graph shows input current to the transformer.

[0016] FIG. 5 is a waveform diagram showing voltage v.sub.m and current i.sub.m at an intermediate stage of transformation.

[0017] FIG. 6 is a waveform diagram in which an upper graph shows output voltage from the transformer and a lower graph shows output current from the transformer.

[0018] FIG. 7 is a circuit diagram showing an example of a transformer that is developed to be more practical.

[0019] FIG. 8 is a circuit diagram showing topological variations of a main part of a front stage circuit in a “2C2L” transformer.

[0020] FIG. 9 is a circuit diagram showing topological variations of a main part of a rear stage circuit.

[0021] FIG. 10 is a diagram showing a main part of a front stage circuit in a “4C2L” transformer.

[0022] FIG. 11 is a diagram showing circuit variations of a first electrical path in a case where the total number of capacitors is not reduced in the first electrical path (solid line).

[0023] FIG. 12 is a diagram showing other circuit variations of the first electrical path in a case where the total number of capacitors is not reduced in the first electrical path (solid line).

[0024] FIG. 13 is a diagram showing circuit variations of the first electrical path in a case where the total number of capacitors is reduced by one in the first electrical path (solid line) shown in FIG. 10.

[0025] FIG. 14 is a diagram showing circuit variations of a second electrical path (dashed line) shown in FIG. 10.

[0026] FIG. 15 is a diagram showing a main part of a front stage circuit in a “6C2L” transformer.

[0027] FIG. 16 is a diagram showing circuit variations in a case where the total number of capacitors are reduced by one in the first electrical path (solid line) or the second electrical path (dashed line) shown in FIG. 15.

[0028] FIG. 17 is a graph showing a change in switching voltage (drain-to-source voltage) when odd-numbered or even-numbered switches change from ON to OFF and change to ON again.

[0029] FIG. 18 is a graph showing the change from OFF to ON shown in FIG. 17, with the time on the horizontal axis being scaled up.

[0030] FIG. 19 is a graph showing the relationship between ZVT and the length of dead time which is set to be “long”, “medium”, and “short”.

[0031] FIG. 20 is a circuit diagram in which diodes and bleeder resistors shown in FIG. 7 are omitted, and instead, floating capacitances possessed by the respective switches are shown.

[0032] FIG. 21 is a circuit diagram of the same background as FIG. 20, in which a path of current in a second half time τ2 is also shown.

[0033] FIG. 22 is a graph showing examples of waveforms of currents that flow in inductors.

[0034] FIG. 23 is an enlarged view showing portions near the peaks of the waveforms shown in FIG. 22.

[0035] FIG. 24 is a diagram showing the waveforms shown in FIG. 23 extended in the time-axis direction (rightward direction).

[0036] FIG. 25 is a graph showing the relationship between dead time τ [ns] and efficiency [%] in the case of condition 1.

[0037] FIG. 26 is a graph showing the relationship between dead time τ [ns] and output power [W] of the transformer in the case of condition 1.

[0038] FIG. 27 is a graph showing the relationship between dead time τ [ns] and efficiency [%] in the case of condition 2.

[0039] FIG. 28 is a graph showing the relationship between dead time τ [ns] and output power [W] of the transformer in the case of condition 2.

[0040] FIG. 29 is a graph showing the relationship between dead time τ [ns] and efficiency [%] in the case of condition 3.

[0041] FIG. 30 is a graph showing the relationship between dead time τ [ns] and output power [W] of the transformer in the case of condition 3.

[0042] FIG. 31 is a graph showing the relationship between dead time τ [ns] and efficiency [%] in the case of condition 4.

[0043] FIG. 32 is a graph showing the relationship between dead time τ [ns] and output power [W] of the transformer in the case of condition 4.

[0044] FIG. 33 is a graph showing the relationship between dead time τ [ns] and efficiency [%] in the case of condition 5.

[0045] FIG. 34 is a graph showing the relationship between dead time τ [ns] and output power [W] of the transformer in the case of condition 5.

[0046] FIG. 35 is a graph showing the relationship between dead time τ [ns] and efficiency [%] in the case of condition 6.

[0047] FIG. 36 is a graph showing the relationship between dead time τ [ns] and output power [W] of the transformer in the case of condition 6.

[0048] FIG. 37 is a graph showing the relationship between dead time τ [ns] and efficiency [%] in the case of condition 7.

[0049] FIG. 38 is a graph showing the relationship between dead time τ [ns] and output power [W] of the transformer in the case of condition 7.

[0050] FIG. 39 is a graph showing the relationship between dead time τ [ns] and efficiency [%] in the case of condition 8.

[0051] FIG. 40 is a graph showing the relationship between dead time τ [ns] and output power [W] of the transformer in the case of condition 8.

[0052] FIG. 41 is a graph showing the relationship between dead time τ [ns] and efficiency [%] in the case of condition 9.

[0053] FIG. 42 is a graph showing the relationship between dead time τ [ns] and output power [W] of the transformer in the case of condition 9.

[0054] FIG. 43 is a graph showing the relationship between dead time τ [ns] and efficiency [%] in the case of condition 10.

[0055] FIG. 44 is a graph showing the relationship between dead time τ [ns] and output power [W] of the transformer in the case of condition 10.

DESCRIPTION OF EMBODIMENTS

Summary of the Embodiment

[0056] The summary of the embodiment of the present invention includes at least the following.

[0057] (1) A transformer provided between a power supply and a load is composed of a front stage circuit and a rear stage circuit.

[0058] The transformer includes, as the front stage circuit, (a) a switch series unit composed of a plurality of switches, as many as a multiple of 2, connected in series with each other, the plurality of switches including odd-numbered switches and even-numbered switches as seen from one of both ends of the series unit, the odd-numbered switches and the even-numbered switches being configured to be alternately turned ON, the switch series unit as a whole being connected in parallel to the power supply, and (b) assuming that mutual connection points of the respective switches and points at the both ends of the switch series unit are regarded as m nodes in total and the nodes are seen in order of 1 to m from one of the both ends of the switch series unit, capacitors provided on at least one electrical path of a first electrical path and a second electrical path, the first electrical path being configured to combine odd nodes and lead the odd nodes to a first output port, the second electrical path being configured to combine even nodes and lead the even nodes to a second output port, the capacitors being present so as to correspond to at least (m−1) nodes. The capacitors are present so as to correspond to at least (m−1) nodes.

[0059] In addition, the transformer includes, as the rear stage circuit, (c) an element series unit composed of a pair of semiconductor elements that are connected in series to each other and perform conducting operations of mutually opposite polarities, one of both ends of the element series unit being connected to the first output port while the other end thereof being connected to the second output port, and (d) inductors provided on at least one electrical path of a third electrical path and a fourth electrical path, the third electrical path being configured to combine two nodes that are points at the both ends of the element series unit and to lead the two nodes to one of both ends of the load, the fourth electrical path being configured to lead one node that is a mutual connection point of the pair of semiconductor elements to the other end of the load. The inductors are present so as to correspond to at least two nodes of the three nodes in total.

[0060] The transformer further includes a control section configured to control ON/OFF operations of the switches.

[0061] The transformer configured as described in above (1) can perform transformation by the circuit configuration including the front stage circuit and the rear stage circuit and by switching. Using this transformer as a power transformer makes it unnecessary to use a conventional transformer including a coil, an iron core, and the like. Therefore, it is possible to realize drastic size reduction and weight reduction of the transformer, and thereby realize cost reduction accordingly. In addition, problems of parasitic capacitance and occurrence of magnetic field leakage, which arise in a high-frequency transformer, are also solved, and thus a transformer with low loss can be realized. As for a power supply, either an AC power supply or a DC power supply is applicable.

[0062] (2) Further, in the transformer described in the above (1), it is assumed that a time period from a dead-time start time to a dead-time end time is a dead time τ, the dead-time start time being a time at which control for the odd-numbered switches and control for the even-numbered switches are both turned OFF, the dead-time end time being a time at which control for either the odd-numbered switches or the even-numbered switches is turned ON. In this case, the control section, after the dead-time start time, may calculate a first half time τ.sub.1 and a second half time τ.sub.2, the first half time τ.sub.1 being calculated on the basis of electric charges that move from the inductors to floating capacitances of the switches while one of the semiconductor elements is in a conductive state, the second half time τ.sub.2 being calculated on the basis of electric charges that move from the inductors to the floating capacitances of the switches while the other semiconductor element is in a conductive state, and the control section may determine the dead time τ on the basis of the first half time τ.sub.1 and the second half time τ.sub.2.

[0063] In this case, an appropriate dead time τ can be determined on the basis of the times τ.sub.1 and τ.sub.2 calculated focusing on movement of electric charges during the dead time, thereby realizing zero volt transition (ZVT).

[0064] (3) Further, in the transformer described in the above (2), the control section preferably terminates the dead time τ before the electric charges that have moved to the floating capacitances return to the inductors.

[0065] When the electric charges that have moved to the floating capacitances return, switching voltage increases again. However, by terminating the dead time τ before the returning of the electric charges, the switching voltage can be prevented from increasing again.

[0066] (4) Further, in the transformer as described in the above (3), assuming that a switching cycle of the switches is T, an inductance of the inductors is L, and a resistance value of the load is R.sub.3, the dead time τ satisfies the following relationship:

τ.sub.1+τ.sub.2≦τ≦τ.sub.0+(τ.sub.2/2)+τ.sub.2

[0067] where

[00001]${\tau }_0=\frac{T}{4}-\frac{L}{2.Math.T_3}$${\tau }_1=\frac{T}{2}+\frac{L}{R_3}-\frac{1}{2}.Math.\sqrt{{\left(T+\frac{2.Math.L}{R_3}\right)}^2-32.Math.L.Math.\underset{n=1}{\overset{n}{.Math.}}.Math.C_{\mathrm{nDS}}}$${\tau }_2=\frac{T}{2}-\frac{L}{R_3}-\frac{1}{2}.Math.\sqrt{{\left(T+\frac{2.Math.L}{R_3}\right)}^2-32.Math.L.Math.\underset{n=1}{\overset{n}{.Math.}}.Math.C_{\mathrm{nDS}}}$

[0068] where n denotes the number of floating capacitances C.sub.DS, C.sub.nDS denotes an n-th floating capacitance, a sign of a value in each radical sign is plus, and τ.sub.1<τ.sub.2 is satisfied.

[0069] In this case, an optimum range of the dead time τ can be precisely determined, thereby reliably realizing zero voltage transition.

[0070] (5) Depending on the topology of the rear stage circuit, the following configuration may be taken instead of the above (4).

[0071] Assuming that a switching cycle of the switches is T, an inductance, of the inductances of the inductors, that is dominant for the dead time is L.sub.1, and a resistance value of the load is R.sub.3, the dead time τ satisfies the following relationship:

τ.sub.1+τ.sub.2≦τ≦τ.sub.0+τ.sub.1

where

[00002]${\tau }_0=\frac{T}{4}-\frac{L_1}{4.Math..Math.R_3}$${\tau }_1=\frac{T}{4}+\frac{L_1}{4.Math..Math.R_3}-\frac{1}{4}.Math.\sqrt{{\left(T+\frac{L_1}{R_3}\right)}^2-32.Math..Math.L_1.Math.\underset{n=1}{\overset{n}{.Math.}}.Math..Math.C_{\mathrm{nDS}}}$${\tau }_2=\frac{T}{4}-\frac{L_1}{4.Math..Math.R_3}-\frac{1}{4}.Math.\sqrt{{\left(T-\frac{L_1}{R_3}\right)}^2-32.Math..Math.L_1.Math.\underset{n=1}{\overset{n}{.Math.}}.Math..Math.C_{\mathrm{nDS}}}$

[0072] where n denotes the number of floating capacitances C.sub.DS, C.sub.nDS denotes an n-th floating capacitance, a sign of a value in each radical sign is plus, and τ.sub.1<τ.sub.2 is satisfied.

DETAILS OF EMBODIMENTS

[0073] Hereinafter, an embodiment will be described in detail with reference to the drawings.

[0074] <<Example of Fundamental Circuit>>

[0075] FIG. 1 is a circuit diagram showing a transformer 1 as a basic form of a transformer according to the present embodiment. In FIG. 1, the transformer 1 is provided between an AC power supply 2 and a load R (R also denotes a resistance value). The transformer 1 includes a pair of capacitors C1 and C2, a pair of inductors L1 and L2, four switches S.sub.r1, S.sub.r2, S.sub.b1, and S.sub.b2, and a control section 3 which performs ON/OFF control of the switches S.sub.r1, S.sub.r2, S.sub.b1, and S.sub.b2. A switching frequency of the control section 3 is, for example, about 1 MHz.

[0076] The pair of capacitors C1 and C2 may have the same capacitance value, or may have different capacitance values. The same applies to the inductance values of the pair of inductors L1 and L2.

[0077] The switches S.sub.r1, S.sub.r2, S.sub.b1, and S.sub.b2 and the control section 3 form a switch device 4 which switches the state of circuit connection of the transformer 1. The switches S.sub.r1 and S.sub.r2 operate in synchronization with each other, and the switches S.sub.b1 and S.sub.b2 operate in synchronization with each other. The pair of switches S.sub.r1 and S.sub.r2 and the pair of switches S.sub.b1 and S.sub.b2 operate so as to be alternately turned ON exclusively from each other. The switches S.sub.r1, S.sub.r2, S.sub.b1, and S.sub.b2 are semiconductor switching elements formed by an SiC element or a GaN element, for example. The SiC element or the GaN element allows faster switching than an Si element, for example. In addition, sufficient withstand voltage (which can be even 6 kV per element, for example) can be obtained without connecting multiple stages of such elements.

[0078] In FIG. 1, the pair of capacitors C1 and C2 are connected in series to each other via a connection point M1. The AC power supply 2 is connected between both ends of this series unit. Input voltage v.sub.in is applied to the series unit of the pair of capacitors C1 and C2, so that input current i.sub.in flows.

[0079] The pair of inductors L1 and L2 are connected in series to each other via a connection point M2. Between both ends of this series unit, input voltage v.sub.m is applied via the capacitors C1 and C2, so that current i.sub.m flows. When one of the switches S.sub.r2 and S.sub.b2 is ON, current flows in the load R. Here, voltage applied to the load R is v.sub.out, and output current flowing from the transformer 1 to the load R is i.sub.out.

[0080] In FIG. 2, (a) is a circuit diagram showing a substantial connection state when, among the four switches S.sub.r1, S.sub.r2, S.sub.b1, and S.sub.b2 in FIG. 1, the two switches S.sub.r1 and S.sub.r2 on the upper side are ON, and the two switches S.sub.b1 and S.sub.b2 on the lower side are OFF. In the drawing, the switch device 4 in FIG. 1 is not shown. In FIG. 2, (b) is a circuit diagram showing, in a step-like shape, the same circuit diagram as in (a).

[0081] On the other hand, in FIG. 3, (a) is a circuit diagram showing a substantial connection state when, among the four switches S.sub.r1, S.sub.r2, S.sub.b1, and S.sub.b2, the two switches S.sub.b1 and S.sub.b2 on the lower side are ON, and the two switches S.sub.r1 and S.sub.r2 on the upper side are OFF. In FIG. 3, (b) is a circuit diagram showing, in a step-like shape, the same circuit diagram as in (a).

[0082] While the states shown in FIG. 2 and FIG. 3 are alternately repeated, voltage obtained via the connection point M1 of the series unit of the capacitors C1 and C2 becomes voltage obtained via the connection point M2 of the series unit of the inductors L1 and L2. That is, the circuit configuration is composed of a front stage circuit including the pair of capacitors C1 and C2, and a rear stage circuit including the pair of inductors L1 and L2, and at each stage, the polarity of output relative to input is inverted through switching. Regarding the capacitors C1 and C2, the directions of currents thereof are alternately inverted through switching. Regarding the inductors L1 and L2, the directions of voltages thereof are alternately inverted through switching.

[0083] Here, it can be estimated that the input voltage becomes ¼ when outputted. This will be logically proved below.

[0084] In FIG. 2, v.sub.in is input voltage from the AC power supply 2, v.sub.out is voltage applied to the load R, v.sub.1 is voltage applied to the capacitor C1, v.sub.2 is voltage applied to the capacitor C2, i.sub.1 is current flowing through the inductor L1, and i.sub.2 is current flowing through the inductor L2. In this case, the following expressions are satisfied.

[0085] For simplifying calculation, it is assumed that the capacitors C1 and C2 have the same capacitance value C, and the inductors L1 and L2 have the same inductance value L.

[00003]$-v_{\mathrm{in}}=v_1-v_2.Math.-\frac{v_{\mathrm{out}}}{R}=i_1+i_2$$C.Math.\frac{d}{\mathrm{dt}}.Math.\left(v_1+v_2\right)=-i_2$$L.Math.\frac{d}{\mathrm{dt}}=\left(i_1-i_2\right)=-v_1$$v_{\mathrm{out}}=L.Math.\frac{d}{\mathrm{dt}}.Math.i_1$

[0086] The above expressions are converted into expressions of v.sub.1, i.sub.1, and i.sub.2, as follows.

[00004]$L.Math.\frac{d}{\mathrm{dt}}.Math.i_1=-R\left(i_1+i_2\right)$$L.Math.\frac{d}{\mathrm{dt}}.Math.i_2=v_1-R\left(i_1+i_2\right)$$2.Math..Math.C.Math.\frac{d}{\mathrm{dt}}.Math.v_1=-i_2-.Math.C.Math.\frac{d}{\mathrm{dt}}.Math.v_{\mathrm{in}}$

[0087] Here, if Ri.sub.1=v.sub.3 and Ri.sub.2=v.sub.4 are set, the following equation 1 is obtained.

[00005]$\begin{array}{cc}\frac{d}{\mathrm{dt}}.Math.v_3=-\frac{R}{L}.Math.\left(v_3+v_4\right).Math..Math.\frac{d}{\mathrm{dt}}.Math.v_4=\frac{R}{L}.Math.\left(v_1-v_3-v_4\right).Math..Math.\frac{d}{\mathrm{dt}}.Math.v_1=-\frac{1}{2.Math..Math.\mathrm{CR}}.Math.v_4-\frac{1}{2}.Math.\frac{d}{\mathrm{dt}}.Math.v_{\mathrm{in}}& \left(\mathrm{Equation}.Math..Math.1\right)\end{array}$

[0088] In FIG. 3, as in FIG. 2, v.sub.in is input voltage from the AC power supply 2, v.sub.out is voltage applied to the load R, v.sub.1 is voltage applied to the capacitor C1, v.sub.2 is voltage applied to the capacitor C2, i.sub.1 is current flowing through the inductor L1, and i.sub.2 is current flowing through the inductor L2. In this case, the following expressions are satisfied.

[00006]$-v_{\mathrm{in}}=v_1-v_2.Math.-\frac{v_{\mathrm{out}}}{R}=i_1+i_2$$C.Math.\frac{d}{\mathrm{dt}}.Math.\left(v_1+v_2\right)=i_1$$L.Math.\frac{d}{\mathrm{dt}}=\left(i_1-i_2\right)=-v_2$$v_{\mathrm{out}}=L.Math.\frac{d}{\mathrm{dt}}.Math.i_2$

[0089] The above expressions are converted into expressions of v.sub.1, i.sub.1, and i.sub.2, as follows.

[00007]$L.Math.\frac{d}{\mathrm{dt}}.Math.i_2=-R\left(i_1+i_2\right)$$L.Math.\frac{d}{\mathrm{dt}}.Math.i_1=-v_1-v_{\mathrm{in}}-R\left(i_1+i_2\right)$$2.Math..Math.C.Math.\frac{d}{\mathrm{dt}}.Math.v_1=i_1-.Math.C.Math.\frac{d}{\mathrm{dt}}.Math.v_{\mathrm{in}}$

[0090] Here, if Ri.sub.1=v3 and Ri.sub.2=v4 are set, the following equation 2 is obtained.

[00008]$\begin{array}{cc}\frac{d}{\mathrm{dt}}.Math.v_4=-\frac{R}{L}.Math.\left(v_3+v_4\right).Math..Math.\frac{d}{\mathrm{dt}}.Math.v_3=-\frac{R}{L}.Math.\left(v_1+v_3+v_4+v_{\mathrm{in}}\right).Math..Math.\frac{d}{\mathrm{dt}}.Math.v_1=\frac{1}{2.Math..Math.\mathrm{CR}}.Math.v_3-\frac{1}{2}.Math.\frac{d}{\mathrm{dt}}.Math.v_{\mathrm{in}}& \left(\mathrm{Equation}.Math..Math.2\right)\end{array}$

[0091] Here, it is difficult to derive an exact solution from the above two states. Therefore, the following conditions are set within a range that is considered to cause no practical problem.

[0092] (1) At a frequency f.sub.o of input voltage, the impedance (reactance) of L is sufficiently smaller than the resistance value. That is, 2πf.sub.oL<<R is satisfied. Preferably, a difference represented by the inequality sign is, for example, one-digit difference or greater, or more preferably, two-digit difference or greater. Thus, more stable transformation operation with less distortion can be obtained.

[0093] (2) At the switching frequency fs, the impedance (reactance) of C is sufficiently smaller than the resistance value R, but at the frequency f.sub.o of input voltage, the impedance (reactance) of C is sufficiently greater than the resistance value. That is, 1/(2πfsC)<<R<<1/(2πf.sub.oC) is satisfied. Preferably, a difference represented by the inequality sign is, for example, one-digit difference or greater, or more preferably, two-digit difference or greater. Thus, more stable transformation operation with less distortion can be obtained.

[0094] (3) In one cycle of switching, input voltage hardly varies.

[0095] Therefore, v.sub.in(t+Δt)=v.sub.in(t) (0≦Δt≦1/fs)

[0096] (4) The system is steady, and returns to the same state with a period (1/fs).

[0097] Therefore, v.sub.x(t+(1/fs))≈v.sub.x(t) (x=1, 2, 3, 4)

[0098] If the switches S.sub.r1 and S.sub.r2 become ON during a period of 0≦t≦(½fs) and the switches S.sub.b1 and S.sub.b2 become ON during a period of (½fs) <t<(1/fs), the following equation 3 is obtained by primary approximation of equation 1 about t=0. In addition, the following equation 4 is obtained by primary approximation of equation 2 about t=(½fs).

[00009]$\begin{array}{cc}.Math.v_3\left(\frac{1}{2.Math..Math.f_s}\right)\approx v_3\left(0\right)-\frac{R}{2.Math..Math.f_s.Math.L}.Math.\left\{v_3\left(0\right)+v_4\left(0\right)\right\}.Math..Math..Math.v_4\left(\frac{1}{2.Math..Math.f_s}\right)\approx v_4\left(0\right)+\frac{R}{2.Math..Math.f_s.Math.L}.Math.\left\{v_1\left(0\right)-v_3\left(0\right)-v_4\left(0\right)\right\}.Math..Math.v_1\left(\frac{1}{2.Math..Math.f_s}\right)\approx v_1\left(0\right)-\frac{1}{4.Math..Math.f_s.Math.\mathrm{CR}}.Math.v_4\left(0\right)-\frac{1}{2}.Math.\left\{v_{\mathrm{in}}\left(\frac{1}{2.Math..Math.f_s}\right)-v_{\mathrm{in}}\left(0\right)\right\}& \left(\mathrm{Equation}.Math..Math.3\right)\end{array}$

[0099] In the above equation 3, the third term on the right-hand side of the expression at the third stage, i.e., −(½){v.sub.in(½fs)−v.sub.in(0)} is sufficiently close to zero.

[00010]$\begin{array}{cc}.Math.v_4\left(\frac{1}{.Math.f_s}\right)\approx v_4\left(\frac{1}{2.Math..Math.f_s}\right)-\frac{R}{2.Math..Math.f_s.Math.L}.Math.\left\{v_3\left(\frac{1}{2.Math..Math.f_s}\right)+v_4\left(\frac{1}{2.Math..Math.f_s}\right)\right\}.Math..Math.v_3\left(\frac{1}{.Math.f_s}\right)\approx v_3\left(\frac{1}{2.Math..Math.f_s}\right)-\frac{R}{2.Math..Math.f_s.Math.L}.Math.\left\{v_1\left(\frac{1}{2.Math..Math.f_s}\right)+v_3\left(\frac{1}{2.Math..Math.f_s}\right)+v_4\left(\frac{1}{2.Math..Math.f_s}\right)+v_{\mathrm{in}}\left(\frac{1}{2.Math..Math.f_s}\right)\right\}.Math..Math.v_1\left(\frac{1}{f_s}\right)\approx v_1\left(\frac{1}{2.Math..Math.f_s}\right)+\frac{1}{4.Math..Math.f_s.Math.\mathrm{CR}}.Math.v_3\left(\frac{1}{2.Math..Math.f_s}\right)-\frac{1}{2}.Math.\left\{v_{\mathrm{in}}\left(\frac{1}{.Math.f_s}\right)-v_{\mathrm{in}}\left(\frac{1}{2.Math..Math.f_s}\right)\right\}& \left(\mathrm{Equation}.Math..Math.4\right)\end{array}$

[0100] In the above equation 4, the third term on the right-hand side of the expression at the third stage, i.e., −(½){v.sub.in(1/fs)=v.sub.in(½fs)} is sufficiently close to zero.

[0101] Here, if v.sub.1, v.sub.3, and v.sub.4 in equations 3 and 4 are each linked, that is, v.sub.1(0)=v.sub.1(1/fs), v.sub.3(0)=v.sub.3(1/fs), and v.sub.4(0)=v.sub.4 (1/fs) are used, and in addition, if ΔT=1/(2 fs) is set, the following expressions are satisfied.

−v.sub.3(0)−v.sub.4(0)≈v.sub.1(ΔT)+v.sub.3(ΔT)+v.sub.4(ΔT)+v.sub.in(ΔT)

v.sub.1(0)−v.sub.3(0)−v.sub.4(0)≈v.sub.3(ΔT)+v.sub.4(ΔT)

v.sub.4(0)≈v.sub.3(ΔT)

[0102] If a sum of the expressions at the first and second stages shown above (just above) is taken, the following expression is obtained.

v.sub.in=−2{v.sub.3(0)+v.sub.4(0)+v.sub.3(ΔT)+v.sub.4(ΔT)}+v.sub.1(0)−v.sub.1(ΔT)

[0103] Here, from the expression at the third stage in equation 3, v.sub.1(0)−v.sub.1(ΔT)=(1/(4 fsCR))v.sub.4(0) is obtained.

[0104] In addition, −v.sub.out=R(i.sub.1+i.sub.2)=v.sub.3+v.sub.4 is obtained, and this expression is always satisfied. Therefore, the following conclusive expression is obtained.

[00011]$v_{\mathrm{in}}\left(\Delta .Math..Math.T\right)\approx 4.Math..Math.v_{\mathrm{out}}\left(\Delta .Math..Math.T\right)+\frac{1}{4.Math..Math.f_s.Math.\mathrm{CR}}.Math.v_4\left(0\right)$

[0105] Here, for simplification, it has been assumed that the values C are the same value and the values L are the same value. However, even if these values are different values, the same result can be derived through similar expression development.

[0106] In the conclusive expression, the second term on the right-hand side of the expression at the lowermost stage is sufficiently smaller than the first term, and thus can be neglected. Therefore, v.sub.in≈4v.sub.out is satisfied regardless of load variation (variation in the value of R), and output voltage becomes about ¼ of input voltage. Since no loss occurs except for the load R, output current is about four times as great as input current, and input impedance is sixteen times as great as the resistance value R.

[0107] As a circuit parameter condition, regarding inductance, 2πf.sub.0L<<R is satisfied. In addition, regarding capacitance, 1/(2πfsC)<<R<<1/(2πf.sub.0C) is satisfied. If this circuit parameter condition is satisfied, it is reliably realized that the voltage transformation ratio is constant regardless of load variation, and more stable transformation operation with less distortion is obtained. Preferably, a difference represented by the inequality sign is, for example, one-digit difference or greater, or more preferably, two-digit difference or greater.

[0108] FIG. 4 is a waveform diagram in which an upper graph shows input voltage to the transformer 1 and a lower graph shows input current to the transformer 1.

[0109] FIG. 5 is a waveform diagram showing voltage v.sub.m and current i.sub.m at an intermediate stage of transformation. Actually, these are composed of pulse trains based on switching, and as a whole, have such waveforms as shown in FIG. 5.

[0110] FIG. 6 is a waveform diagram in which an upper graph shows output voltage from the transformer 1 and a lower graph shows output current from the transformer 1. As is obvious from comparison between FIG. 4 and FIG. 6, voltage is transformed to be ¼, and along with this, current is quadrupled.

[0111] The transformer 1 shown in FIG. 1 is composed of a front stage circuit 1f including the switches S.sub.r1 and S.sub.b1 and the capacitors C1 and C2, and a rear stage circuit 1r including the switches S.sub.r2 and S.sub.b2 and the inductors L1 and L2. The circuit configurations of the front stage circuit 1f and the rear stage circuit 1r can be topologically expressed as follows.

[0112] That is, the front stage circuit 1f includes a “switch series unit” and “capacitors” described below.

[0113] The “switch series unit” is composed of two switches (S.sub.r1 and S.sub.b1) connected in series to each other. The odd-numbered switch (S.sub.r1) and the even-numbered switch (S.sub.b1), as seen from one end (e.g., an upper end) of both ends of the series unit, are configured to be alternately turned ON, and the switch series unit as a whole is connected in parallel to the power supply 2.

[0114] When a mutual connection point (N2) of the respective switches and points (N1 and N3) at the both ends of the switch series unit are regarded as three nodes in total and these three nodes are seen in order of 1 to 3 from one of the both ends of the switch series unit, the “capacitors (C1 and C2)” are disposed on at least one electrical path of a first electrical path and a second electrical path. The first electrical path combines the odd nodes (N1 and N3) and leads the odd nodes to a first output port Px, while the second electrical path leads the even node (N2) to a second output port Py. The “capacitors (C1 and C2)” are present so as to correspond to two nodes.

[0115] The rear stage circuit 1r includes an “element series unit” and “inductors” described below.

[0116] The “element series unit” is composed of a pair of semiconductor elements (S.sub.r2 and S.sub.b2) that are connected in series to each other and perform conducting operations of mutually opposite polarities, and one of both ends of the series unit is connected to the first output port Px while the other end thereof is connected to the second output port Py.

[0117] The “inductors (L1 and L2)” are disposed on at least one electrical path of a third electrical path and a fourth electrical path. The third electrical path combines two nodes (N11 and N13) that are points at the both ends of the element series unit, and leads the nodes to one of both ends of the load R. The fourth electrical path leads one node (N12) that is a mutual connection point of the pair of semiconductor elements to the other end of the load R. The “inductors (L1 and L2)” are present so as to correspond to two nodes (N11 and N13) among the three nodes in total.

[0118] <<Practical transformer>>

[0119] Next, an example of a transformer obtained by practically developing the above-described basic circuit will be described on the basis of the basic circuit.

[0120] FIG. 7 is a circuit diagram of such a transformer 1. This transformer 1 is provided between a power supply 2 and a load R, and is composed of a front stage circuit 1f, a rear stage circuit 1r, and a control section 3. For example, the power supply 2 is a DC power supply, and voltage is 1 kV. The load R includes a resistance R.sub.3 and a capacitance C.sub.6 as equivalent circuit elements.

[0121] The front stage circuit 1f includes bleeder resistor R.sub.1 and R.sub.2, switches SW1 to SW4, diodes D1 to D4 intrinsic to the switches SW1 to SW4, and capacitors C1 to C5, and these elements are connected as shown in FIG. 7.

[0122] The rear stage circuit 1r includes diodes D11 and D12 and inductors L1 and L2, and these elements are connected as shown in FIG. 7.

[0123] In addition, a control section 3 which performs ON/OFF control of the switches SW1 to SW4 is provided.

[0124] While five capacitors C1 to C5 are shown in FIG. 7, one of these capacitors can be omitted as described later. Therefore, using “4” equal to the number of the switches, the circuit shown in FIG. 7 is referred to as a “4C2L” circuit having 4C at the front stage and 2L at the rear stage. In contrast, the circuit shown in FIG. 1 is “2C2L”.

[0125] The diodes D1 to D4 may be body diodes intrinsic to the switches SW1 to SW4, or may be external diodes provided separately from the switches SW1 to SW4 depending on the type of the switches SW1 to SW4. These diodes D1 to D4 function as freewheel diodes, and may reduce switching loss, and further, may eventually reduce inductances of the inductors L1 and L2 and thus contribute to downsizing.

[0126] When the circuit configuration of the transformer 1 shown in FIG. 7 is topologically expressed similarly to FIG. 1, the transformer 1 includes, as the front stage circuit 1f, a “switch series unit” and “capacitors (C1 to C5)”.

[0127] The “switch series unit” is composed of the switches (SW1 to SW4) connected in series to each other. The odd-numbered switches (SW1 and SW3) and the even-numbered switches (SW2 and SW4), as seen from one end (e.g., an upper end) of both ends of the series unit, are alternately turned ON, and the switch series unit as a whole are connected in parallel to the power supply 2.

[0128] When mutual connection points (N2, N3, and N4) of the respective switches and points (N1 and N5) at the both ends of the switch series unit are regarded as five nodes in total and these five nodes are seen in order of 1 to 5 from one of the both ends of the switch series unit, the “capacitors (C1 to C5)” are disposed on at least one electrical path of a first electrical path and a second electrical path. The first electrical path combines the odd nodes (N1, N3, and N5) and leads the odd nodes to a first output port Px, and the second electrical path combines the even nodes (N2 and N4) and leads the even nodes to a second output port Py. The “capacitors (C1 to C5)” are present so as to correspond to five nodes.

[0129] In addition, the transformer 1 includes, as the rear stage circuit 1r, an “element series unit” and “inductors (L1 and L2)”.

[0130] The “element series unit” is composed of a pair of semiconductor elements (D11 and D12) that are connected in series to each other, and perform conducting operations of mutually opposite polarities, and one of both ends of the series unit is connected to the first output port Px while the other end thereof is connected to the second output port Py.

[0131] The “inductors (L1 and L2)” are disposed on at least one electrical path of a third electrical path and a fourth electrical path. The third electrical path combines two nodes (N11 and N13) that are points at the both ends of the element series unit, and leads the two nodes to one of both ends of the load R. The fourth electrical path leads one node (N12) that is a mutual connection point of the pair of semiconductor elements to the other end of the load R. The “inductors (L1 and L2)” are present so as to correspond to two nodes (N11 and N13) among the three nodes in total.

[0132] It was confirmed that the transformer shown in FIG. 7 performs switching so that the switches SW1 and SW3 and the switches SW2 and SW4 are alternately turned ON under the same conditions as those for the transformer 1 shown in FIG. 1, and thus the transformer operates as a step-down circuit having a voltage transformation ratio of 1/8. That is, input voltage of 1 kV can be stepped down to DC voltage of 125 V.

[0133] <<Topological variations>>

[0134] Next, topological variations of the circuit configuration of the transformer 1 (FIG. 1, FIG. 7, etc.) will be described.

[0135] (Topology of 2C Front Stage Circuit)

[0136] FIG. 8 is a circuit diagram showing topological variations of a main part of the front stage circuit 1f in the “2C2L” transformer 1. Circuits shown in (a) to (e) of FIG. 9 are each composed of a pair of switches and a pair of capacitors (reference numerals thereof are omitted).

[0137] In (a) of FIG. 8, capacitors are present so as to correspond to the node N3 of the switch series unit and the node N2 at the mutual connection point of the pair of switches. In (b) of FIG. 8, the topology of FIG. 1 is shown. In (c) of FIG. 8, capacitors are present so as to correspond to the node N1 of the switch series unit and the node N2 at the mutual connection point of the pair of switches. In (d) of FIG. 8, two capacitors are present so as to correspond to the node N3 of the switch series unit, and one capacitor is present in the output direction so as to correspond to the node N1. In (e) of FIG. 8, two capacitors are present so as to correspond to the node N1 of the switch series unit, and one capacitor is present in the output direction so as to correspond to the node N3.

[0138] Although two capacitors are present in any of the above circuits, capacitors may be present so as to correspond to all the nodes N1 to N3.

[0139] (Topology of 2L Rear Stage Circuit)

[0140] FIG. 9 is a circuit diagram showing topological variations of a main part of the rear stage circuit 1r. In each of circuits shown in (a) to (e) of FIG. 9, the rear stage circuit 1r connected to the load is composed of a pair of switches and a pair of inductors (reference numerals thereof are omitted). Instead of the switches, diodes may be used as shown in FIG. 7.

[0141] In (a) of FIG. 9, inductors are present so as to correspond to the node N13 of the switch series unit and the node N12 at the mutual connection point of the pair of switches. In (b) of FIG. 9, the topology of FIG. 1 is shown. In (c) of FIG. 9, inductors are present so as to correspond to the node N11 of the switch series unit and the node N12 at the mutual connection point of the pair of switches. In (d) of FIG. 9, two inductors are present so as to correspond to the node N13 of the switch series unit, and one inductor is present in the output direction so as to correspond to the node N11. In (e) of FIG. 9, two inductors are present so as to correspond to the node N11 of the switch series unit, and one inductor is present in the output direction so as to correspond to the node N13.

[0142] Although two inductors are present in any of the above circuits, inductors may be present so as to correspond to all the nodes N11 to N13.

[0143] In the case of (b) of FIG. 9, the inductances L (common inductance) of the two inductors L1 and L2 equally affect a dead time τ described later. On the other hand, in the cases of (a), (c), (d), and (e) of FIG. 9, the inductance L.sub.1, of the inductances L.sub.1 and L.sub.2 of the two inductors L1 and L2, is dominant in setting of the dead time τ.

[0144] (Topology of 4C Front Stage Circuit)

[0145] FIG. 10 shows the main part of the front stage circuit 1f in the “4C2L” transformer 1. In FIG. 10, a first electrical path that combines the odd nodes N1, N3, and N5 as seen from one of both ends of the switch series unit and leads the odd nodes to the first output port Px is represented by a solid line, and a second electrical path that combines the even nodes N2 and N4 and leads the even nodes to the second output port Py is represented by a dashed line. Expressing the second electrical path by the dashed line is simply for convenience of illustration, and the second electrical path coexists with the first electrical path.

[0146] This topology is identical to the front stage circuit 1f shown in FIG. 7.

[0147] In FIG. 10, one of the five capacitors may be omitted to provide “4C”. Assuming that the number of nodes is m (=5), the number of corresponding capacitors needs to be at least four.

[0148] At least one capacitor needs to be interposed between nodes that are mutually combined and connected by the first electrical path (solid line) or the second electrical path (dashed line) among the five nodes N1 to N5, in order to realize insulation for DC therebetween.

[0149] FIG. 11 and FIG. 12 each show circuit variations of the first electrical path in the case where the total number of capacitors is not reduced in the first electrical path (solid line) shown in FIG. 10.

[0150] In the circuit shown in (a) of FIG. 11, three electrical paths before being combined into a single path are each provided with a capacitor (similar to FIG. 10). In the circuits shown in (b), (c), and (d) of FIG. 11, two of three electrical paths before being combined into a single path are each provided with a capacitor, and a single electrical path obtained by combining the three electrical paths is also provided with a capacitor.

[0151] In the circuits shown in (a), (b), (c), and (d) of FIG. 12, the electrical paths are combined in two stages, and capacitor(s) is/are provided before and/or after the electrical paths are combined.

[0152] FIG. 13 is a diagram showing circuit variations of the first electrical path in the case where the total number of capacitors is reduced by one in the first electrical path (solid line) shown in FIG. 10.

[0153] In the circuits shown in (a) to (e) of FIG. 13, one node among the nodes N1, N3, and N5 is directly connected to the first output port Px. The other nodes are each connected to the first output port Px via one capacitor or two capacitors.

[0154] FIG. 14 is a diagram showing circuit variations of the second electrical path (dashed line) shown in FIG. 10. In FIG. 14, (a) and (b) are circuit diagrams in the case where one capacitor is reduced in the second electrical path while no capacitor is reduced in the first electrical path. In the case of (a), the node N2 is directly connected to the second output port Py. The node N4 is connected to the second output port Py via a capacitor. In the case of (b), the node N4 is directly connected to the second output port Py. The node N2 is connected to the second output port Py via a capacitor.

[0155] In FIG. 14, (c), (d), and (e) are circuit diagrams in the case where one capacitor is reduced in the first electrical path while no capacitor is reduced in the second electrical path. In any of the cases of (c) (identical to FIG. 10), (d), and (e), the nodes N2 and N4 are each connected to the second output port Py via one capacitor or two capacitors.

[0156] (Topology of 6C Front Stage Circuit)

[0157] As a modification intended to increase a step-down ratio, “6C2L” is also conceivable.

[0158] FIG. 15 shows a main part of a front stage circuit 1f in a “6C2L” transformer 1.

[0159] In FIG. 15, a first electrical path that combines odd nodes N1, N3, N5, and N7 as seen from one of both ends of the switch series unit and leads the odd nodes to the first output port Px is represented by a solid line, and a second electrical path that combines even nodes N2, N4, and N6 and leads the even nodes to the second output port Py is represented by a dashed line. Expressing the second electrical path by the dashed line is simply for convenience of illustration, and the second electrical path coexists with the first electrical path.

[0160] In the “6C2L” shown in FIG. 15, only one capacitor may be omitted from among seven capacitors to provide “6C”. Assuming that the number of nodes is m (=7), the number of corresponding capacitors needs to be at least six.

[0161] At least one capacitor needs to be interposed between nodes that are mutually combined and connected by the first electrical path (solid line) or the second electrical path (dashed line) among the seven nodes N1 to N7, in order to realize insulation for DC therebetween.

[0162] FIG. 16 shows circuit variations in the case where one capacitor is reduced in the first electrical path (solid line) or the second electrical path (dashed line) shown in FIG. 15. In the circuit shown in (a) of FIG. 16, the node N3 is directly connected to the first output port Px without an interposed capacitor. In the circuit shown in (b), the node N7 is directly connected to the first output port Px without an interposed capacitor. In the circuit shown in (c), the node N4 is directly connected to the second output port Py without an interposed capacitor.

[0163] <<Overview of Topology>>

[0164] Further, the front stage circuit 1f can be similarly extended to “8C” or more.

[0165] On the basis of the various circuits exemplified above, the front stage circuit 1f can be topologically expressed as follows.

[0166] The front stage circuit 1f (see FIG. 1, FIG. 8, and FIGS. 10 to 16) includes: (a) a switch series unit composed of a plurality of switches, as many as a multiple of 2, connected in series to each other, the plurality of switches including odd-numbered switches and even-numbered switches as seen from one of both ends of the series unit, the odd-numbered switches and even-numbered switches being configured to be alternately turned ON, the switch series unit as a whole being connected in parallel to a power supply; and (b) assuming that mutual connection points of the respective switches and points at the both ends of the switch series unit are regarded as m nodes in total and the nodes are seen in order of 1 to m from one of the both ends of the switch series unit, capacitors provided on at least one electrical path of a first electrical path and a second electrical path, the first electrical path being configured to combine odd nodes and lead the odd nodes to a first output port, the second electrical path being configured to combine even nodes and lead the even nodes to a second output port, the capacitors being present so as to correspond to at least (m−1) nodes.

[0167] On the other hand, the rear stage circuit 1r (see FIG. 1, FIG. 7, and FIG. 9) includes: (c) an element series unit composed of a pair of semiconductor elements that are connected in series to each other and perform conducting operations of mutually opposite polarities, one of both ends of the series unit being connected to the first output port while the other end being connected to the second output port; and (d) inductors provided on at least one electrical path of a third electrical path and a fourth electrical path, the third electrical path being configured to combine two nodes that are points at the both ends of the element series unit and to lead the two nodes to one end of a load, the fourth electrical path being configured to lead one node that is a mutual connection point of the pair of semiconductor elements to the other end of the load, the inductors being present so as to correspond to at least two nodes of the three nodes in total.

[0168] If the semiconductor elements of the rear stage circuit 1r are diodes, the element series unit can be configured by connecting the diodes in series with conducting directions thereof being opposite to each other. If the semiconductor elements are switches, the element series unit is configured by connecting a pair of switches in series, and the pair of switches are alternately turned ON.

[0169] The transformer 1 as described above can perform transformation by the circuit configuration including the front stage circuit 1f and the rear stage circuit 1r and by switching. Using the transformer 1 as a power transformer makes it unnecessary to use a conventional transformer including a coil, an iron core, and the like. Therefore, it is possible to realize drastic size reduction and weight reduction of a transformer, and thereby realize cost reduction accordingly. In addition, problems of parasitic capacitance and occurrence of magnetic field leakage, which arise in a high-frequency transformer, are also solved, and thus a transformer with low loss can be realized. As for the power supply, either an AC power supply or a DC power supply is applicable.

[0170] <<Design of Dead Time>>

[0171] Next, design of a dead time will be described. A dead time τ s a transient time from a moment when control for all switches is turned OFF to when control for either switches is turned on when, for example, the odd-numbered switches SW1 and SW3 and the even-numbered switches SW2 and SW4 shown in FIG. 7 are alternately turned ON.

[0172] FIG. 17 is a graph showing a change in switching voltage (drain-to-source voltage) when the odd-numbered switches or the even-numbered switches change from ON to OFF and then change to ON again. When the switches are ON, the switching voltage is 0 V. When the switches are OFF, the switching voltage is 500 V, for example. There is a transient voltage change in a dead time τ during the ON to OFF change or the OFF to ON change of the switches. When the switches change from OFF to ON, zero voltage transition (ZVT) in which the switching voltage drops to 0 V and thereafter the switches change to ON is desired in order to minimize switching loss.

[0173] FIG. 18 is a graph showing a part corresponding to the OFF to ON change shown in FIG. 17, with the time on the horizontal axis being scaled up. It is found that, in FIG. 18, the dead time τ includes a first half time τ.sub.1 from 500 V to 250 V, and a subsequent second half time τ.sub.2 from 250 V to 0 V. That is, the following relationship is satisfied:

τ≧τ.sub.1+τ.sub.2   (1)

[0174] The gradient of the first half time τ.sub.1 and the gradient of the second half time τ.sub.2 are slightly different from each other, and τ.sub.1<τ.sub.2 is satisfied. Therefore, the dead time τ can be considered separately for the first half time τ.sub.1 and the second half time τ.sub.2. Assuming that the output voltage of 125 V from the transformer 1 is V.sub.out,

[0175] τ.sub.1: a period in which the voltage is from 4 V.sub.out to 2 V.sub.out

[0176] τ.sub.2: a period in which the voltage is from 2 V.sub.out to 0

[0177] FIG. 19 is a graph showing the relationship between ZVT and the length of the dead time which is set to be “long”, “medium”, and “short”. In FIG. 19, when the dead time τ is shorter than an appropriate value (medium), a voltage change indicated by an alternate long and short dash line occurs, and next ON starts before the voltage reaches 0 V. That is, this is not ZVT. On the other hand, when the dead time τ is longer than the appropriate value (medium), a voltage change indicated by a solid line occurs and the voltage once reaches 0 V, but thereafter the voltage increases again, and eventually, next ON starts with the voltage remaining increased. That is, this is also not ZVT. Therefore, there is an appropriate (not too long and not too short) range of “τ” indicated by the dashed line.

[0178] FIG. 20 is a circuit diagram of a transformer 1 in which the diodes D1 to D4 and the bleeder resistors R1 and R2 shown in FIG. 7 are omitted, and instead, floating capacitances C11 to C14 possessed by the respective switches SW1 to SW4 are shown. FIG. 20 also shows a current path in the first half time τ.sub.1. Of the diodes D11 and D12, the diode D12 is in the conductive state. At this time, current I.sub.L1 that flows in the inductor L1 flows into the floating capacitances C11 to C14. Assuming that current that flows in the inductor L2 is I.sub.L2, current that flows into the floating capacitances C11 to C14 is I.sub.Q, and current that flows in the load R is I.sub.R, the following relationship is satisfied:

I.sub.Q=I.sub.L2+I.sub.R=I.sub.L1

[0179] Although FIG. 21 is of the same background as FIG. 20, FIG. 21 also shows a current path in the second half time τ.sub.2. Of the diodes D11 and D12, the diode D11 is in the conductive state. At this time, current I.sub.L2 that flows in the inductor L2 flows into the floating capacitances C11 to C14. In this case, the following relationship is satisfied:

I.sub.Q=I.sub.L1−I.sub.R=I.sub.L2

[0180] Therefore, I.sub.L2 is smaller than I.sub.L1.

[0181] FIG. 22 is a graph showing examples of waveforms of currents that flow in the inductors L1 and L2. The current waveforms can be approximated by straight lines as shown in FIG. 22. Of the two waveforms, the upper waveform is the waveform of I.sub.L1, and the lower waveform is the waveform of I.sub.L2. A transition time from a minimum value to a maximum value of each waveform is half the switching cycle T.

[0182] Here, the following approximate conditions for analysis are adopted.

[0183] (Approximate Condition 1)

[0184] First, it is assumed that the step-down ratio is constant at 1/8. That is, assuming that the input voltage of the transformer 1 is V.sub.m and output voltage thereof is V.sub.out, the following relationship is satisfied:

V.sub.out≈V.sub.in/8=125[V]

[0185] (Approximate Condition 2)

[0186] The voltage waveform at both ends of each of the inductors L1 and L2 is a rectangular wave having a duty ratio of 50%.

[0187] (Approximate Condition 3)

[0188] The absolute values of voltages V.sub.L1 and V.sub.L2 at both ends of the inductors L1 and L2, respectively, are the output voltage. That is, assuming that the maximum value of voltage V.sub.L is V.sub.Lmax and the minimum value of voltage V.sub.L is V.sub.Lmin, the following relationships are satisfied:

V.sub.Lmax≈V.sub.out

V.sub.Lmin≈−V.sub.out

[0189] For simplifying calculation,

V.sub.L1≈V.sub.L2≈±V.sub.out.

[0190] Assuming that the inductors L1 and L2 have a common inductance value L, the voltage V.sub.L at the both ends of each of the inductors L1 and L2 is expressed by

V.sub.L=L(dI.sub.L(t)/dt)=L.Math.a

[0191] where a is inclination of a straight line.

Therefore, the following relationship is satisfied:

a=V.sub.out/L   (2)

[0192] In addition, peak-to-peak current I.sub.Lp-p is expressed by

I.sub.Lp-p=a(T/2)

and therefore, the following relationship is satisfied.

I.sub.Lp-p=T.Math.V.sub.out/2L  (3)

[0193] FIG. 23 is an enlarged view showing a portion near the peaks of the waveforms shown in FIG. 22. In FIG. 23, electric charges Q.sub.1 that flow into floating capacitance C.sub.DS (general term for C11 to C14) during the first half time τ.sub.1 are represented by a hatched area on the left side in FIG. 23. That is, the following expression is obtained:

Q.sub.1={(I.sub.Lp-p/2)+(V.sub.out/2R.sub.3)}τ.sub.1−(τ.sub.1/2).Math.(aτ.sub.1/2)  (4)

In addition, electric charges Q.sub.2 that flow into the floating capacitance C.sub.DS during the second half time τ.sub.2 are represented by a hatched area on the right side in FIG. 23. That is, the following expression is obtained:

Q.sub.2={(I.sub.Lp-p/2)−(V.sub.out/2R.sub.3)}τ.sub.2−(τ.sub.2/2).Math.(aτ.sub.2/2)  (5)

[0194] When the above expression (4) is developed by substituting expressions (2) and (3) for Q.sub.1 of expression (4), the following expression is obtained:

Q.sub.t=(V.sub.out.Math.τ½){(T/2L)+(1/R.sub.3)}−(V.sub.out.Math.τ1.sup.2/4L)  (6)

[0195] When the above expression (5) is developed by substituting expressions (2) and (3) for Q.sub.2 of expression (5), the following expression is obtained:

Q.sub.2=(V.sub.out.Math.τ2/2){(T/2L)−(1/R.sub.3)}−(V.sub.out.Math.τ2.sup.2/4L)  (7)

[0196] Because of the electric charges Q.sub.1, electric charges equivalent to V.sub.in(=1 kV)/4, i.e., 250 V (=2V.sub.out) move to the four floating capacitances C.sub.DS (C11 to C14), and therefore, the following expression is obtained:

Q.sub.1=4C.sub.DS.Math.2V.sub.out=8C.sub.DS.Math.V.sub.out  (8)

When a quadratic equation obtained from expressions (6) and (8) is solved with respect to τ.sub.1, the following expression is obtained:

τ.sub.1=(T/2)+(L/R.sub.3)−(½)[{T+(2L/R.sub.3)}.sup.2−128LC.sub.DS].sup.1/2  (9)

[0197] Likewise, because of the electric charges Q.sub.2, electric charges equivalent to V.sub.in(=1 kV)/4, i.e., 250 V(=2V.sub.out) move to the four floating capacitances C.sub.DS (C11 to C14), and therefore, the following expression is obtained:

Q.sub.2=4C.sub.DS.Math.2V.sub.out=8C.sub.DS.Math.V.sub.out  (10)

When a quadratic equation obtained from expressions (7) and (10) is solved with respect to τ.sub.2, the following expression is obtained:

τ.sub.2=(T2)−(L/R.sub.3)−(½)[{T−(2L/R.sub.3)}.sup.2−128LC.sub.DS].sup.1/2  (11)

[0198] Next, the maximum value of the dead time τ will be considered.

[0199] FIG. 24 is a diagram showing the waveforms shown in FIG. 23 extended in the time-axis direction (rightward direction). In a second half region of the second half time τ2, the gradient of current becomes (−a). Therefore, time to exists, at which I.sub.L2=0. After time to has passed, negative current flows. This means that electric charges corresponding to a lower-right hatched portion return on and after time t.sub.0. If so, the switching voltage increases again. Therefore, the dead time τ must be set so as not to reach time t.sub.0. The maximum value of the dead time that does not reach to is referred to as τ.sub.max.

[0200] In FIG. 24, assuming that a time period for the current I.sub.L2 from the positive peak to 0V is τ.sub.0, the following expression is obtained:

{(I.sub.Lp-p/2)−(V.sub.out/2R.sub.3)}−aτ.sub.0=0  (12)

When expression (12) is solved with respect to τ.sub.0 by substituting expressions (2) and (3) for expression (12), the following expression is obtained:

τ.sub.0=(T/4)−(L/2R.sub.3)  (13)

From FIG. 24, the following expression is obtained:

τ.sub.max=τ.sub.0+(τ.sub.2/2)+τ.sub.1  (14)

On the basis of expressions (13) and (14), the following expression is obtained:

τ.sub.max=(T/4)−(L/2R.sub.3)+(τ.sub.2/2)+τ.sub.1  (14a)

[0201] It is needless to say that τ.sub.max must satisfy τ.sub.max<(T/2) in order to secure ON time of switching.

[0202] Consequently, the range of the dead time τ should be set as follows:

τ.sub.1+τ.sub.2≦τ≦τ.sub.0+(τ.sub.2/2)+τ.sub.1  (15)

[0203] whereto, τ.sub.0, τ.sub.1, and τ.sub.2 are as follows:

[00012]$\begin{array}{cc}{\tau }_0=\frac{T}{4}-\frac{L}{2.Math..Math.R_3}.Math..Math.{\tau }_1=\frac{T}{2}+\frac{L}{.Math.R_3}-\frac{1}{2}.Math.\sqrt{{\left(T+\frac{2.Math.L}{R_3}\right)}^2-128.Math..Math.L.Math..Math.C_{\mathrm{DS}}}.Math..Math.{\tau }_2=\frac{T}{2}-\frac{L}{.Math.R_3}-\frac{1}{2}.Math.\sqrt{{\left(T-\frac{2.Math.L}{R_3}\right)}^2-128.Math..Math.L.Math..Math.C_{\mathrm{DS}}}& \left(16\right)\end{array}$

[0204] The above expression (16) is generalized as follows, taking into consideration multistage configuration of the front stage circuit. Expression (15) is unchanged even when multistage configuration of the front stage circuit is considered.

[0205] Assuming that the number of the floating capacitances C.sub.DS (equal to the number of the switches constituting the switch series unit) is n, and the n-th floating capacitance counted in order from 1 is C.sub.nDS, expression (16) is generalized as follows:

[00013]$\begin{array}{cc}{\tau }_0=\frac{T}{4}-\frac{L}{2.Math..Math.R_3}.Math..Math.{\tau }_1=\frac{T}{2}+\frac{L}{.Math.R_3}-\frac{1}{2}.Math.\sqrt{{\left(T+\frac{2.Math.L}{R_3}\right)}^2-32.Math..Math.L.Math.\underset{n=1}{\overset{n}{.Math.}}.Math..Math.C_{\mathrm{nDS}}}.Math..Math.{\tau }_2=\frac{T}{2}-\frac{L}{.Math.R_3}-\frac{1}{2}.Math.\sqrt{{\left(T-\frac{2.Math.L}{R_3}\right)}^2-32.Math..Math.L.Math.\underset{n=1}{\overset{n}{.Math.}}.Math..Math.C_{\mathrm{nDS}}}& \left(17\right)\end{array}$

[0206] wherein the sign of a value in each radical sign is plus, and τ.sub.1<τ.sub.2 is satisfied.

[0207] It has been known that the range of the dead time τ is determined by the topology of the rear stage circuit, regardless of the topology of the front stage circuit. When the rear stage circuit has the configuration shown in (b) of FIG. 9, τ is given by the above expressions (15) and (17).

[0208] On the other hand, when the rear stage circuit has the configuration other than that shown in (b) of FIG. 9, in other words, any of the configurations shown in (a), (c), (d), and (e) of FIG. 9, τ is given by the following expressions (15a) and (17a).

τ.sub.1+τ.sub.2≦τ≦τ.sub.0+τ.sub.1  (15a)

[0209] where τ.sub.0, τ.sub.1, and τ.sub.2 are as follows:

[00014]$\begin{array}{cc}{\tau }_0=\frac{T}{4}-\frac{L_1}{4.Math.R_3}.Math..Math.{\tau }_1=\frac{T}{4}+\frac{L_1}{.Math.4.Math.R_3}-\frac{1}{4}.Math.\sqrt{{\left(T+\frac{L_1}{R_3}\right)}^2-32.Math..Math.L_1.Math.\underset{n=1}{\overset{n}{.Math.}}.Math..Math.C_{\mathrm{nDS}}}.Math..Math.{\tau }_2=\frac{T}{4}-\frac{L_1}{.Math.4.Math.R_3}-\frac{1}{4}.Math.\sqrt{{\left(T-\frac{L_1}{R_3}\right)}^2-32.Math..Math.L_1.Math.\underset{n=1}{\overset{n}{.Math.}}.Math..Math.C_{\mathrm{nDS}}}& \left(17.Math.a\right)\end{array}$

[0210] As described above, when the topology of the rear stage is any of (a), (c), (d), and (e) of FIG. 9, the inductance that is dominant for the dead time τ is L.sub.1, only the inductance τ.sub.1 appears in expression (17a).

[0211] (Conclusion)

[0212] As described above in detail, for example, in FIG. 7, the control section 3 of the transformer 1, after the time at which the dead time has started, obtains: the first half time τ.sub.1 which can be calculated on the basis of the electric charges that move from the inductor L1 to the floating capacitance C.sub.DS of the switch while one (D12) of the diodes D11 and D12 is in the conductive state; and the second half time τ.sub.2 which can be calculated on the basis of the electric charges that move from the inductor L2 to the floating capacitance C.sub.DS of the switch while one (D11) of the diodes D11 and D12 is in the conductive state, and then the control section 3 can determine the dead time τ on the basis of the first half time τ.sub.1 and the second half time τ.sub.2.

[0213] Thus, on the basis of the times τ.sub.1 and τ.sub.2 calculated focusing on movement of the electric charges during the dead time, an appropriate dead time τ can be determined to realize zero voltage transition (ZVT).

[0214] Further, the control section 3 terminates the dead time τ before the electric charges that have moved to the floating capacitance CDs return to the inductors L1 and L2, thereby preventing the switching voltage from increasing again.

[0215] Further, the appropriate range of the dead time τ can be precisely determined on the basis of the above expressions (15) to (17), thereby reliably realizing zero voltage transition.

[0216] <<Verification of Effect Of Dead Time τ>>

[0217] Regarding various transformers in which the dead time τ is designed within the above-described range, the performances thereof have been verified. The verification results will be described below.

[0218] <Condition 1>

[0219] Circuit configuration: “2C2L”

[0220] Inductance L of inductors L1 and L2=15 [mH]

[0221] Resistance R.sub.3 of load=15625 [Ω]

[0222] Floating capacitance C.sub.DS=5 [pF]

[0223] In the case of the condition 1, the minimum value and the maximum value of the dead time τ are calculated as follows on the basis of above expressions (15) and (17).

[0224] Minimum value τ.sub.min=253 [ns]

[0225] Maximum value τ.sub.max=2197 [ns]

[0226] FIG. 25 is a graph showing the relationship between the dead time τ [ns] and efficiency [%] in the case of the condition 1. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which the efficiency is excellent on the characteristics shown in the graph.

[0227] FIG. 26 is a graph showing the relationship between the dead time τ [ns] and output power [W] of the transformer in the case of the condition 1. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which stable high output is achieved on the characteristics shown in the graph.

[0228] <Condition 2>

[0229] Circuit configuration: “2C2L”

[0230] Inductance L of inductors L1 and L2=15 [mH]

[0231] Resistance R.sub.3 of load=7000 [Ω]

[0232] Floating capacitance C.sub.DS=5 [pF]

[0233] In the case of the above condition 2, the minimum value and the maximum value of the dead time τ are calculated as follows on the basis of expressions (15) and (17).

[0234] Minimum value τ.sub.min=303 [ns]

[0235] Maximum value τ.sub.max=1622 [ns]

[0236] FIG. 27 is a graph showing the relationship between the dead time τ [ns] and efficiency [%] in the case of the condition 2. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which the efficiency is excellent on the characteristics shown in the graph.

[0237] FIG. 28 is a graph showing the relationship between the dead time τ [ns] and output power [W] of the transformer in the case of the condition 2. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which stable high output is achieved on the characteristics shown in the graph.

[0238] <Condition 3>

[0239] Circuit configuration: “2C2L”

[0240] Inductance L of inductors L1 and L2=15 [mH]

[0241] Resistance R.sub.3 of load=15625 [Ω]

[0242] Floating capacitance C.sub.DS=10 [pF]

[0243] In the case of the above condition 3, the minimum value and the maximum value of the dead time τ are calculated as follows on the basis of expressions (15) and (17).

[0244] Minimum value τ.sub.min=514 [ns]

[0245] Maximum value τ.sub.max=2379 [ns]

[0246] FIG. 29 is a graph showing the relationship between the dead time τ [ns] and efficiency [%] in the case of the condition 3. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which the efficiency is excellent on the characteristics shown in the graph.

[0247] FIG. 30 is a graph showing the relationship between the dead time τ [ns] and output power [W] of the transformer in the case of the condition 3. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which stable high output is achieved on the characteristics shown in the graph.

[0248] <Condition 4>

[0249] Circuit configuration: “2C2L”

[0250] Inductance L of inductors L1 and L2=7.5 [mH]

[0251] Resistance R.sub.3 of load=15625 [Ω]

[0252] Floating capacitance C.sub.DS=5 [pF]

[0253] In the case of the above condition 4, the minimum value and the maximum value of the dead time τ are calculated as follows on the basis of expressions (15) and (17).

[0254] Minimum value τ.sub.min=122 [ns]

[0255] Maximum value τ.sub.min=2348 [ns]

[0256] FIG. 31 is a graph showing the relationship between the dead time τ [ns] and efficiency [%] in the case of the condition 4. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which the efficiency is excellent on the characteristics shown in the graph.

[0257] FIG. 32 is a graph showing the relationship between the dead time τ [ns] and output power [W] of the transformer in the case of the condition 4. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which stable high output is achieved on the characteristics shown in the graph.

[0258] <Condition 5>

[0259] Circuit configuration: “6C2L”

[0260] Inductance L of inductors L1 and L2=15 [mH]

[0261] Resistance R.sub.3 of load=15625 [Ω]

[0262] Floating capacitance C.sub.Ds=5 [pF]

[0263] In the case of the above condition 5, the minimum value and the maximum value of the dead time τ are calculated as follows on the basis of expressions (15) and (17).

[0264] Minimum value τ.sub.min=783 [ns]

[0265] Maximum value τ.sub.max=2567 [ns]

[0266] FIG. 33 is a graph showing the relationship between the dead time τ [ns] and efficiency [%] in the case of the condition 5. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which the efficiency is excellent on the characteristics shown in the graph.

[0267] FIG. 34 is a graph showing the relationship between the dead time τ [ns] and output power [W] of the transformer in the case of the condition 5. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which stable high output is achieved on the characteristics shown in the graph.

[0268] <Condition 6>

[0269] Circuit configuration: “6C2L”

[0270] Inductance L of inductors L1 and L2=15 [mH]

[0271] Resistance R.sub.3 of load=7000 [Ω]

[0272] Floating capacitance C.sub.DS=5 [pF]

[0273] In the case of the above condition 6, the minimum value and the maximum value of the dead time τ are calculated as follows on the basis of expressions (15) and (17).

[0274] Minimum value τ.sub.min=978 [ns]

[0275] Maximum value τ.sub.max=2046 [ns]

[0276] FIG. 35 is a graph showing the relationship between the dead time τ [ns] and efficiency [%] in the case of the condition 6. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which the efficiency is excellent on the characteristics shown in the graph.

[0277] FIG. 36 is a graph showing the relationship between the dead time τ [ns] and output power [W] of the transformer in the case of the condition 6. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which stable high output is achieved on the characteristics shown in the graph.

[0278] <Condition 7>

[0279] Circuit configuration: “6C2L”

[0280] Inductance L of inductors L1 and L2=15 [mH]

[0281] Resistance R.sub.3 of load=15625 [Ω]

[0282] Floating capacitance C.sub.DS=10 [pF]

[0283] In the case of the above condition 7, the minimum value and the maximum value of the dead time τ are calculated as follows on the basis of expressions (15) and (17).

[0284] Minimum value τ.sub.min=1658 [ns]

[0285] Maximum value τ.sub.max=3168 [ns]

[0286] FIG. 37 is a graph showing the relationship between the dead time τ [ns] and efficiency [%] in the case of the condition 7. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which the efficiency is excellent on the characteristics shown in the graph.

[0287] FIG. 38 is a graph showing the relationship between the dead time τ [ns] and output power [W] of the transformer in the case of the condition 7. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which stable high output is achieved on the characteristics shown in the graph.

[0288] <Condition 8>

[0289] Circuit configuration: “6C2L”

[0290] Inductance L of inductors L1 and L2=7.5 [mH]

[0291] Resistance R.sub.3 of load=15625 [Ω]

[0292] Floating capacitance C.sub.DS=5 [pF]

[0293] In the case of the above condition 8, the minimum value and the maximum value of the dead time τ are calculated as follows on the basis of expressions (15) and (17).

[0294] Minimum value τ.sub.min=370 [ns]

[0295] Maximum value τ.sub.max=2528 [ns]

[0296] FIG. 39 is a graph showing the relationship between the dead time τ [ns] and efficiency [%] in the case of the condition 8. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which the efficiency is excellent on the characteristics shown in the graph.

[0297] FIG. 40 is a graph showing the relationship between the dead time τ [ns] and output power [W] of the transformer in the case of the condition 8. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which stable high output is achieved on the characteristics shown in the graph.

[0298] In the above conditions 1 to 8, the value of the floating capacitance C.sub.DS is common among a plurality of capacitors. Hereinafter, a case where a plurality of capacitors have different floating capacitances C.sub.DS will be verified.

[0299] <Condition 9>

[0300] Circuit configuration: “4C2L”

[0301] Inductance L of inductors L1 and L2=15 [mH]

[0302] Resistance R.sub.3 of load=15625 [Ω]

[0303] Floating capacitances C.sub.DS=17 [pF], 10 [pF], 10 [pF], 3 [pF]

[0304] Floating capacitance ΣC.sub.DS as a whole: 40 [pF]

[0305] In the case of the above condition 9, the minimum value and the maximum value of the dead time τ are calculated as follows on the basis of expressions (15) and (17).

[0306] Minimum value τ.sub.min=1063 [ns]

[0307] Maximum value τ.sub.max=2760 [ns]

[0308] FIG. 41 is a graph showing the relationship between the dead time τ [ns] and efficiency [%] in the case of the condition 9. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which the efficiency is excellent on the characteristics shown in the graph.

[0309] FIG. 42 is a graph showing the relationship between the dead time τ [ns] and output power [W] of the transformer in the case of the condition 9. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which stable high output is achieved on the characteristics shown in the graph.

[0310] <Condition 10>

[0311] Circuit configuration: “4C2L”

[0312] Inductance L of inductors L1 and L2=15 [mH]

[0313] Resistance R.sub.3 of load=15625 [Ω]

[0314] Floating capacitances C.sub.DS=12 [pF], 5 [pF], 15 [pF], 8 [pF]

[0315] Floating capacitance ΣC.sub.DS as a whole: 40 [pF]

[0316] In the case of the above condition 10, the minimum value and the maximum value of the dead time τ are calculated as follows on the basis of expressions (15) and (17).

[0317] Minimum value τ.sub.min=1063 [ns]

[0318] Maximum value τ.sub.max=2760 [ns]

[0319] FIG. 43 is a graph showing the relationship between the dead time τ [ns] and efficiency [%] in the case of the condition 10. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which the efficiency is excellent on the characteristics shown in the graph.

[0320] FIG. 44 is a graph showing the relationship between the dead time τ [ns] and output power [W] of the transformer in the case of the condition 10. When the calculated τ.sub.min and τ.sub.max are plotted on the graph, it is found that these values correspond to a range in which stable high output is achieved on the characteristics shown in the graph.

[0321] As described above, by determining the dead time τ on the basis of the relationships expressed by expressions (15) and (17), the transformer can achieve excellent efficiency and stable high output.

[0322] <<Supplement>>

[0323] It is noted that the embodiment disclosed herein is merely illustrative in all aspects and should not be recognized as being restrictive. The scope of the present invention is defined by the scope of the claims and is intended to include meaning equivalent to the scope of the claims and all modifications within the scope.

REFERENCE SIGNS LIST

[0324] 1 transformer

[0325] 1f front stage circuit

[0326] 1r rear stage circuit

[0327] 2 AC power supply, power supply

[0328] 3 control section

[0329] 4 switch device

[0330] C1 to C5 capacitor

[0331] C6 capacitance

[0332] D1 to D4, D11, D12 diode

[0333] L1, L2 inductor

[0334] M1, M2 connection point

[0335] N1 to N7, N11 to N13 node

[0336] Px first output port

[0337] Py second output port

[0338] R load

[0339] R.sub.1, R.sub.2 bleeder resistor

[0340] R.sub.3 resistance

[0341] Sr1, Sr2, Sb1, Sb2 switch

[0342] SW1 to SW4 switch