METHOD OF PROCESSING LAYERED STRUCTURES

Abstract

A method of processing a stack of layers to provide a stack of discrete layer elements, comprises the steps of: providing a stack of layers comprising: #a first layer (20) provided by a first material; #a third layer (16) provided by a solid electrolyte; and #a second layer (18) located between the first and third layers, the second layer having a thickness of at least 500 nm and being provided by a second material comprising at least 95 atomic % amorphous silicon; removing a through-thickness portion of the first layer (20) to form a first discrete layer element (20a) provided by the first material; removing a through-thickness portion of the second layer (18) to form a second discrete layer element (18a) provided by the second material, the second discrete layer element being located between the first discrete layer element (20a) and the solid electrolyte; and etching the third layer (16) using the second discrete layer element (18a) as an etching mask, to form a third discrete layer element (16a) provided by the solid electrolyte; wherein the first, second and third discrete layer elements provide the stack of discrete layer elements.

Claims

1. A method of processing a stack of layers to provide a stack of discrete layer elements, comprising the steps of: providing a stack of layers comprising: a first layer provided by a first material; a third layer provided by a solid electrolyte; and a second layer located between the first and third layers, the second layer having a thickness of at least 500 nm and being provided by a second material comprising at least 95 atomic % amorphous silicon; removing a through-thickness portion of the first layer to form a first discrete layer element provided by the first material; removing a through-thickness portion of the second layer to form a second discrete layer element provided by the second material, the second discrete layer element being located between the first discrete layer element and the solid electrolyte; and etching the third layer using the second discrete layer element as an etching mask, to form a third discrete layer element provided by the solid electrolyte; wherein the first, second and third discrete layer elements provide the stack of discrete layer elements.

2. The method according to claim 1, further comprising the step, after the step of etching the third layer, of modifying the second discrete layer element, to provide a modified second discrete layer element, wherein the perimeter of the modified second discrete layer element encompasses a smaller area than the area encompassed by the perimeter of the second discrete layer element.

3. The method according to claim 2, wherein the step of providing a modified second discrete layer element comprises one or more of the following steps: trimming the second discrete layer element about at least a portion of its perimeter and/or creating a trench in the second discrete layer element, the trench extending in a through-thickness direction of the second discrete layer element and defining a boundary between the modified second discrete layer element and an isolated part of the second discrete layer element, the isolated part extending about at least a portion of the perimeter of the second discrete layer element.

4. The method according to claim 3, wherein the step of providing a modified second discrete layer element comprises the step of creating a trench in the second discrete layer element, and further wherein the trench defines the whole perimeter of the modified second discrete layer element.

5. The method according to claim 3, wherein the step of providing a modified second discrete layer element comprises the step of creating a trench in the second discrete layer element, and further wherein the trench is created through an etching process.

6. The method according to claim 3, wherein the step of providing a modified second discrete layer element comprises the step of creating a trench in the second discrete layer element, and further wherein the trench extends at least as far as the interface between the second discrete layer element and the third discrete layer element, such that the base of the trench is either in the same plane as the interface between the second discrete layer element and the third discrete layer element or within the third discrete layer element.

7. The method according to claim 3, wherein the step of providing a modified second discrete layer element comprises the step of creating a trench in the second discrete layer element, and further wherein the width of the trench lies within the range 1-100 μm.

8. The method according to claim 3, wherein the step of providing a modified second discrete layer element comprises the step of creating a trench in the second discrete layer element, the trench having a base and sidewalls, the base being aligned with the interface between the modified second discrete layer element and the third discrete layer element, and the sidewalls extending in a transverse direction relative to the base and being mutually aligned.

9. The method according to claim 3, wherein the step of providing a modified second discrete layer element comprises the step of creating a trench in the second discrete layer element, wherein a cathode layer is provided on a face of the third discrete layer element that is opposed to the second discrete layer element and at least a portion of the trench is created in a part of the second discrete layer element that is directly opposed to the cathode layer.

10. The method according to claim 1, further comprising the step, after the step of etching the third layer, of trimming the second discrete layer element about at least a portion of its perimeter to provide a modified second discrete layer element.

11. The method according to claim 10, wherein the modified second discrete layer element is located entirely within a boundary defined by the perimeter of the third discrete layer element.

12. The method according to claim 1, wherein the steps of removing a through-thickness portion of the first layer to form the first discrete layer element and removing a through-thickness portion of the second layer to form the second discrete layer element are carried out in a single procedure.

13. The method according to claim 1, wherein the step of removing a through-thickness portion of the first layer to form the first discrete layer element and/or removing a through-thickness portion of the second layer to form the second discrete layer element comprises etching the respective layer.

14. The method according to claim 13, wherein the step of removing a through-thickness portion of the first layer comprises a photolithography procedure.

15. The method according to claim 13, wherein the step of etching the respective layer comprises using a dry etching treatment.

16. The method according to claim 15, wherein the dry etching treatment is a plasma etching treatment.

17. The method according to claim 16, wherein the plasma etching treatment is carried out using a plasma comprising argon and/or SF6.

18. The method according to claim 1, wherein the step of removing a through-thickness portion of the second layer to form the second discrete layer element is carried out using laser ablation.

19. The method according to claim 1, wherein the step of etching the third layer is carried out using an aqueous etchant having a neutral, alkaline, or acidic pH value.

20. The method according to claim 19, wherein the etchant is water.

21. The method according to claim 1, wherein the solid electrolyte is provided by a material selected from the group consisting of LiPON, LiSiPON, Thio-LiSiCON, LiBON, an amorphous lithium borosilicate compound, and a doped amorphous lithium borosilicate compound.

22. The method according to claim 1, wherein the first material is selected from the group consisting of platinum, nickel, molybdenum, copper, titanium nitride, aluminium, gold and stainless steel.

23. The method according to claim 1, wherein the second layer has a thickness of at least 700 nm.

24. The method according to claim 1, wherein a plurality of the stacks of discrete layer elements are provided, the plurality of stacks of discrete layer elements being displaced from each other in the plane of the first, second and/or third layer.

25. The method according to claim 24, wherein the plurality of stacks of discrete layer elements are arranged on a substrate in a regular array.

26. An electrochemical cell comprising at least the following discrete layer elements stacked in the following order: a first discrete layer element provided by a first material; a second discrete layer element having a thickness of at least 500 nm and being provided by a second material comprising at least 95 atomic % amorphous silicon; a third discrete layer element provided by a solid electrolyte; and a fourth discrete layer element comprising a cathode active material; wherein a trench is provided in a through-thickness direction of the second discrete layer element, the trench having a base that is either at the interface between the second and third discrete layer elements or within the third discrete layer element, the trench defining a boundary between a modified second discrete layer element and an isolated part of the second discrete layer element, the isolated part extending about at least a portion of the perimeter of the second discrete layer element.

27. The electrochemical cell according to claim 26, wherein the trench defines the entire perimeter of the modified second discrete layer element.

28. The electrochemical cell according to claim 26, wherein the width of the trench lies within the range 1-100 μm.

29. The electrochemical cell according to claim 26, wherein the trench additionally extends through the first discrete layer element.

30. The electrochemical cell according to claim 26, wherein the trench has sidewalls extending from the base, the sidewalls being mutually-aligned.

31. The electrochemical cell according to claim 26, wherein at least a portion of the trench is provided in a part of the second discrete layer element that is located directly opposite the fourth discrete layer element.

Description

DETAILED DESCRIPTION

[0089] The invention will now be described by way of example with reference to the following Figures in which:

[0090] FIGS. 1 to 7 show schematic cross-sectional views of assembled battery components at various stages of manufacture of a battery incorporating a process according to a first example of the method of the invention;

[0091] FIG. 8 shows a schematic cross-sectional view of a battery manufactured according to a process incorporating the first example of the method according to the invention;

[0092] FIG. 9 shows a schematic cross-sectional view of a battery manufactured according to a process incorporating a second example of the method according to the invention;

[0093] FIG. 10 shows a schematic cross-sectional view of a battery manufactured according to a process incorporating a third example of the method according to the invention;

[0094] FIG. 11 shows a graph of multiple charge-discharge cycles measured from a battery such as that in FIG. 8, as a plot of voltage against time;

[0095] FIG. 12 shows a graph of battery capacity over multiple charge-discharge cycles measured from a battery such as that in FIG. 8.

[0096] Referring to FIGS. 1-8, the manufacture of a battery incorporating a process according to a first example of the method of the invention comprises providing a substrate 10 and depositing a layer 12 on a surface of the substrate. Layer 12 comprises an adhesion layer and a metal layer. Layer 12 is subsequently etched through a photolithographic procedure to provide a cathode current collector 12a. The photolithographic procedure comprises the deposition of a photoresist layer (not shown) onto the surface of layer 12, treatment of the photoresist layer to form a mask, followed by etching using ion beam milling or wet chemical etching and subsequent removal of the photoresist layer.

[0097] The substrate 10 is typically provided by a sapphire (aluminium oxide) wafer, but other materials, such as silicon, glass, or ceramics may be used. When a silicon substrate is used, this may have a passivation layer such as silicon nitride or silicon oxide. The substrate may be provided by a wafer of non-conductive, semi-conductive, or conductive material. In the case that the substrate is provided by a wafer of semi-conductive or conductive material, it is preferred that the surface of the wafer in contact with the cathode current collector 12 is provided with a non-conductive film.

[0098] Referring to FIGS. 3 and 4, a cathode layer 14 is deposited onto the cathode current collector 12a as well as the uncovered surface of the substrate 10 (suitable cathode materials are known in the art). The cathode layer is subsequently etched through a photolithographic procedure to provide a cathode 14a that has a similar footprint to the cathode current collector 12a (for example, the cathode may be generally slightly larger than the cathode current collector, while leaving a portion of the cathode current collector uncovered, so as to provide a contact pad to allow connection of the battery to external devices). The photolithographic procedure comprises the deposition of a photoresist layer (not shown) onto the surface of layer 14, treatment of the photoresist layer to form a mask, followed by etching of layer 14, and removal of the photoresist layer.

[0099] Referring to FIG. 5, a LiPON electrolyte layer 16 is deposited onto the cathode 14a as well as any uncovered surfaces of the cathode current collector 12a and the substrate 10 through radio-frequency sputtering to a thickness of 3 μm. An amorphous silicon (a-Si) layer 18 is deposited on the electrolyte layer 16 to a thickness of 1 μm using electron beam physical vapour deposition from a target having a purity of at least 99 atomic %. A platinum layer 20 is deposited on the silicon layer 18 to a thickness of 300 nm using direct-current sputtering from a target having a purity of at least 99.99 atomic %. The LiPON electrolyte layer 16, amorphous silicon layer 18 and platinum layer 20 are deposited sequentially without removing the sample from the vacuum chamber. This assists in preventing contamination of the interfaces between the layers 16, 18 and 20.

[0100] Referring to FIG. 6, the platinum layer 20 and the amorphous silicon layer 18 are etched in a single photolithographic procedure to provide an anode current collector 20a and an anode 18a respectively. The photolithographic procedure comprises the deposition of a photoresist layer (not shown) onto the surface of layer 20, treatment of the photoresist layer to form a mask, followed by reactive ion etching with an inductively coupled plasma comprising SF.sub.6, and removal of the photoresist layer. The footprint of the current collector 20a and the anode 18a on the substrate 10 is greater than that of the cathode 14a.

[0101] Referring to FIG. 7, the electrolyte layer 16 is etched using water as an etchant and the combined current collector 20a and anode 18a as a hard mask. The aqueous etchant tends to undercut the hard mask, such that the etched electrolyte layer 16a has a smaller footprint on the substrate 10 than the current collector 20a and the anode 18a. That is, the anode 18a tends to overhang the etched electrolyte layer 16a. However, the footprint of the etched electrolyte layer 16a remains greater than that of the cathode 14a, such that the cathode 14a is entirely enclosed by the cathode current collector 12a and the etched electrode layer 16a.

[0102] Referring to FIG. 8, the current collector 20a and the anode 18a are trimmed using a photolithographic process to provide a trimmed current collector 20b and a trimmed anode 18b. Thus, the footprint of the current collector and the anode on the substrate is reduced to match that of the etched electrolyte 16a (alternatively, the footprint of the current collector and the anode on the substrate may be reduced to be smaller than that of the etched electrolyte, as shown in FIG. 9, in which the footprint of trimmed current collector 20c and trimmed anode 18c is less than that of etched electrolyte 16a). That is, the trimmed anode 20b no longer overhangs the etched electrolyte 16a. The trimming procedure comprises the deposition of a photoresist layer (not shown) onto the surface of layer 20, treatment of the photoresist layer to form a mask, followed by reactive ion etching with an inductively coupled plasma comprising SF.sub.6, and removal of the photoresist layer.

[0103] It is thought that the trimming process provides one or both of the following advantages: [0104] The extent of overhang of the anode 18a over the etched electrolyte 16a is reduced or eliminated, such that the risk of a short circuit between cathode 14a and the trimmed anode 18b (which might otherwise have occurred, for example, through contact between the anode 18a and the cathode current collector 12a) is reduced; and/or [0105] Material at the perimeter of the anode that may have been damaged through the action of the aqueous etchant may be partly or wholly removed.

[0106] In an alternative example of the method according to the invention, battery components are assembled and configured as described above with reference to FIGS. 1-7, followed by the provision of a battery as shown in FIG. 10.

[0107] Referring to FIG. 10, in an alternative example of the method according to the invention, a trench 22 is created in the current collector and the anode, instead of trimming them. The trench lies within the perimeter of the current collector 20a and the anode 18a (as shown in FIG. 7) and forms a closed loop, dividing each of the current collector and the anode into an active portion and an inactive portion. The active portions 18d, 20d of the anode and the current collector are contained within the closed loop provided by the trench, while the inactive portions 18e and 20e of the anode and the current collector lie outside this loop. The outer perimeter of inactive portions 18e,20e effectively coincides with the perimeter of current collector 20a and anode 18a, as shown in FIG. 7.

[0108] Effectively, the trench 22 defines the outer perimeters of a modified current collector and modified anode.

[0109] The anode contact pad of the battery (not shown) is provided within the trench loop, so that when the battery is connected to an external device, active portions 18d,20d of the anode and current collector form part of the electrical circuit, while inactive portions 18e,20e of the anode and current collector are isolated from the electrical circuit. Thus, although portions 18e,20e of the anode and current collector may overhang the etched electrolyte 16a, the risk of a short circuit in the battery is reduced. Furthermore, although material at the outer perimeter portion 18e of the anode may have been damaged through the action of the aqueous etchant during the etching of the electrolyte layer, this material is isolated from the electrical circuit created when the battery is connected to an external device.

[0110] In general, the trench 22 is located directly opposite a section of the cathode 14a, although this is not the case for the portion of the trench 22 that defines the outline of the anode contact pad (not shown). That is, the majority of the trench typically lies within the footprint of the cathode 14a.

[0111] The trench is formed through the process of depositing a photoresist layer (not shown) onto the surface of current collector 20a (as shown in FIG. 7) and treating the photoresist layer to form a mask that defines the path to be followed by the trench. This is followed by reactive ion etching with an inductively coupled plasma comprising SF.sub.6, and removal of the photoresist layer.

[0112] The base of the trench is in the same plane as the interface between the anode and the electrolyte layer 16a. The sidewalls of the trench extend away from the electrolyte layer 16a and are aligned with each other. The width of the trench is typically 50 μm.

[0113] FIG. 11 shows a graph of multiple charge and discharge cycles measured from a battery such as that of FIG. 8, as a plot of voltage against time. This confirms good performance of the battery, indicating that the shaping processes used did not impede or impair its operation. In particular, it is surprising that the use of the combined current collector 20a and anode 18a as a hard mask during etching of the electrolyte layer 16 with water did not have an adverse effect on the performance of the amorphous silicon anode.

[0114] FIG. 12 shows a graph of data from multiple cycles, as a plot of charge and discharge capacities measured for consecutive cycles for a battery such as that of FIG. 8. The capacity is maintained at a reasonable level over the cycles, with only a small decline which is comparable with expected values for a similar conventionally-fabricated thin-film battery. Again, this confirms good performance of the battery, indicating that the shaping processes used did not impede or impair its operation. [0115] The anode current collector 20a provides an example of a first discrete layer element as formed in the method according to the first aspect of the invention; [0116] The anode 18a provides an example of a second discrete layer element as formed in the method according to the first aspect of the invention; [0117] The etched electrolyte layer 16a provides an example of a third discrete layer element as formed in the method according to the first aspect of the invention; [0118] The trimmed anode 18b provides an example of a modified second discrete layer element, as formed in an optional variant of the method according to the first aspect of the invention; [0119] Active portion 18d of the anode provides a further example of a modified second discrete layer element, as formed in a further optional variant of the method according to the first aspect of the invention.